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S6B0719
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
Sep. 2002. Ver. 0.8
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
S6B0719 Specification Revision History Version 0.0 0.1 0.2 Original Content Append pad center coordinate (refer to table 2) Append display data RAM map (refer to figure 8) Modify display data RAM map (refer to figure 8) Append reference circuit examples (refer to page 22) Change the low power consumption V0 = 13V -> 15V (refer to page 1) Modify page a ddress circuit description ; DB3, DB2 and DB1 are "H", but DB1 is "L" -> DB3, DB2 and DB0 are "H", but DB1 is "L" (refer to page 20) Modify set partial display duty ratio (refer to page 27) Add partial duty changing "waiting for discharging the LCD power levels (refer to figure 34) Change the condition of power consumption : (VDD = 3V, x6 boosting, V0 = 15V) (VDD = 3V, x5 boosting, V0 = 13V) (refer to page 1) Change the absolute maximum ratings of V0 and VOUT : 20V 17V (refer to page 50) Change the operating voltage of V0 and VOUT : 17V 15V (refer to page 1 and 51) Change the operating voltage of VDD : (2.4 to 5.5V) (2.4 to 3.6V) (refer to page 1 and 51) Modify Figure20 (refer to page 24) Change the operating voltage of VOUT : 17 V 15 V ( refer to page 51 ) TBD value is replaced in the DC characteristics (refer to page 1, 52 and 53 ) Change the low power consumption : TBD 200uA (VDD = 3V, x5 boosting, V0 = 13V) (refer to page 1) Change the low power consumption : TBD 10uA (Power save mode) (refer to page 1) Change the IDD2 (Display OFF) current: 100uA 200uA(refer to page 52) Change the IDDS2 current: 10uA 20uA (refer to page 53) ILB and Bump align key description added (refer to page 3) MPU Interface protocol 8080 and 6800 mode diagram added (refer to page 12) Re-sort the figure number. Data Transfer Read Timing Diagram modified.(refer to page 14) Change Reference Instruction Setup Flow (refer to page 47, Figure 36 ~ 40) Change RB/RA ratio of Regulator Resistor Select(refer to page 41) - change the bump specification (refer to page 3 ) Date Feb.1999 Mar.1999 May.1999
0.3
Jun.1999
0.4
Jan.2000
0.5
Jun. 2000
0.6
Sep. 2000
0.7
Mar. 2001
0.8
Sep. 2002
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S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
CONTENTS
INTRODUCTION ............................................................................................................................................ 1 BLOCK DIAGRAM ......................................................................................................................................... 2 PAD CONFIGURATION ................................................................................................................................. 3 PAD CENTER COORDINATES ...................................................................................................................... 5 PIN DESCRIPTION ........................................................................................................................................ 7 FUNCTIONAL DESCRIPTION .......................................................................................................................12 MICROPROCESSOR INTERFACE .........................................................................................................12 DISPLAY DATA RAM (DDRAM) ..............................................................................................................16 LCD DISPLAY CIRCUITS .......................................................................................................................19 LCD DRIVER CIRCUIT ...........................................................................................................................21 POWER SUPPLY CIRCUITS ..................................................................................................................23 REFERENCE CIRCUIT EXAMPLES........................................................................................................28 RESET CIRCUIT ....................................................................................................................................30 INSTRUCTION DESCRIPTION ......................................................................................................................31 SPECIFICATIONS .........................................................................................................................................52 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................52 DC CHARACTERISTICS ........................................................................................................................53 AC CHARACTERISTICS .........................................................................................................................57 REFERENCE APPLICATIONS ......................................................................................................................61 MICROPROCESSOR INTERFACE .........................................................................................................61 CONNECTIONS BETWEEN S6B0719 AND LCD PANEL .........................................................................62
3
S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
INTRODUCTION
The S6B0719 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 105 common and 160 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip display data RAM of 105 x 160 bits. It provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no external-operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
Driver Output Circuits - 105 common outputs / 160 segment outputs
Applicable Duty-ratios Programmable duty ratio 1/9 to 1/105 - - - - - - - - - - - - - - - - - Various partial display Partial window movi ng & data scrolling Applicable LCD bias 1/4 to 1/11 Maximum display area 105 x 160
On-chip Display Data RAM Capacity: 105 x 160 = 16,800 bits Bit data "1": a dot of display is illuminated Bit data "0": a dot of display is not illuminated
Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series or 8080-series Serial interface (only write operation) available
On-chip Low Power Analog Circuit On-chip oscillator circuit Voltage converter (x3, x4, x5 or x6) Voltage regulator (temperature coefficient: -0.05%/C or external input) On-chip electronic contrast control function (64 steps) Voltage follower (LCD bias: 1/4 to 1/11)
Operating Voltage Range Supply voltage (VDD): 2.4 to 3.6 V LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V 200 Typ. (VDD = 3V, x5 boosting, V0 = 13V, Internal power supply ON and display OFF) 20 Max. (during power save [standby] mode )
Low Power Consumption
Package Type Gold bumped chip or TCP
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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
BLOCK DIAGRAM
COM103 SEG159 SEG158 SEG157 : : SEG2 SEG1 SEG0 : COM0 COMS COMS
:
:
VDD V0 V1 V2 V3 V4 VSS
160 SEGMENT DRIVER CIRCUITS
106 COMMON DRIVER CIRCUITS
SEGMENT CONTROLLER
COMMON CONTROLLER
HPMB
V/F CIRCUIT PAGE ADDRESS CIRCUIT V/R RCIRCUIT COLUMN ADDRESS CIRCUIT DISPLAY DATA RAM 105 X 1 60 = 16,800 Bits LINE ADDRESS CIRCUIT DISPLAY TIMING GENERATOR CIRCUIT STATIC DRIVER MS CL SYNC M FRS FR
V0 VR INTRS VEXT REF
VOUT C1C1+ C2C2+ C3+ C4+ C5+ VCI
OSCILLATOR
V/C CIRCUIT INSTRUCTION DECODER & REGISTER
BUS HOLDER
STATUS REGISTER
MPU INTERFACE (PARALLEL & SERIAL)
Figure 1. Block Diagram
DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) RW_WR E_RD RS CS2 CS1B PS C68 RESETB
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S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
PAD CONFIGURATION
330 331 167 166
- - - - - - - - - -
- - - - - - - -
*2
Y
S6B 0719
(TOP VIEW)
*1
(0,0)
X
*3
360
- - - - - - - - - -
1
137
136
Figure 2. S6B0719 Chip Configuration Table 1. S6B0719 Pad Dimensions Size Item Chip size Pad pitch Pad No. X 29 to 108 1 to 28, 109 to 136, 137 to 360 30 to 107 138 to 165, 332 to 359 Bumped pad size 3 to 27, 110 to 134 169 to 328 1, 2, 28, 29, 108, 109, 135, 136, 167, 168, 329 and 330 137, 166, 331 and 360 Bumped pad height 1 to 360 9370 Y 2220 Unit
70 (Min.) 54 (Min.) 55 73 39 65 73 73 39 73 73 65 m
14 (Typ.)
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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
COG Align Key Coordinate
ILB Align Key Coordinate(with Gold Bump*)
30m 30m 30m
42m
108m
108m
42m
30m 30m 30m
42m
(-4131.6, +622.75)
108m
(-4030.65, -374.4)
* When designing electrode pattern must be prohibited on this area (ILB Align Key). If ITO pattern is used for routing over this area, it can be happened pattern-short through gold bumped pattern on ILB Align Key.
108m (+4135.6, -633.0)
42m
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S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
PAD CENTER COORDINAT ES
Table 2. Pad Center Coordinates [Unit: m]
NO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NAME
DUMMY DUMMY COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COMS DUMMY DUMMY FRS FR TEST1 TEST2 TEST3 CL M SYNC VSS HPMB MS VDD PS C68 VSS CS1B CS2 VDD RESETB RS VSS
X
-4453 -4373 -4293 -4239 -4185 -4131 -4077 -4023 -3969 -3915 -3861 -3807 -3753 -3699 -3645 -3591 -3537 -3483 -3429 -3375 -3321 -3267 -3213 -3159 -3105 -3051 -2997 -2917 -2775 -2695 -2625 -2555 -2485 -2415 -2345 -2275 -2205 -2135 -2065 -1995 -1925 -1855 -1785 -1715 -1645 -1575 -1505 -1435 -1365 -1295
Y
-985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985
NO
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
NAME
RW_WR E_RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VDD VCI VCI VSS VSS VSS VSS VOUT VOUT C5+ C5+ C3+ C3+ C1C1C1+ C1+ C2+ C2+ C2C2C4+ C4+ VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 VR
X
-1225 -1155 -1085 -1015 -945 -875 -805 -735 -665 -595 -525 -455 -385 -315 -245 -175 -105 -35 35 105 175 245 315 385 455 525 595 665 735 805 875 945 1015 1085 1155 1225 1295 1365 1435 1505 1575 1645 1715 1785 1855 1925 1995 2065 2135 2205
Y
-985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985
NO
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
NAME
VR VSS REF VEXT VDD INTRS VSS DUMMY DUMMY COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 DUMMY DUMMY DUMMY COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14
X
2275 2345 2415 2485 2555 2625 2695 2775 2917 2997 3051 3105 3159 3213 3267 3321 3375 3429 3483 3537 3591 3645 3699 3753 3807 3861 3915 3969 4023 4077 4131 4185 4239 4293 4373 4453 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560
Y
-985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -809 -729 -675 -621 -567 -513 -459 -405 -351 -297 -243 -189 -135 -81
NO
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
NAME
COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS DUMMY DUMMY DUMMY SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
X
4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4560 4453 4373 4293 4239 4185 4131 4077 4023 3969 3915 3861 3807 3753 3699 3645 3591 3537 3483 3429 3375 3321 3267 3213 3159 3105 3051 2997 2943 2889 2835 2781 2727 2673 2619
Y
-27 27 81 135 189 243 297 351 405 459 513 567 621 675 729 809 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985
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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
Table 2 (Continued) [Unit: m] NO
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
NAME
SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81
X
2565 2511 2457 2403 2349 2295 2241 2187 2133 2079 2025 1971 1917 1863 1809 1755 1701 1647 1593 1539 1485 1431 1377 1323 1269 1215 1161 1107 1053 999 945 891 837 783 729 675 621 567 513 459 405 351 297 243 189 135 81 27 -27 -81
Y
985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985
NO
251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
NAME
SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
X
-135 -189 -243 -297 -351 -405 -459 -513 -567 -621 -675 -729 -783 -837 -891 -945 -999 -1053 -1107 -1161 -1215 -1269 -1323 -1377 -1431 -1485 -1539 -1593 -1647 -1701 -1755 -1809 -1863 -1917 -1971 -2025 -2079 -2133 -2187 -2241 -2295 -2349 -2403 -2457 -2511 -2565 -2619 -2673 -2727 -2781
Y
985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985
NO
301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
NAME
SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 DUMMY DUMMY DUMMY COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70
X
-2835 -2889 -2943 -2997 -3051 -3105 -3159 -3213 -3267 -3321 -3375 -3429 -3483 -3537 -3591 -3645 -3699 -3753 -3807 -3861 -3915 -3969 -4023 -4077 -4131 -4185 -4239 -4293 -4373 -4453 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560
Y
985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 985 809 729 675 621 567 513 459 405 351 297 243 189 135 81 27 -27 -81 -135 -189 -243
NO
351 352 353 354 355 356 357 358 359 360
NAME
COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 DUMMY
X
-4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560 -4560
Y
-297 -351 -405 -459 -513 -567 -621 -675 -729 -809
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S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
PIN DESCRIPTION
Table 3. Power Supply Pins Name VDD Vss I/O Supply Supply Power supply Ground LCD drivers supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. Voltages should have the following relationship: V0 V1 V2 V3 V4 Vss When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias V1 (N-1)/N x V0 V2 (N-2)/N x V0 V3 2/N x V0 V4 1/N x V0 Description
V0 V1 V2 V3 V4
I/O
NOTE : *N = 4 to 11
Table 4. LCD Driver Supply Pins Name C1-, C2C1+, C2+ C3+, C4+ C5+ VOUT VCI VR I/O I/O I/O I/O I I Description Capacitor negative connection pins for voltage converter Capacitor positive connection pins for voltage converter Voltage converter input/output pin Voltage converter input voltage pin Voltages should have the following relationship: VDD VCI V0 V0 voltage adjustment pin It is valid only when on-chip resistors are not used. (INTRS = "L") Selects the external VREF voltage via VEXT pin - REF = "L": using the external VREF - REF = "H": using the internal VREF Externally input reference voltage (VREF) for the internal voltage regulator. It is valid only when REF is "L".
REF
I
VEXT
I
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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
Table 5. System Control Pins Name I/O Description Master / Slave operations select pin - MS = "H": master operation - MS = "L": slave operation The following table depends on the MS status. MS I MS H L Internal analog circuits Oscillator Enabled Disabled Power supply Enabled Disabled CL Output Input Display timing signals SYNC Output Input M Output Input
CL
I/O
Display clock input / output pin When the S6B0719 is used in master / slave mode (multi-chip), the CL pins must be connected each other. Display sync input / output pin When the S6B0719 is used in master/slave mode (multi-chip), the SYNC pins must be connected each other. LCD AC input / output pin When the S6B0719 is used in master/slave mode (multi-chip), the M pins must be connected each other. Static driver common output pin This pin is used together with the FRS pin. Static driver segment output pin This pin is used together with the FR pin. Internal resistors select pin This pin selects the resistors for adjusting V0 voltage level. - INTRS = "H": use the internal resistors. - INTRS = "L": use the external resistors. VR pin and external resistive divider control V0 voltage. Power control pin of the power supplies circuit for LCD driver - HPMB = "L": high power mode - HPMB = "H": normal mode This pin is valid in master operation. Test pins Don't use these pins.
SYNC
I/O
M
I/O
FR FRS
O O
INTRS
I
HPMB
I
TEST1 to TEST3
I
NOTE: DUMMY - These pins should be opened (floated).
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S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
Table 6. Microprocessor Interface Pins Name RESETB I/O I Description Reset input pin When RESETB is "L", initialization is executed. Parallel / Serial data input select input PS Interface mode Parallel Serial Data / instruction RS RS Data Read / Write E_RD RW_WR Write only Serial clock
PS
I
H L
DB0 to DB7 SID (DB7)
SCLK (DB6)
*NOTE: When PS is "L", DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either "H" or "L". C68 I Microprocessor interface select input pin - C68 = "H": 6800-series MPU interface - C68 = "L": 8080-series MPU interface Chip select input pins Data / instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin - RS = "H": DB0 to DB7 are display data - RS = "L": DB0 to DB7 are control data Read / Write execution control pin C68 H RW_WR I L 8080-series /WR MPU Type 6800-series RW_WR RW Description Read/Write control input pin - RW = "H": read - RW = "L": write Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal.
CS1B CS2
I
RS
I
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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
Table 6. (Continued) Name I/O Read / Write execution control pin C68 MPU Type E_RD Description Read / Write control input pin - RW = "H": When E is "H", DB0 to DB7 are in an output status. - RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", DB0 to DB7 are in an output status. Description
E_RD
I
H
6800-series
E
L
8080-series
/RD
DB0 to DB7
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS = "L"); - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID). When chip select is not active, DB0 to DB7 may be high impedance.
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S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
Table 7. LCD driver output pins Name I/O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data SEG0 to SEG159 H O H L L Power save mode M H L H L Segment driver output voltage Normal display V0 Vss V2 V3 Vss Reverse display V2 V3 V0 Vss Vss
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data COM0 to COM103 H O H L L Power save mode M H L H L Common driver output voltage Vss V0 V1 V4 Vss
COMS
O
Common output for the icons The output signals of two pins are same. When not used, these pins should be left open.
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160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input There are CS1B and CS2 pins for chip selection. The S6B0719 can interface with an MPU only when CS1B is "L" and CS2 is "H". When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface The S6B0719 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8. Parallel / Serial Interface Mode. PS H L Type Parallel Serial CS1B CS1B CS1B CS2 CS2 CS2 C68 H L *x Interface mode 6800-series MPU mode 8080-series MPU mode Serial-mode
*x: Don't care
Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 10. Table 9. Microprocessor Selection for Parallel Interface C68 H L CS1B CS1B CS1B CS2 CS2 CS2 RS RS RS E_RD E /RD RW_WR RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Table 10. Parallel Data Transfer Common RS H H L L 6800-series E_RD (E) H H H H RW_WR (RW) H L H L 8080-series E_RD (/RD) L H L H RW_WR (/WR) H L H L Display data read out Display data write Register status read Writes to internal register (instruction) Description
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S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
CS1B
CS2
RS
RW
E
DB Command Write Data Write Status Read Data Read
Figure 3. 6800-Series MPU Interface protocol (PS="H", C68="H")
CS1B
CS2
RS
/WR
/RD
DB Command Write Data Write Status Read Data Read
Figure 4. 8080-Series MPU Interface Protocol (PS="H", C68="L")
Serial Interface (PS = "L") When the S6B0719 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8 -bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended.
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S6B0719
CS1B
CS2
SID
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCLK
RS
Figure 5. Serial Interface Timing Busy Flag The Busy Flag indicates whether the S6B0719 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
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Data Transfer The S6B0719 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WR
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/WR
BUS HOLDER
N
D(N)
D(N+1)
D(N+2)
D(N+3)
COLUMN ADDRESS
N
N+1
N+2
N+3
Figure 6. Write Timing
MPU signals
RS /WR /RD DB0 to DB7 N Dummy D(N) D(N+1) D(N+2)
Internal signals
/WR /RD BUS HOLDER COLUMN ADDRESS N N D(N) N+1 D(N+1) N+2 D(N+2) N+3
Figure 7. Read Timing
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S6B0719
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 105-row by 160-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 105 rows are divided into 13 pages of 8 lines and the 13th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
DB0 DB1 DB2 DB3 DB4
0 1 0 1 0
0 0 1 0 0
1 0 1 1 0
------
0 1 0 0 1
COM0 COM1 COM2 COM3 COM4 LCD Display
------
Display Data RAM
Figure 8. RAM-to-LCD Data Transfer Page Address Circuit This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4 -bit Page Address register changed by only the "Set Page" instruction. Page Address 13 (DB3, DB2 and DB0 are "H", but DB1 is "L") is a special RAM area for the icons and display data DB0 is only valid.
Line Address Circuit This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 7. It incorporates 7-bit line address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the Line A ddress for transferring the 160-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access Line Address of icons.
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Column Address Circuit Column Address circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not incremented and locked if a non-existing address above 9FH. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the Column Address counter is independent of page address register. ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following figure 7. SEG Output Column address [Y7:Y0] Display data LCD panel display ( ADC = 0 ) SEG 0 00H 1 SEG 1 01H 0 SEG 2 02H 1 SEG 3 03H 0 ... ... ... ... ... ... SEG 156 9CH 1 SEG 157 9DH 1 SEG 158 9EH 0 SEG 159 9FH 0
LCD panel display ( ADC = 1 )
... ...
Figure 9. The Relationship between the Column Address and The Segment Outputs
Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
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S6B0719
Page Address
DB3 DB2 DB1 DB0
Data
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31
0
0
0
0
Page 0
End = 07H
Start = 08H 1/105 Duty 1/97 Duty
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0
ADC=0 ADC=1 00 01 02 03 04 05 9F 9E 9D 9C 9B 9A SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
Page 9
Page 10
Page 11
Page 12
Page 13 ---------------------9A 9B 9C9D 9E 9F 05 04 03 02 01 00 SEG158 SEG157 SEG156 SEG155 SEG154 SEG159
48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H -
COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COMS
Column Address LCD Segment Output
Initial start line address = 08H
Figure 10. Display Data RAM Map
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LCD DISPLAY CIRCUITS
Oscillator This is completely on-chip Oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the display data latch circuit in synchronization latches the 160-bit display data with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame or the line changes the phase of M by setting internal instruction. Driving waveform and internal timing signal are shown in figure 10. In a multiple-chip configuration, the slave chip requires the CL, M and SYNC signals from the master. Table 11 shows the CL, SYNC, and M status. Table 11. Master and Slave Timing Signal Status Operation mode Master Slave Oscillator ON (internal clock used) OFF (external clock used) CL Output Input SYNC Output Input M Output Input
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S6B0719
84
85
1
2
3
4
5
6
7
8
9
10
11
12
78
79
80
81
82
83
84
85
1
2
3
4
5
6
CL
FR
M
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 11. 2-frame AC Driving Waveform (Duty Ratio = 1/85)
84
85
1
2
3
4
5
6
7
8
9
10
11
12
78
79
80
81
82
83
84
85
1
2
3
4
5
6
CL
FR
M
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 12. N-line Inversion Driving Waveform (N = 5, Duty Ratio = 1/85)
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LCD DRIVER CIRCUIT
106-channel common driver and 160-channel segment driver configure this driver circuit. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD
M
VSS V0 V1 V2
COM0
V3 V4 VSS V0 V1 V2
COM1
V3 V4 VSS V0 V1 V2
COM8 COM9 COM10 COM11
COM2
V3 V4 VSS V0 V1 V2
SEG0
COM12 COM13 COM14
V3 V4 VSS V0 V1 V2
SEG1
COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
V3 V4 VSS V0 V1 V2
SEG2
V3 V4 VSS
Figure 13. Segment and Common Timing
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S6B0719
Partial Display on LCD The S6B0719 realizes the partial display function on LCD with low-duty driving for saving power consumption and showing the various display duties. To show the various display duties on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages
-- COMS -- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23
Figure 14. Reference Example for Partial Display (Display Duty = 25)
-- COMS ------------------------COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Figure 15. Partial Display (Partial Display Duty = 9, Initial COM0 = 0)
-- COMS -- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23
Figure 16. Moving Display (Partial Display Duty = 9, Initial COM0 = 8)
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POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction Description". Table 12 shows the referenced combinations in using Power Supply circuits. Table 12. Recommended Power Supply Combinations User setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power control (VC VR VF) 111 V/C circuits ON V/R circuits ON V/F circuits ON VOUT V0 V1 to V4
Open
Open
Open
011
OFF
ON
ON
External input External input Open
Open
Open
001 000
OFF OFF
OFF OFF
ON OFF
Open External input
Open External input
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S6B0719
Voltage Converter Circuits These circuits boost up the electric potential between VCI and Vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by "Set DC-DC Step-up" instruction. When the higher level is selected by instruction, VOUT voltage is not valid. [C1 = 1.0 to 4.7 F] Vss VOUT C5+ C3+ C1C1+ C2+
+
+
Vss C1 VOUT C5+ C3+ VOUT= 3 x VCI
+
C1
VOUT = 4 x VCI
+ +
C1 C1
+
C1C1+
C1 C2+
C1
VCI Vss
+
C1
VCI Vss
C2 C4+
-
C2 C4+
-
Figure 17. Three Times Boosting Circuit
Figure 18. Four Times Boosting Circuit
Vss VOUT C5+ C3+ C1C1+ C2+
+
Vss C1 VOUT = 5 x VCI VOUT C5+
+
VOUT = 6 x VCI C1
C1
+ +
+ -
C3+ C1 C1C1 C1+ C2+ VCI C2 C1 Vss C4+
+ +
C1 C1
+
C1
+ +
C1 C1
VCI Vss
C2 C4+
+
Figure 19. Five Times Boosting Circuit
Figure 20. Six Times Boosting Circuit
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Voltage Regulator Circuits The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 19, it is necessary to be applied internally or externally. For the Eq. 6-1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 6-2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta = 25C is shown in Table 13.
V0 = { 1 + (Rb / Ra) } x VEV [V] ------ (Eq. 6-1)
VEV = { 1 - (63 - ) / 200 } x 2.0 = 1.69 [V] ------ (Eq. 6.2) Table 13. VREF Voltage at Ta = 25C REF 1 0 Temp. coefficient -0.05% / C External input VREF [V] 2.0 VEXT
VOUT
+ VEV V0 Rb VR
Ra VSS
GND
Figure 21. Internal Voltage Regulator Circuit
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S6B0719
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and V SS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". 3-bit data settings (R2 R1 R0) 000 1 + (Rb / Ra) 2.6 001 3.4 010 4.2 011 5.0 100 5.8 101 6.6 110 7.4 111 8.3
Table 14. Internal Rb / Ra ratio Depending on 3-bit Data (R2 R1 R0)
Figure 22 shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C.
V0 Voltage [V] 16.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 0 8 16 24 32 40 48 56 63 Electronic volume register (0 to 63)
Figure 22. V0 Voltage by 1 + (Rb / Ra) and Electronic Volume Levels
(1, 1, 1) (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0)
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In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA
From Eq. 6.1 10 = { 1 + (Rb / Ra) } x VEV
[V] ------ (Eq. 6.3) [V] ------ (Eq. 6.4)
From Eq. 6.2 VEV = { 1 - (63 - 32) / 200 } x 2.0 = 1.69 From requirement 3 10 / ( Ra + Rb) = 1 [uA] ------ (Eq. 6.5)
From equations Eq. 6.3, 6.4 and 6.5 Ra = 1.69 [M] Rb = 8.31 [M] Table 15 shows the range of V0 depending on the above requirements. Table 15. The Range of V0 Electronic volume level 0 V0 8.10 ....... ....... 32 10.00 ....... ....... 63 11.83
Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and these output impedance are converted by the Voltage Follower for increasing drive capability. Table 16 shows the relationship between V1 to V4 level and each duty ratio. Table 16. V1 to V4 Level LCD bias 1/N V1 (N-1)/N x V0 V2 (N-1)/N x V0 V3 2/N x V0 V4 1/N x V0 Remarks N = 4 to 11
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S6B0719
REFERENCE CIRCUIT EXAMPLES
[C1 = 1.0 to 4.7 [ C2 = 0.1 to 0.47 [ F], F]]
When using internal regulator resistors When not using internal regulator resistors
VDD MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR C2 C2 C2 C2 C2 VSS + + + + + V0 V1 V2 V3 V4 VSS INTRS
VDD MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ Rb VR V0 V1 V2 V3 V4 INTRS VSS
C1
C1 C1 C1 C1
C1
C1 C1 C1 C1 Ra
C1
C1
C2 C2 C2 C2 C2
+ + + + +
Figure 23. When Using all LCD Power Circuits (6-Time V/C: ON, V/R: ON, V/F: ON)
When using internal regulator resistors When not using internal regulator resistors
VDD MS
External power Supply
VDD INTRS
External power Supply
MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ Rb VR V0 V1 V2 V3 V4
INTRS
VSS
VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR
Ra C2 C2 C2 C2 C2 VSS + + + + +
C2 C2 C2 C2 C2 VSS
+ + + + +
V0 V1 V2 V3 V4
Figure 24. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON)
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VDD MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR + + + + + VSS Figure 25. When Using only Voltage Follower Circuit (V/C: OFF, V/R: OFF, V/F: ON) V0 V1 V2 V3 V4 INTRS
External power Supply
VDD MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR
External power Supply
INTRS
V0 V1 V2 V3 V4
VSS Figure 26. When Not Using all LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: OFF)
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S6B0719
RESET CIRCUIT
Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", following procedure is occurred. Page address: 0 Column address: 0 Modify-read: OFF Display ON / OFF: OFF Initial display line: 0 (first) Initial COM0 register: 0 (COM0) Partial display duty ratio: 1/105 Reverse display ON / OFF: OFF (normal) n-line inversion register: 0 (disable) Entire display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) DC-DC step up: 3 times converter circuit = (0, 0) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage control register: (EV5, EV4, EV3, EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0) LCD bias ratio: 1/11 SHL select: OFF (normal) ADC select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Oscillator status: OFF Power save mode: release When RESET instruction is issued, following procedure is occurred. Page address: 0 Column address: 0 Modify-read: OFF Initial display line: 0 (First) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage control register (EV5, EV4, EV3, EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) While RESETB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
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INSTRUCTION DESCRIPTION
Table 17. Instruction Table Instruction
Read display data Write display data Read status Set page address Set column address MSB Set column address LSB Set modify-read Reset modify-read Display ON / OFF Set initial display line register RS 1 1 0 0 0 0 0 0 0 0 0 0 Set initial COM0 register Set partial display duty ratio Set N-line inversion Release N-line inversion Reverse display ON / OFF Entire display ON / OFF 0 0 0 0 0 0 0 0 RW 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BS UY 1 0 0 1 1 1 0 x 0 x 0 x 0 x 1 1 1 ADC 0 0 0 1 1 0 1 S6 1 C6 1 D6 1 x 1 0 0 O N 1 0 0 1 1 1 0 S5 0 C5 0 D5 0 x 1 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
x : Don't care Description
Read data from DDRAM Write data into DDRAM
Read data Write data RS E 1 1 0 0 0 0 0 S4 0 C4 0 D4 0 N4 0 0 0 0 P3 Y7 Y3 0 1 1 0 S3 0 C3 1 D3 1 N3 0 0 0 0 P2 Y6 Y2 0 1 1 0 S2 1 C2 0 D2 1 N2 1 1 1 0 P1 Y5 Y1 0 1 1 x S1 x C1 x D1 x N1 0 1 0 0 P0 Y4 Y0 0 0 D x S0 x C0 x D0 x N0 0 REV EON
Read the internal status Set page address Set column address MSB Set column address LSB Set modify-read mode release modify-read mode D = 0: display OFF D = 1: display ON 2-byte instruction to specify the initial display line to realize vertical scrolling 2-byte instruction to specify the initial COM0 to realize window scrolling 2-byte instruction to set partial display duty ratio 2-byte instruction to set n-line inversion register Release N-line Inversion mode REV = 0: normal display REV = 1: reverse display EON = 0: normal display EON = 1: entire display ON
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Table 17. Instruction Table (Continued) Instruction
Power control Select DC-DC step-up Select regulator resistor Set electronic volume register Select LCD bias SHL select RS 0 0 0 0 0 0 0 RW 0 0 0 0 0 0 0 DB7 0 0 0 1 x 0 1 DB6 0 1 0 0 x 1 1 DB5 1 1 1 0 EV5 0 0 DB4 0 0 0 0 EV4 1 0 DB3 1 0 0 0 EV3 0 SHL DB2 VC 1 R2 0 EV2 B2 x DB1 VR DC1 R1 0 EV1 B1 x DB0 VF DC0 R0 1 EV0 B0 x
Description
Control power circuit operation Select the step-up of the internal voltage converter Select internal resistance ratio of the regulator resistor 2-byte instruction to specify the electronic volume register Select LCD bias COM bi-directional selection SHL = 0: normal direction SHL = 1: reverse direction SEG bi-directional selection ADC = 0: normal direction ADC = 1: reverse direction 2-byte instruction to specify the static indicator mode Start the built-in oscillator P = 0: standby mode P = 1: sleep mode Release power save mode Initialize the internal functions No operation Don't use this instruction.
ADC select Set static indicator mode Set static indicator register Oscillator ON start Set power save mode Release power save mode Reset NOP Test instruction
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 x 1 1 1 1 1 1
0 0 x 0 0 1 1 1 1
1 1 x 1 1 1 1 1 1
0 0 x 0 0 0 0 0 1
0 1 x 1 1 0 0 0 x
0 1 x 0 0 0 0 0 x
0 0 S1 1 0 0 1 1 x
ADC SM S0 1 P 1 0 1 x
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Read Display Data 8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the column address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS 1 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read data
Write Display Data 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is incremented by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write data
Set Page Address Set Column Address Data W rite Column = Column +1 Yes
Set Page Address Set Column Address Dummy Data Read Column = Column +1 Data Read Column = Column +1 Yes
Data Write Continue ? No Optional Status
Data Read Continue ? No Optional Status
Figure 27. Sequence for Writing Display Data
Figure 28. Sequence for Reading Display Data
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S6B0719
Read Status Indicates the internal status of the S6B0719 RS 0 RW 1 DB7 BUSY DB6 ADC DB5 ON DB4 RES DB3 0 DB2 0 DB1 0 DB0 0
Flag BUSY
Description The device is busy when internal operation or reset Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG159 SEG0), 1: normal direction (SEG0 SEG159) Indicates display ON / OFF status 0: display ON, 1: display OFF Indicates the initialization is in progress by RESETB signal 0: chip is active, 1: chip is being reset.
ADC ON RES
Set Page Address Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address doesn't effect to the display status. RS 0 P3 0 0 0 : 1 1 1 1 1 1 RW 0 P2 0 0 0 : 0 0 0 1 1 1 DB7 1 P1 0 0 1 : 0 1 1 0 0 1 DB6 0 P0 0 1 0 : 1 0 1 0 1 0 DB5 1 DB4 1 DB3 P3 DB2 P2 DB1 P1 DB0 P0
Selected page 0 1 2 : 10 11 12 13 14 15
Description
Accessible pages for displaying dot-matrix display data
Accessible page for displaying icons Not accessible page. Do not use these pages.
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Set Column Address Sets the Column Address of display RAM from the microprocessor into the Column Address register. Along with the Column Address, the Column A ddress defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically incremented. Set Column Address MSB RS 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 Y7 DB2 Y6 DB1 Y5 DB0 Y4
Set Column Address LSB RS RW DB7 0 0 0
DB6 0
DB5 0
DB4 0
DB3 Y3
DB2 Y2
DB1 Y1
DB0 Y0
Y7 0 0 0 : : : 1 1 1 1 1 1
Y6 0 0 0 : : : 0 0 0 0 0 0
Y5 0 0 0 : : : 0 0 0 1 1 1
Y4 0 0 0 : : : 1 1 1 0 0 0
Y3 0 0 0 : : : 1 1 1 0 0 0
Y2 0 0 0 : : : 1 1 1 0 0 0
Y1 0 0 1 : : : 0 1 1 0 0 1
Y0 0 1 0 : : : 1 0 1 0 1 0
Selected column address 0 1 2 : : : 157 158 159 Not accessible column
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Set Modify-Read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Reset Modify-Read This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify-read instruction is started. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
Set Page Address Set Column Address (N) Set Modify-Read Dummy Read Data Read Data Process Data Write No Change Complete ? Yes Reset Modify-Read Return Column Address (N)
Figure 29. Sequence for Cursor Display
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Display ON / OFF Turns the Display ON or OFF RS RW DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 D
0 0 D = 1: display ON D = 0: display OFF
Set Initial Display Line Register Sets the line address of display RAM to determine the initial display line using 2 -byte instruction. The RAM display data is displayed at the top row (COM0) of LCD panel. The 1 Instruction RS 0 The 2
nd st
RW 0 Instruction RW 0 S5 0 0 : 1 1 1 : 1
DB7 0
DB6 1
DB5 0
DB4 0
DB3 0
DB2 0
DB1 x
DB0 x
RS 0 S6 0 0 : 1 1 1 : 1
DB7 x S4 0 0 : 0 0 0 : 1
DB6 S6 S3 0 0 : 0 0 1 : 1
DB5 S5 S2 0 0 : 1 1 0 : 1
DB4 S4 S1 0 0 : 1 1 0 : 1
DB3 S3 S0 0 1 : 0 1 0 : 1
DB2 S2
DB1 S1
DB0 S0
Selected line address 0 1 : 102 103 No operation
Setting Initial Display Line Start 1 Instruction (2-Byte Instruction for Mode Setting) 2
nd st
Instruction (2-Byte Instruction for Register Setting) Setting Initial Display Line End
Figure 30. The Sequence for Setting the Initial Display Line
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Set Initial COM0 Register Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the window moving without the change of display data. The 1 Instruction RS RW 0
nd st
DB7 0
DB6 1
DB5 0
DB4 0
DB3 0
DB2 1
DB1 x DB1 C1 Initial COM0 COM0 COM1 COM2 : COM101 COM102 COM103
DB0 x DB0 C0
0
The 2 Instruction RS RW 0 C6 0 0 0 : 1 1 1 1 : 1 0 C5 0 0 0 : 1 1 1 1 : 1
DB7 x C4 0 0 0 : 0 0 0 0 : 1
DB6 C6 C3 0 0 0 : 0 0 0 1 : 1
DB5 C5 C2 0 0 0 : 1 1 1 0 : 1
DB4 C4 C1 0 0 1 : 0 1 1 0 : 1
DB3 C3 C0 0 1 0 : 1 0 1 0 : 1
DB2 C2
No operation
Setting Initial COM0 Start 1st Instruction (Mode Setting) 2nd Instruction (Initial COM0 Setting) Setting Initial COM0 End end
Figure 31. Sequence for Setting the Initial COM0
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Set Partial Display Duty Ratio Sets the duty ratio within range of 9, 17 and 32 to 105 to realize Partial Display by using the 2-byte instruction. The 1 Instruction RS 0 The 2
nd st
RW 0 Instruction RW 0 D5 0 0 1 1 : 0 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 1
DB2 0
DB1 x
DB0 x
RS 0 D6 0 0 0 0 : 1 1
DB7 x D4 0 1 0 0 : 1 1
DB6 D6 D3 1 0 0 0 : 0 0
DB5 D5 D2 0 0 0 0 : 1 1
DB4 D4 D1 0 0 0 0 : 0 0
DB3 D3 D0 1 1 0 1 : 0 1
DB2 D2
DB1 D1
DB0 D0
Selected partial duty ratio 1/9 1/17 1/32 1/33 : 1/104 1/105 No operation
Other combinations
Setting Partial Display Start 1 st Instruction (Mode Setting)
nd
2
Instruction (Partial Display Duty Setting) Setting Partial Display End end
Figure 32. Sequence for Setting Partial Display
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Set N-line Inversion Register Sets the inverted line number within range of 2 to 32 to improve the display quality by controlling the phase of the internal LCD AC signal (M) by using the 2-byte instruction. The 1 Instruction RS 0 The 2
nd st
RW 0 Instruction RW 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 1
DB2 1
DB1 x
DB0 x
RS 0
DB7 x N2 0 0 0 0 : 1 1 1
DB6 x N1 0 0 1 1 : 0 1 1
DB5 x N0 0 1 0 1 : 1 0 1
DB4 N4
DB3 N3
DB2 N2
DB1 N1
DB0 N0
N4 0 0 0 0 : 1 1 1
N3 0 0 0 0 : 1 1 1
Selected n-line inversion 0-line inversion (frame inversion) 2-line inversion 3-line inversion 4-line inversion : 30-line inversion 31-line inversion 32-line inversion
Setting N-Line Inversion Start 1st Instruction (Mode Setting) 2nd Instruction (N-Line Inversion Setting) Setting N-Line Inversion End
Figure 33. Sequence for Setting Partial Display Release N-line Inversion Returns to the frame inversion condition from the n-line inversion condition. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
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Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS 0 REV 0 (normal) 1 (reverse) RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
RAM bit data = "1" LCD pixel is illuminated LCD pixel is not illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the reverse Display ON / OFF instruction. RS 0 EON 0 (Normal) 1 (Entire) RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON
RAM bit data = "1" LCD pixel is illuminated LCD pixel is illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
Power Control Selects one of eight power circuit functions by using 3 -bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
VC 0 1
VR
VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON
0 1 0 1
Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
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Select DC/DC Step-up Selects one of 4 DC/DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial display function. RS 0 RW 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 DC1 DB0 DC0
DC1 0 0 1 1
DC0 0 1 0 1
Selected DC-DC converter circuit 3 times boosting circuit 4 times boosting circuit 5 times boosting circuit 6 times boosting circuit
Regulator Resistor Select Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 15. RS 0 R2 0 0 0 0 1 1 1 1 RW 0 R1 0 0 1 1 0 0 1 1 DB7 0 R0 0 1 0 1 0 1 0 1 DB6 0 DB5 1 DB4 0 DB3 0 [Rb / Ra] ratio 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.3 DB2 R2 DB1 R1 DB0 R0
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Set Electronic Volume Register Consists of 2 -byte instruction. The 1 instruction sets Electronic Volume mode, the 2 one updates the contents of Electronic Volume register. After second instruction, Electronic Volume mode is released. The 1 Instruction RS 0 The 2
nd st st nd
RW 0 Instruction RW 0
DB7 1
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 1
RS 0
DB7 x EV3 0 0 : : 1 1
DB6 x EV2 0 0 : : 1 1
DB5 EV5
DB4 EV4
DB3 EV3
DB2 EV2
DB1 EV1
DB0 EV0
EV5 0 0 : : 1 1
EV4 0 0 : : 1 1
EV1 0 0 : : 1 1
EV0 0 1 : : 0 1
Reference voltage () 0 1 : : 62 63
Setting Electronic Volume Start 1st Instruction for Mode Setting 2nd Instruction for Register Setting Setting Electronic Volume End
Figure 34. Sequence for Setting the Electronic Volume
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Select LCD Bias Selects LCD Bias ratio of the voltage required for driving the LCD. RS 0 B2 0 0 0 0 1 1 1 1 RW 0 B1 0 0 1 1 0 0 1 1 DB7 0 B0 0 1 0 1 0 1 0 1 DB6 1 DB5 0 DB4 1 DB3 0 DB2 B2 DB1 B1 DB0 B0
Selected LCD bias 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11
SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x
SHL = 0: normal direction (COM0 COM103) SHL = 1: reverse direction (COM103 COM0)
ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
ADC = 0: normal direction (SEG0 SEG159) ADC = 1: reverse direction (SEG159 SEG0)
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Set Static Indicator State Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte instruction (set Static Indicator register) to be valid. The first byte sets the Static Indicator ON / OFF. When it is on, the second byte updates the contents of Static Indicator register without issuing any other instruction and this Static Indicator state is released after setting the data of indicator register. The 1 Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 0 DB0 SM 0 0 1 SM = 0: static indicator OFF SM = 1: static indicator ON The 2
nd st
Instruction: Set Static Indicator Register RW 0 S1 0 0 1 1 DB7 x S0 0 1 0 1 DB6 x DB5 x DB4 x DB3 x DB2 x DB1 S1 DB0 S0
RS 0
Status of static indicator output OFF ON (about 0.5 second blinking) ON (about 1 second blinking ) ON (always ON)
Oscillator ON Start This instruction enables the built-in oscillator circuit. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply that is initialized by the RESETB pin. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
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Power Save The S6B0719 enters the Power Save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. Set Power Save Mode RS RW DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 P 0 0 P = 0: standby mode P = 1: sleep mode
Release Power Save Mode RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Set Power Save Mode
Sleep Mode Oscillator Circuits: OFF Static Driver: Disable LCD Power Supply Circuits: OFF All COM / SEG Output Level: VSS Consumption Current < 2A
Standby Mode Oscillator Circuits: ON Static Driver: Enable LCD Power Supply Circuits: OFF All COM / SEG Output Level: VSS Consumption Current < 10 A
Release Power Save Mode
Release Sleep Mode
Release Standby Mode
Figure 35. Power Save Routine
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NOP Non-operation RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
Test Instruction This instruction is for testing IC. Please do not use it. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x
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Referential Instruction Setup Flow: Initializing with the Built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization Power ON (VDD-VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB pin = "H" User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select]
User LCD Power Setup by Internal Instructions [Oscillator On]
[DC-DC Step-up Register Select] [VC On] Waititing for 25ms [Regulator Resistor Select] [Electronic Volume Register Select] [VR On] Waititing for 1ms [LCD Bias Register Select] [Power Control] [VF On] Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 36. Initializing with the Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Initializing without the Built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization Power ON (VDD-VSS) Keeping the RESETB Pin = "L" Waiting for Stabilizing the Power
RESETB pin = "H" User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator On]
[DC-DC Step-up Register Select] [VC On] Waititing for 25ms [Regulator Resistor Select] [Electronic Volume Register Select] [VR On] Waititing for 1ms [LCD Bias Register Select] [Power Control] [VF On]
Waiting for Stabilizing the LCD Power Levels End of Initialization
Figure 37. Initializing without the Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display Data by Instruction [Display Data write]
Turn Display On by Instruction [Display ON/Off]
End of Data Display
Figure 38. Data Displaying Referential Instruction Setup Flow: Power OFF
Optional Status
Set Power Save by Instruction [Power Save Mode] Waiting for 25ms Power Off (VDD-VSS)
End of Power Off
Figure 39. Power OFF
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Referential Instruction Setup Flow: Partial Duty Changing
Start of Partial changing Set Display OFF by Internal Instruction [Display ON / OFF] Set Standby Mode by Internal Instruction [Power Save Mode] Set Partial Duty by Internal Instructions [Partial Display Duty Ratio Select] [Initial Display Line Register] [COM0 Register Select] User LCD Power Setup by Internal Instructions [DC-DC Step-up Register Select] [VC On] Waiting for 25ms [Regulator Resistor Select] [Electronic Volume Register Select] [VR On] Waiting for 1ms [LCD Bias Register Select] [VF ON] Waiting for Discharging the LCD Power Levels
Release Power Save Waiting for Stabilizing the LCD Power Levels Write Display Data & Display ON by Internal Instruction [Display Data Write] [Display ON / OFF] End of Partial Changing
Figure 40. Partial Duty Changing
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SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 18. Absolute Maximum Ratings (Vss = 0V) Unit V V V
Parameter Supply voltage range
Symbol VDD V0, VOUT V1, V2, V3, V4
Rating - 0.3 ~ + 7.0 + 0.3 ~ + 17.0 + 0.3 ~ V0 +0.3 ~ VDD - 0.3 ~ VDD + 0.3 - 40 ~ + 85 - 55 ~ + 125
External reference voltage Input voltage range Operating temperature range Storage temperature range
VEXT VIN TOPR TSTR
V C C
NOTES: 1. VDD, V0, VOUT, V1 to V4, VEXT and VCI are based on Vss = 0V. 2. Voltage VOUT V0 V1 V2 V3 V4 VSS must always be satisfied. 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
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DC CHARACTERISTICS
Table 19. DC Characteristics (VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40~85C) Item Operating voltage (1) Operating voltage (2) Input voltage Output voltage High Low High Low Symbol VDD V0 VIH VIL VOH VOL IIL IOZ RON fFR IOH = -0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS Ta = 25C, V0 = 8V Ta = 25C x3 Voltage converter input voltage VCI x4 x5 x6 Voltage converter circuit output voltage Voltage regulator circuit operating voltage Voltage follower circuit operating voltage Reference voltage VOUT x3 / x4 / x5 / x6 voltage conversion (no-load ) Condition Min. 2.4 4.0 0.8VDD VSS 0.8VDD VSS - 1.0 - 3.0 70 2.4 2.4 2.4 2.4 95 Typ. 2.0 85 99 Max. 3.6 15.0 VDD 0.2VDD VDD 0.2VDD + 1.0 + 3.0 3.0 100 3.6 3.6 3.0 2.5 % VOUT V VCI A A k Hz *3 *5 SEGn COMn *6 *7 FR V *4 Unit V V V Pin used VDD *1 V0, *2 *3
Input leakage current Output leakage current LCD driver ON resistance Frame frequency
VOUT
6.0
-
15.0
V
VOUT
V0 VREF Ta = 25C
4.0 1.94
2.00
15.0 2.06
V V
V0 *8 *9
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Dynamic Current Consumption (1) when an External Power Supply is used. Table 20. Display OFF (VDD = 3.0V, Ta = 25C) Item Dynamic current consumption (1) Symbol IDD1 Condition V0 - Vss = 13.0V, duty = 1/105 Min. Typ. Max. 10 Unit Pin used *10
Table 21. Checker Pattern (VDD = 3.0V, Ta = 25C) Item Dynamic current consumption (1) Symbol IDD1 Condition V0 - Vss = 13.0V, duty = 1/105 Min. Typ. Max. 15 Unit Pin used *10
Dynamic Current Consumption (2) when the Internal Power Supply is ON Table 22. Display OFF (VDD = 3.0V, Ta = 25C) Item Dynamic current consumption (2) Symbol IDD2 Condition V0 - Vss = 13.0V, X5 boosting, duty = 1/105, normal mode Min. Typ. Max. 200 Unit Pin used *10
Table 23. Check Pattern (VDD = 3.0V, Ta = 25C) Item Dynamic current consumption (2) Symbol IDD2 Condition V0 - Vss = 13.0V, X5 boosting, duty = 1/105, normal mode Min. Typ. Max. 300 Unit Pin used *10
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Dynamic Current Consumption during Power Save Mode Table 24. Power Save Mode (VDD = 3.0V, Ta = 25C) Item Sleep mode current Standby mode current Symbol IDDS1 IDDS2 Condition During sleep During standby Min. Typ. Max. 2 20 Unit Pin used
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Table 25. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio 1/N Item fCL Fosc
On-chip oscillator circuit is fFR x N fFR x 4 x N used (fOSC: oscillation frequency, fCL: display clock frequency, fFR: frame frequency, N = 9 to 105)
[* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, C68, PS, INTRS, HPMB, REF, CL, M and SYNC. *4. DB0 to DB7, FR, FRS, SYNC, M and CL. *5. Applies when the DB0 to DB7, SYNC, M, and CL pins are in high impedance. *6. Resistance value when -0.1[mA] is applied during the On status of the output pin SEGn or COMn. RON [k] = V[V] / 0.1[mA] (V : voltage change when -0.1[mA] is applied in the ON status.) *7. See Table 25 for the relationship between oscillation frequency and frame frequency. *8. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. *9. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *10. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is on or OFF. The current flowing through voltage regulation resistors (Rb and Ra) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
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AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
RS tAS80 tCY80 tPWLW , tPWLR /RD, /WR CS1B DB0 to DB7 ( Write ) DB0 to DB7 ( Read ) Figure 41. Parallel Interface (8080-series MPU) Timing Diagram tACC80 tOD80 0.9VDD 0.1VDD tDS80 tPWHW , tPWHR tDH80 tAH80
Table 26. AC Characteristics (8080-series Parallel Mode) Item Address setup time Address hold time System cycle time Pulse width low for write Pulse width High for write Pulse width low for read Pulse width high for read Data setup time Data hold time Read access time Output disable time RW_WR (/WR) E_RD (/RD) DB0 to DB7 Signal RS Symbol tAS80 tAH80 tCY80 tPWLW tPWHW tPWLR tPWHR tDS80 tDH80 tACC80 tOD80 CL = 100 pF Condition (VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 300 60 60 120 60 40 15 10 140 100 ns ns ns ns ns ns
NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read
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Read / Write Characteristics (6800-series Microprocessor)
RS, R/W tAS68 tCY68 tEWLW, tEWLR E CS1B DB0 to DB7 ( Write ) tACC68 DB0 to DB7 ( Read ) Figure 42. Parallel Interface (6800-series MPU) Timing Diagram tOD68 0.1VDD 0.9VDD tEWHW , tEWHR tDS68 tDH68 tAH68
Table 27. AC Characteristics (6800-series Parallel Mode) (VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 300 60 60 120 60 40 15 CL = 100 pF 10 140 100 ns ns ns ns ns ns
Item Address setup time Address hold time System cycle time Enable width high for write Enable width low for write Enable width high for read Enable width low for read Data setup time Data hold time Read access time Output disable time
Signal RS RW
Symbol tAS68 tAH68 tCY68
Condition
E_RD (E) E_RD (E) DB0 to DB7
tEWHW tEWLW tEWHR tEWLR tDS68 tDH68 tACC68 tOD68
NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tCY68 - tEWHW - tEWLW ) for write, (tr + tf) < (tCY68 - tEWHR - tEWLR ) for read
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Serial Interface Characteristics tCSS CS1B (CS2 = 1 ) tASS tCHS tAHS
RS tCYS DB6 ( SCLK ) 0.9VDD 0.1VDD tWLS tDSS DB7 ( SID ) Figure 43. Serial Interface Timing Diagram tDHS tWHS
Table 28. AC Characteristics (Serial Mode) Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CS1B setup time CS1B hold time Signal DB6 (SCLK) RS DB7 (SID) CS1B Symbol tsCY tsHW tsLW tASS tAHS tDSS tDHS tCSS tCHS Condition (VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Min. Max. Unit 250 100 100 150 150 100 100 150 150 ns
ns ns ns
NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
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Reset Input Timing
tRW RESETB tR Internal status During reset Reset complete
Figure 44. Reset Input Timing Diagram
Table 29. AC Characteristics (Reset mode) (VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Item Reset low pulse width Reset time Signal RESETB Symbol tRW tR Condition Min. 1000 Max. 1000 Unit ns ns
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REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
CS1B CS2 RS E RW DB0 to DB7 RESETB VDD VDD
6800-series MPU
CS1B CS2 RS E_RD
S6B 0719
RW_WR DB0 to DB7 RESETB C68 PS
Figure 45. In Case of Interfacing with 6800-series (PS = "H", C68 = "H")
CS1B CS2
CS1B CS2 RS E_RD RW_WR
8080-series MPU
RS /RD /WR DB0 to DB7 RESETB V SS VDD
S6B 0719
DB0 to DB7 RESETB C68 PS
Figure 46. In Case of Interfacing with 8080-series (PS = "H", C68 = "L")
CS1B CS2 RS SID
CS1B CS2 RS DB7(SID)
S6B 0719
MPU
SCLK RESETB OPEN VDD or VSS VSS
DB6(SCLK) RESETB DB0 to DB5 C68 PS
Figure 47. In Case of Serial Interface (PS = "L", C68 = "H/L")
61
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD
S6B0719
CONNECTIONS BETWEEN S6B0719 AND LCD PANEL
Single Chip Configuration (1/105 Duty configurations)
COMS COM103 COM 52
S6B0719 (Bottom View)
COM51 COM0 COMS
COM 51 COM0 COMS
S6B0719 (Top View)
COMS COM103 COM52
SEG159 SEG158 SEG1 SEG0
SEG0 SEG1 SEG158 SEG159
(R)
(R)
104 x 160 pixels
(R)
104 x 160 pixels
(R)
Figure 48. SHL = 0, ADC = 0
Figure 49. SHL = 0, ADC = 1
(R)
(R)
104 x 160 pixels
(R)
104 x 160 pixels
(R)
SEG0 SEG1 SEG158 SEG159
COMS COM0 COM51
SEG159 SEG158 SEG1 SEG0
COM52 COM103 COMS
S6B0719 (Bottom View)
COM52 COM 103 COMS
S6B0719 (Top View)
COMS COM0 COM 51
Figure 50. SHL = 1, ADC = 0
Figure 51. SHL = 1, ADC = 1
62
S6B0719 LCD
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN
Multiple Chip Configuration
COMS COM 103 COM 52
S6B0719 (Bottom View) (Master)
COM51 COM0 COMS
COMS COM 103 COM52
SEG159 SEG158 SEG1 SEG0
SEG159 SEG158 SEG1 SEG0
S6B0719 (Bottom View) (Slave)
COM51 COM0 COMS
(R)
104 x 320 pixels
(R)
Figure 52. SHL = 0, ADC = 1 Connect the following pins of two chips each other: - Display clock pins: CL, M, SYNC - LCD power pins: V0, V1, V2, V3, V4
(R)
104 x 320 pixels
(R)
SEG0 SEG1 SEG158 SEG159
COMS COM0 COM51
SEG0 SEG1 SEG158 SEG159
COMS COM0 COM51
S6B0719 (Bottom View) (Master)
COM 52 COM 103 COMS
S6B0719 (Bottom View) (Slave)
COM52 COM 103 COMS
Figure 53. SHL = 1, ADC = 0 Connect the following pins of two chips each other: - Display clock pins: CL, M, SYNC - LCD power pins: V0, V1, V2, V3, V4
63

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