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80 SEGMENT DRIVER FOR DOT MATRIX LCD
S6A2067
S6A2067
80 SEG DRIVER FOR STN LCD
Jan. 2002. Ver. 0.1
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
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S6A2067
80 SEGMENT DRIVER FOR DOT MATRIX LCD
INTRODUCTION
The S6A2067 is a LCD driver lC which is fabricated by low power CMOS technology. Basically this LSl consists of 40 x 2 bit bi-directional shift register, 40 x 2 bit data latch and 40 x 2 bit LCD driver (refer to Figure 1). This lC can be used as segment driver.
FUNCTION
-- -- Dot matrix LCD driver with 80 channel output. Input/Output signal - Output: 40 x 2 channel waveform for LCD driving - Input: Serial display data and control signal pulse from the controller lC. Bias voltage (V1 to V4)
FEATURES
-- -- -- -- Display driving bias: static - 1/5 Power supply voltage: 2.7V to 5.5V Supply voltage for display: 3.0V to 13.0V (V LCD = VDD - VEE) Interface Driver (cascade connection) S6A0065, Other S6A2067 Controller S6A0069 S6A0070 S6A0073
-- --
CMOS Process 100QFP or bare chip available
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80 SEGMENT DRIVER FOR DOT MATRIX LCD
S6A2067
BLOCK DIAGRAM
S1 S2
Part 1 S39 S40
S41 S42
Part 2 S79 S80
V1 V2 V3 V4
LCD DRIVER
LCD DRIVER
VDD Data Latch (40 bits) Bidirectional Shift Register (40 bits) M CL1 CL2 SW Contr Logic Data Latch (40 bits) Bidirectional Shift Register (40 bits) VSS VEE
DL1 SHL1 DR1
DL2
SHL2
DR2
Figure 1. S6A2067 Functional Block Diagram
3
S6A2067
80 SEGMENT DRIVER FOR DOT MATRIX LCD
PIN CONFIGURATION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
S6A2067
NC NC M DR2 DL2 DR1 DL1 CL2 VDD NC NC SHL2 SHL1 CL1 GND V4 V3 V2 V1 VEE
4
S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Figure 2. 100 QFP Top View
80 SEGMENT DRIVER FOR DOT MATRIX LCD
S6A2067
PAD DIAGRAM
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
Y
(0, 0)
X
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
S6A2067
Chip size: 3160 x 4110 Pad size: 100 x 100 Unit: m
52 51 48 47 46 45 44 43 42 39 38 37 36 35 34 33 32 31 30
5
S6A2067
80 SEGMENT DRIVER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
Pad Num. Pad Name Coordinate X Y Pad Num. Pad Name Coordinate X Y Pad Num. Pad Name Coordinate X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTE:
S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 VEE V1
-1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1352 -1087 -962 -837
1687 1562 1437 1312 1187 1062 937 812 687 562 437 312 187 62 -63 -188 -313 -438 -563 -688 -813 -938 -1063 -1188 -1313 -1438 -1563 -1688 -1813 -1827 -1827 -1827
33 34 35 36 37 38 39 42 43 44 45 46 47 48 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
V2 V3 V4 V5 CL1 SHL1 SHL2 VDD CL2 DL1 DR1 DL2 DR2 M S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58
-712 -587 -462 -313 -188 -63 62 187 312 437 562 687 812 937 1086 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352
-1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1827 -1813 -1688 -1563 -1438 -1313 -1188 -1063 -938 -813 -688 -563 -438 -313 -188 -63 62 187
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31
1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1352 1062 937 812 687 562 437 312 187 62 -63 -188 -313 -438 -563 -688 -813 -938 -1063 -1352
312 437 562 687 812 937 1062 1187 1312 1437 1562 1687 1812 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827 1827
S6A2067 Marking: easy to find the PAD No.6, No.90.
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80 SEGMENT DRIVER FOR DOT MATRIX LCD
S6A2067
PIN DESCRIPTION
PIN (NO.)
VDD(42) VSS(GND)(36) VEE(31) V1, V2(32,33) Input
I/O
Power
Name Operating Voltage
Description
For logical circuit (2.7 - .5V) 0V (GND)
Interface
Power Supply
Negative Supply Voltage LCD driver output voltage level
For LCD driver circuit Bias voltage level for LCD drive (Select level) Power
V3, V4(34,35) S1 - S40 SHL1(38)
Input Output Input Part 1
Bias voltage level for LCD drive (Non-select level)
LCD driver Data Interface
LCD driver output Selection of the shift direction of shift register SHL1 VDD VSS DL1 OUT IN DR1 IN OUT
LCD VDD or VSS
DL1, DR1 (44,45) S41 - S80 SHL2 (39)
Input Output Output Input Part 2
Data Input/output of shift register (part 1)
Controller or S6A2067/ S6A0065 LCD VDD or VSS
LCD driver Data Interface
LCD driver output Selection of the shift direction of shift register SHL2 VDD VSS DL2 OUT IN DR2 IN OUT
DL2, DR2 (46,47) M(48)
Input Output Input
Data Input/output of shift register (part 2)
Controller or S6A2067/ S6A0065 Controller
Alternated signal for LCD driver output Data shift/ latch clock
The alternating signal to convert LCD drive waveform to AC CL1 : Data latch clock CL2 : Data shift clock No connection
CL1, CL2 (37,43) NC (40,41,49,50)
Input
NC
7
S6A2067
80 SEGMENT DRIVER FOR DOT MATRIX LCD
MAXIMUM ABSOLUTE LIMIT
(TA = 25C) Characteristic Operating Voltage Driver Supply Voltage Input Voltage 1 Input Voltage 2 (V1 - V4) Operating Temperature Storage Temperature Symbol VDD VLCD VlN1 VIN2 TOPR TSTG Value -0.3 - +7.0 VDD-15.0 - VDD+0.3 -0.3 - VDD+0.3 VDD+0.3 - VEE-0.3 -30 - +85 -55 - +125 Unit V V V V

C C
NOTES: 1. Voltage greater than above may damage the circuit 2. VEE : connect a protection resistor (220 5%)
ELECTRICAL CHARACTERISTICS
DC Characteristics (V DD = 2.7 to 5.5V, VDD-VEE = 3 - 13V, VSS = 0V, TA = -30 to 85C) Characteristic Operating Current Supply Current Input High Voltage Input Low Voltage Symbol lDD lEE VIH VIL lLKG VOH VOL VD1 VD2 Leakage Current IV VIN = 0 - VDD IOH = -0.4mA IOL = +0.4mA ION = 0.1mA for one of S1 - S80 ION = 0.05mA for each S1 - S80 VIN = VDD - VEE (Output S1 - S80: floating) -10 10 A V1 - V4 - 1.5 - Test condition fCL2 = 400kHz fCL1 = 1kHz - Min - - 0.7V DD 0 Max 1 10 VDD 0.3V DD 5 - 0.4 1.1 V A Unit mA A V CL1, CL2,DL1, DL2, DR1, DR2, Input Leakage Current Output High Voltage Output Low Voltage Voltage Descending -5 VDD-0.4 SHL1, SHL2, M DL1, DL2, DR1, DR2 V (V1-V4)-S (S1-S80) Applicable pin VDD, VEE
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80 SEGMENT DRIVER FOR DOT MATRIX LCD
S6A2067
AC Characteristics (V DD = 2.7 to 5.5V, VDD-VEE = 3 - 13V, VSS = 0V, TA = -30 to 85C) Characteristic Data Shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Symbol fCL tWCKH tWCKL tSL tLS Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time tR/tF tSU tDH tD Test condition - - - from CL2 to CL1 from CL1 to CL2 - - - CL = 15pF Min - 800 800 500 500 - 300 300 - Max 400 - - - - 200 - - 500 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 Unit kHz ns Applicable pin CL2 CL1, CL2 CL2 CL1,CL2
9
S6A2067
80 SEGMENT DRIVER FOR DOT MATRIX LCD
TIMING CHARACTERISTICS
CL2
VIH VIL tR tWCKH
tWCKL VIL tF tSU
VIH
tDH
Data in (DL1,DL2) (DR1, DR2) Data out (DL1,DL2) (DR1, DR2)
VIH tD
VIL tSL
VOH
VOL VIH VIL tR tSU
tLS
tLS
CL1
tWCKH tF
FLM
VIH
VIL
Figure 3. AC Characteristics
10
80 SEGMENT DRIVER FOR DOT MATRIX LCD
S6A2067
LCD OUTPUT WAVEFORMS
Output of Latch (DATA)
M
V2 V4 OUTPUT (S1 - S80) V1 V3 V1
V2 V4 V3
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S6A2067
80 SEGMENT DRIVER FOR DOT MATRIX LCD
APPLICATION CIRCUIT
COM1 COM16 S6A0069 (controller) D CLK1 CLK2 VDD M V1 V2 V3 V4 V5 -
common signal LCD Segment signal S1 - S80 SHL1 SHL2 S6A2067 (seg driver) DL1 DR1 DL2 CL1 CL2 M DR2 S1 - S80 SHL1 SHL2 DL1 DR1 DL2 CL1 CL2 M S6A2067 (seg driver)
DR2 open
VEE V1 V2 V3 V4
VDD GND or Other Voltage
12
VEE V1 V2 V3 V4

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