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DRV593 DRV594
SLOS401A - AUGUST 2002 - REVISED OCTOBER 2002
3-A HIGH-EFFICIENCY PWM POWER DRIVER
FEATURES D Operation Reduces Output Filter Size and
Cost by 50% Compared to DRV591
DESCRIPTION
The DRV593 and DRV594 are high-efficiency, high-current power amplifiers ideal for driving a wide variety of thermoelectric cooler elements in systems powered from 2.8 V to 5.5 V. The operation of the device requires only one inductor and capacitor for the output filter, saving significant printed-circuit board area. Pulse-width modulation (PWM) operation and low output stage on-resistance significantly decrease power dissipation in the amplifier. The DRV593 and DRV594 are internally protected against thermal and current overloads. Logic-level fault indicators signal when the junction temperature has reached approximately 115C to allow for system-level shutdown before the amplifier's internal thermal shutdown circuitry activates. The fault indicators also signal when an overcurrent event has occurred. If the overcurrent circuitry is tripped, the devices automatically reset (see application information section for more details). The PWM switching frequency may be set to 500 kHz or 100 kHz depending on system requirements. To eliminate external components, the gain is fixed at 2.3 V/V for the DRV593. For the DRV594, the gain is fixed at 14.5 V/V.
VDD 10 F 1 F
D D D D D D D D D
3-A Maximum Output Current Low Supply Voltage Operation: 2.8 V to 5.5 V High Efficiency Generates Less Heat Overcurrent and Thermal Protection Fault Indicators for Overcurrent, Thermal and Undervoltage Conditions Two Selectable Switching Frequencies Internal or External Clock Sync PWM Scheme Optimized for EMI 9x9 mm PowerPAD Quad Flatpack Package
APPLICATIONS D Thermoelectric Cooler (TEC) Driver D Laser Diode Biasing
PWM
PWM
FREQ
PVDD
PVDD
INT/EXT
PVDD
PWM
1 F 120 k 220 pF 1 F
10 H PWM PGND PGND PGND
AVDD ROSC COSC AREF IN+ IN-
AGND (Connect to PowerPAD)
To TEC or Laser Diode Anode
DC Control Voltage 1 k 1 k
DRV593 DRV594
PGND PGND PGND H/C 10 F
FAULT1
FAULT0
Shutdown Control
SHUTDOWN
PVDD
PVDD
PVDD
H/C
H/C
FAULT1 FAULT0 1 F
H/C
To TEC or Laser Diode Cathode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
DRV593 DRV594
SLOS401A - OCTOBER 2002
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA -40C to 85C 40C PowerPAD QUAD FLATPACK (VFP) DRV593VFP(1) DRV594VFP(1)
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., DRV593VFPR or DRV594VFPR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) DRV593, DRV594 Supply voltage, AVDD, PVDD Input voltage, VI Output current, IO (FAULT0, FAULT1) Continuous total power dissipation Operating free-air temperature range, TA Operating junction temperature range, TJ -0.3 V to 5.5 V -0.3 V to VDD + 0.3 V 1 mA See Dissipation Rating Table -40C to 85C -40C to 150C
Storage temperature range, Tstg -65C to 165C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, AVDD, PVDD High-level input voltage, VIH Low-level input voltage, VIL 2.8 2 FREQ, INT/EXT, SHUTDOWN, COSC FREQ, INT/EXT, SHUTDOWN, COSC MAX UNIT 5.5 0.8 85 V V V
NNN N NNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN N NN N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NN
Operating free-air temperature, TA - 40 C
PACKAGE DISSIPATION RATINGS
PACKAGE JA(1) (C/W) JC (C/W)
TA = 25C POWER RATING
VFP 29.4 1.2 4.1 W (1) This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in x 3 in PCB.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted PARAMETER |VOO| |IIH| |IIL| Vn VICM Av Output offset voltage (measured differentially) High-level input current Low-level input current Integrated output noise voltage Common-mode Common mode voltage range Closed-loop Closed loop voltage gain Full power bandwidth VO Voltage output (measured differentially) IO = 1 A, rds(on) = 65 m, VDD = 5 V IO = 3 A, rds(on) = 65 m, VDD = 5 V High side VDD = 5 V, IO = 4 A, TA = 25C VDD = 3.3 V, IO = 4 A, TA = 25C Maximum continuous current output Status flag output pins (FAULT0, FAULT1) Fault active (open drain output) External clock f Et l l k frequency range Iq Iq(SD) Quiescent current Qi t t Quiescent current in shutdown mode Output resistance in shutdown Power-on threshold Power-off threshold Thermal trip point Thermal shutdown ZI Input impedance (IN+, IN-) FAULT0 active Power off Sinking 200 A For 500 kHz operation For 100 kHz operation VDD = 5 V, No load or filter VDD = 3.3 V, No load or filter VDD = 5 V, SHUTDOWN = 0.8 V SHUTDOWN = 0.8 V 0 1 1.7 1.6 115 150 100 225 45 250 50 4 2.5 40 2 2.8 2.6 Low side High side Low side TEST CONDITIONS VI = VDD/2, VDD = 5.5V, VDD = 5.5V, f = <1 Hz to 10 kHz VDD = 5 V VDD = 3.3 V DRV593 DRV594 IO = 0 A VI = VDD VI = 0 V 40 1.2 1.2 2.1 13.7 2.3 14.5 60 4.87 4.61 25 25 25 25 60 65 80 90 3 0.1 300 55 12 8 80 mA A A k V V C C k kHz kH 95 95 140 140 m A V m V 3.8 2.1 2.6 15.3 V V/V V/V kHz MIN TYP 14 MAX 100 1 1 UNIT mV A A V
rDS(on)
Drain-source on-state Drain source on state resistance
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SLOS401A - OCTOBER 2002
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PIN ASSIGNMENTS
VFP PACKAGE (TOP VIEW)
32 31 30 29 28 27 26 25
AVDD AGND ROSC COSC AREF IN+ IN- SHUTDOWN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PowerPAD
FREQ INT/EXT PVDD PVDD PVDD PWM PWM PWM
24 23 22 21 20 19 18 17
PWM PGND PGND PGND PGND PGND PGND H/C
Terminal Functions
TERMINAL NAME AGND AREF AVDD COSC FAULT0 FAULT1 FREQ IN- IN+ INT/EXT H/C PWM PGND NO. 2 5 1 4 10 9 32 7 6 31 14, 15, 16, 17 24, 25, 26, 27 18, 19, 20, 21, 22, 23 11, 12, 13, 28, 29, 30 3 8 I O I I O O I I I I O O I/O Analog ground Connect 1 F capacitor to ground for AREF voltage filtering Analog power supply Connect capacitor to ground to set oscillation frequency (220 pF for 500 kHz, 1 nF for 100 kHz) when the internal oscillator is selected; connect clock signal when an external oscillator is used Fault flag 0, low when active open drain output (see application information) Fault flag 1, high when active open drain output (see application information) Selects 500 kHz switching frequency when a TTL logic low is applied to this terminal; selects 100 kHz switching frequency when a TTL logic high is applied Negative differential input Positive differential input Selects the internal oscillator when a TTL logic high is applied to this terminal; selects the use of an external oscillator when a TTL logic low is applied to this terminal Direction control output for heat and cool modes (4 pins) PWM output for voltage magnitude (4 pins) High-current ground (6 pins) DESCRIPTION
PVDD
High-current power supply (6 pins)
ROSC SHUTDOWN
I I
Connect 120-k resistor to AGND to set oscillation frequency (either 500 kHz or 100 kHz). Not needed if an external clock is used. Places the amplifier in shutdown mode when a TTL logic low is applied to this terminal; places the amplifier in normal operation when a TTL logic high is applied
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FAULT1 FAULT0 PVDD PVDD PVDD H/C H/C H/C
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DRV593 DRV594
SLOS401A - OCTOBER 2002
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND
AVDD
R
2.3 x R (DRV593) 14.5 x R (DRV594) _ + + _ _ + + _
PVDD
+ _ Gate Drive
IN-
H/C PGND
PVDD
IN+
R 2.3 x R (DRV593) 14.5 x R (DRV594) + _ Gate Drive
PWM PGND
SHUTDOWN INT/EXT FREQ COSC ROSC AREF
TTL Input Buffer Biases and References Ramp Generator
Start-Up Protection Logic
OC Detect
Thermal
VDDok
FAULT0 FAULT1
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TYPICAL CHARACTERISTICS TABLE OF GRAPHS
FIGURE Efficiency vs Load resistance vs Supply voltage rDS(on) Iq PSRR Drain source on-state Drain-source on state resistance Supply current Power supply rejection ratio Closed loop response vs Output voltage IO VIO Maximum output current Input offset voltage vs Ambient temperature Common-mode input voltage vs Free-air temperature vs Free-air temperature vs Supply voltage vs Frequency 2, 3 4 5 6 7 8, 9 12, 13 14 15 16, 17
TEST SETUP FOR GRAPHS
The LC output filter used in Figures 2, 3, 8, and 9 is shown below.
L1 PWM
C1
RL
H/C
L1 = 10 H (part number: CDRH104R, manufacturer: Sumida) C1 = 10 F (part number: ECJ-4YB1C106K, manufacturer: Panasonic)
Figure 1. LC Output Filter
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DRV593 DRV594
SLOS401A - OCTOBER 2002
TYPICAL CHARACTERISTICS
EFFICIENCY vs LOAD RESISTANCE
100 90 80 70 Efficiency - % 60 50 40 30 20 10 0 1 2 3 4 5 6 7 8 RL - Load Resistance - 9 10 VDD = 5 V fS = 500 kHz PO = 1 W PO = 0.5 W Efficiency - % PO = 2 W 100 90 80 PO = 0.5 W 70 60 50 40 30 20 10 0 1 2 3 4 5 6 7 8 RL - Load Resistance - 9 10 VDD = 3.3 V fS = 500 kHz PO = 0.25 W PO = 1 W
EFFICIENCY vs LOAD RESISTANCE
Figure 2
DRAIN-SOURCE ON-STATE RESISTANCE vs SUPPLY VOLTAGE
rDS(on) - Drain-Source On-State Resistance - m rDS(on) - Drain-Source On-State Resistance - m 300 IO = 1 A TA = 25C 250 300
Figure 3
DRAIN-SOURCE ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE
VDD = 5 V IO = 1 A VFP Package
250
200
Total
200 Total 150
150
100
Low Side High Side
100
Low Side High Side
50
50
0 2.7
3.1
3.5 3.9 4.3 4.7 VDD - Supply Voltage - V
5.1
5.5
0 -40
-15 10 35 60 TA - Free-Air Temperature - C
85
Figure 4
Figure 5
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SLOS401A - OCTOBER 2002
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TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE
rDS(on) - Drain-Source On-State Resistance - m 300 VDD = 3.3 V IO = 1 A VFP Package Iq - Supply Current - mA Total 200 10 No Load 9 8 7 6 5 4 3 2 1 0 -40 -15 10 35 60 85 0 2.7 3.1
SUPPLY CURRENT vs SUPPLY VOLTAGE
250
150 Low Side 100 High Side 50
3.5
3.9
4.3
4.7
5.1
5.5
TA - Free-Air Temperature - C
VDD - Supply Voltage - V
Figure 6
POWER SUPPLY REJECTION RATIO vs FREQUENCY
-20 PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB VDD = 5 V fS = 500 kHz RL = 1 Vripple = 100 mVpp -20
Figure 7
POWER SUPPLY REJECTION RATIO vs FREQUENCY
VDD = 3.3 V fS = 500 kHz RL = 1 Vripple = 100 mVpp
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80 10
100
1k 10k f - Frequency - Hz
100k
-80 10
100
1k 10k f - Frequency - Hz
100k
Figure 8
Figure 9
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DRV593 DRV594
SLOS401A - OCTOBER 2002
TYPICAL CHARACTERISTICS
DRV593 DRV594
CLOSED LOOP RESPONSE
4 Phase 3 10 0 -10 -20 Gain - V/V Gain - V/V -30 2 -40 -50 1 VDD = 5 V No Load 0 10 100 1k 10k f - Frequency - Hz -60 -70 -80 100k 4 2 0 10 Phase - Gain 10 8 6 16
CLOSED LOOP RESPONSE
10 Gain 14 12 Phase -20 -30 -40 -50 VDD = 5 V No Load -60 -70 100 k Phase - Phase - 9 0 -10
100
1k f - Frequency - Hz
10 k
Figure 10
Figure 11
DRV593
DRV594
CLOSED LOOP RESPONSE
4 10 0 Phase 3 -10 -20 Gain - V/V -30 2 -40 -50 1 VDD = 3.3 V No Load 0 10 100 1k 10k f - Frequency - Hz -60 -70 -80 100k 4 2 0 10 Gain - V/V Gain Phase - 10 8 6 16
CLOSED LOOP RESPONSE
10 Gain 14 12 Phase -20 -30 -40 -50 VDD = 3.3 V No Load -60 -70 100 k 0 -10
100
1k f - Frequency - Hz
10 k
Figure 12
Figure 13
DRV593 DRV594
SLOS401A - OCTOBER 2002
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TYPICAL CHARACTERISTICS
MAXIMUM OUTPUT CURRENT vs OUTPUT VOLTAGE
3.5 3 I O - Maximum Output Current - A TJ = 100C 2.5 2 1.5 1 0.5 0 0 1 VDD = 5 V TA = 25C VFP Package 2 3 VO - Output Voltage - V 4 5 TJ = 85C TJ = 125C 3.5 3 2.5 2 1.5 1 0.5
MAXIMUM OUTPUT CURRENT vs AMBIENT TEMPERATURE
I O - Maximum Output Current - A
TJ 125C VFP Package
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TA - Ambient Temperature - C
Figure 14
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
10 9 VIO - Input Offset Voltage - mV 8 7 6 5 4 3 2 1 0 1.2 1.6 2.0 2.4 2.8 3.2 3.6 3.8 VDD = 5 V No Load VIO - Input Offset Voltage - mV 20 19 18 17 16 15 14 13 12 11 10 1.2 VDD = 3.3 V No Load
Figure 15
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
VIC - Common-Mode Input Voltage - V
1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VIC - Common-Mode Input Voltage - V
2.1
Figure 16
Figure 17
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DRV593 DRV594
SLOS401A - OCTOBER 2002
APPLICATION INFORMATION PULSE-WIDTH MODULATION SCHEME FOR DRV593 AND DRV594
The pulse-width modulation scheme implemented in the DRV593 and DRV594 eliminates one-half of the full output filter previously required for PWM drivers. The DRV593 and DRV594 require only one inductor and capacitor for the output filter. The H/C outputs determine the direction of the current and do not switch back and forth. The PWM outputs switch to produce a voltage across the load that is proportional to the input control voltage.
COOLING MODE
Figure 18 shows the DRV593 and DRV594 in cooling mode. The H/C outputs (pins 14-17) are at ground and the PWM outputs (pins 24-27) create a voltage across the load that is proportional to the input voltage. The differential voltage across the load is determined using equation (1) and the duty cycle using equation (2). The differential voltage is defined as the voltage measured after the filter on the PWM output relative to the H/C output.
V Load + D
V DD
(1)
D+ where D
Av VIN+ VIN- VDD
A v VIN)-V IN- V DD
(2)
duty cycle of the PWM signal Gain of DRV593/594 (DRV593: 2.3 V/V, DRV594: 14.5 V/V) Positive input terminal of the DRV593/594 Negative input terminal of the DRV593/594 Power supply voltage
For example, a 50% duty cycle, shown in Figure 18, results in 2.5 V across the load for VDD = 5 V.
VDD PWM 0
VDD H/C 0
VDD VDD/2 Load Voltage
0
Figure 18. Cooling Mode
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SLOS401A - OCTOBER 2002
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HEATING MODE
Figure 19 shows the DRV593 and DRV594 in heating mode. The H/C output is at VDD and the PWM output is proportional to the voltage across the load. The differential voltage across the load is determined using equation (3). The variables are the same as used previously for equations (1) and (2).
V Load + -(1-D)
V DD
(3)
For example, a 50% duty cycle, shown in Figure 19, results in -2.5 V across the load for VDD = 5 V. The differential voltage across the load is defined as the voltage measured after the filter on the PWM output relative to the H/C output.
VDD PWM 0
VDD H/C 0
Load Voltage -VDD/2 -VDD
0
Figure 19. Heating Mode
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HEAT/COOL TRANSITION
As the device transitions from cooling to heating, the duty cycle of the PWM outputs decrease to a small value and the H/C outputs remains at ground. When the device transitions to heating mode, the H/C outputs change from zero volts to VDD and the PWM outputs change to a high duty cycle. The direction of the current flow is reversed, but a low voltage is maintained across the load. The duty cycle decreases as the part is put further into heating mode to drive more current through the load. Figure 20 illustrates the transition from cooling to heating.
ZERO-CROSSING REGION
When the differential output voltage is near zero, the control logic in the DRV593 and DRV594 causes the outputs to change between heating and cooling modes. There are two possible states for the PWM and H/C outputs to obtain zero volts differentially: both outputs can be at VDD or both outputs can be at ground. Therefore, random noise causes the outputs to change between the two states when the two input voltages are equal. The outputs switch from zero to VDD, although not at a fixed frequency rate. Some of the pulses may be wider than others, but the two outputs (PWM and H/C) track each other to provide zero differential voltage. These uneven pulse widths can increase the switching noise during the zero-crossing condition. To avoid this phenomenon, hysteresis should be implemented in the control loop to prevent the device from operating within this region. Although planning for operation during the zero-crossing is important, the normal operating points for the DRV593 and DRV594 are outside of this region. For laser temperature/wavelength regulation, the zero volts output condition is only a concern when the laser temperature or wavelength, relative to the ambient temperature, requires no heating or cooling from the TEC element.
VDD
IN + IN -
0
VDD PWM 0
VDD H/C 0
Figure 20. Transition From Cooling to Heating
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DRV593 DRV594
SLOS401A - OCTOBER 2002 VDD 10 F 1 F
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PWM
PWM
FREQ
PVDD
PVDD
INT/EXT
PVDD
PWM
1 F 120 k 220 pF 1 F
10 H PWM PGND PGND PGND
AVDD ROSC COSC AREF IN+ IN-
AGND (Connect to PowerPAD)
To TEC or Laser Diode Anode
DC Control Voltage 1 k 1 k
DRV593 DRV594
PGND PGND PGND H/C 10 F
FAULT1
FAULT0
Shutdown Control
SHUTDOWN
PVDD
PVDD
PVDD
H/C
H/C
FAULT1 FAULT0 1 F
H/C
To TEC or Laser Diode Cathode
Figure 21. Typical Application Circuit
OUTPUT FILTER CONSIDERATIONS
TEC element manufacturers provide electrical specifications for maximum dc current and maximum output voltage for each particular element. The maximum ripple current, however, is typically only recommended to be less than 10% with no reference to the frequency components of the current. The maximum temperature differential across the element, which decreases as ripple current increases, may be calculated with the following equation:
DT + 1 1 ) N2 DT max (4)
where T = actual temperature differential Tmax = maximum temperature differential (specified by manufacturer) N = ratio of ripple current to dc current According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. An LC network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more importantly, protect the rest of the system from any electromagnetic interference (EMI).
FILTER COMPONENT SELECTION
The LC filter, which may be designed from two different perspectives, both described below, helps estimate the overall performance of the system. The filter should be designed for the worst-case conditions during operation, which is typically when the differential output is at 50% duty cycle. The following section serves as a starting point for the design, and any calculations should be confirmed with a prototype circuit in the lab. Any filter should always be placed as close as possible to the DRV593 and DRV594 to reduce EMI.
L PWM C H/C TEC R
Figure 22. LC Output Filter
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LC FILTER IN THE FREQUENCY DOMAIN
The transfer function for a second-order low-pass filter (Figures 17 and 18) is shown in equation (5):
H LP(jw) + 1 (5)
2
w -w 0
jw ) 1 w )1 Q0
w0 + 1 LC Q + quality factor
w + DRV593 or DRV594 switching frequency For the DRV593 and DRV594, the differential output switching frequency is typically selected to be 500 kHz. The resonant frequency for the filter is typically chosen to be at least one order of magnitude lower than the switching frequency. equation (5) may then be simplified to give the following magnitude equation (6). These equations assume the use of the filter in Figure 22.
H LP dB + -40 log fo + 1 2p LC fs fo (6)
f s + 500 kHz (DRV593 or DRV594 switching frequency)
If L=10 H and C=10 F, the cutoff frequency is 15.9 kHz, which corresponds to -60 dB of attenuation at the 500 kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element is approximately 5 mV. The average TEC element has a resistance of 1.5 , so the ripple current through the TEC is approximately 3.4 mA. At the 3-A maximum output current of the DRV593 and DRV594, this 5.4 mA corresponds to 0.11% ripple current, causing less than 0.0001% reduction of the maximum temperature differential of the TEC element (see equation 4).
LC FILTER IN THE TIME DOMAIN
The ripple current of an inductor may be calculated using equation (7):
V -V DTs O TEC DI + L L D + duty cycle (0.5 worst case) T s + 1 fs + 1 500 kHz (7)
For VO = 5 V, VTEC = 2.5 V, and L = 10 H, the inductor ripple current is 250 mA. To calculate how much of that ripple current flows through the TEC element, however, the properties of the filter capacitor must be considered. For relatively small capacitors (less than 22 F) with very low equivalent series resistance (ESR, less than 10 m), such as ceramic capacitors, the following equation (8) may be used to estimate the ripple voltage on the capacitor due to the change in charge:
2 DV + p 1-D C 2
fo fs
2
(8) V TEC
D + duty cycle f s + 500 kHz fo + 1 2p LC
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SLOS401A - OCTOBER 2002
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For L = 10 H and C = 10 F, the cutoff frequency, fo, is 15.9 kHz. For worst case duty cycle of 0.5 and VTEC=2.5 V, the ripple voltage on the capacitors is 6.2 mV. The ripple current may be calculated by dividing the ripple voltage by the TEC resistance of 1.5 , resulting in a ripple current through the TEC element of 4.1 mA. Note that this is similar to the value calculated using the frequency domain approach. For larger capacitors (greater than 22 F) with relatively high ESR (greater than 100 m), such as electrolytic capacitors, the ESR dominates over the charging/discharging of the capacitor. The following simple equation (9) may be used to estimate the ripple voltage:
DV C + DIL R ESR (9)
DI + inductor ripple current L R + filter capacitor ESR ESR
For a 100 F electrolytic capacitor, an ESR of 0.1 is common. If the 10 H inductor is used, delivering 250 mA of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times that of the 10 F ceramic capacitor, as ceramic capacitors typically have negligible ESR.
SWITCHING FREQUENCY CONFIGURATION: OSCILLATOR COMPONENTS ROSC AND COSC AND FREQ OPERATION
The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. The frequency may be either 500 kHz or 100 kHz by selecting the proper capacitor value and by holding the FREQ pin either low (500 kHz) or high (100 kHz). Table 1 shows the values required and FREQ pin configuration for each switching frequency. Table 1. Frequency Configuration Options
SWITCHING FREQUENCY 500 kHz 100 kHz ROSC 120 k 120 k COSC 220 pF 1 nF FREQ LOW (GND) HIGH (VDD)
For proper operation, the resistor ROSC should have 1% tolerance while capacitor COSC should be a ceramic type with 10% tolerance. Both components should be grounded to AGND, which should be connected to PGND at a single point, typically where power and ground are physically connected to the printed-circuit board.
EXTERNAL CLOCKING OPERATION
To synchronize the switching to an external clock signal, pull the INT/EXT terminal low, and drive the clock signal into the COSC terminal. This clock signal must be from 10% to 90% duty cycle and meet the voltage requirements specified in the electrical specifications table. Since the DRV593 and DRV594 include an internal frequency doubler, the external clock signal must be approximately 250 kHz. Deviations from the 250 kHz clock frequency are allowed and are specified in the electrical characteristic table. The resistor connected from ROSC to ground may be omitted from the circuit in this mode of operation--the source is disconnected internally.
INPUT CONFIGURATION: DIFFERENTIAL AND SINGLE-ENDED
If a differential input is used, it should be biased around the midrail of the DRV593 or DRV594 and must not exceed the common-mode input range of the input stage (see the operating characteristics at the beginning of the data sheet). The most common configuration employs a single-ended input. The unused input should be tied to VDD/2, which may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values chosen should be at least 100 times lower than the input resistance of the DRV593 or DRV594. This prevents the bias voltage at the unused input from shifting when the signal input is applied. A small ceramic capacitor should also be placed from the input to ground to filter noise and keep the voltage stable. An op amp configured as a buffer may also be used to set the voltage at the unused input.
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FIXED INTERNAL GAIN
The differential output voltage may be calculated using equation (10):
V O +V -V + A v V IN)-V IN- OUT) OUT- (10)
AV is the voltage gain, which is fixed internally at 2.3 V/V for DRV593 and 14.5 V/V for DRV594. The maximum and minimum ratings are provided in the electrical specification table at the beginning of the data sheet.
POWER SUPPLY DECOUPLING
To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor, typically 0.1 F to 1 F, should be placed as close to each set of PVDD pins of the DRV593 and DRV594 as possible. For bulk decoupling, a 10 F to 100 F tantalum or aluminum electrolytic capacitor should be placed relatively close to the DRV593 and DRV594.
AREF CAPACITOR
The AREF terminal is the output of an internal mid-rail voltage regulator used for the onboard oscillator and ramp generator. The regulator may not be used to provide power to any additional circuitry. A 1 F ceramic capacitor must be connected from AREF to AGND for stability (see oscillator components above for AGND connection information).
SHUTDOWN OPERATION
The DRV593 and DRV594 include a shutdown mode that disables the outputs and places the device in a low supply current state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is held high, the device operates normally. When SHUTDOWN is held low, the device is placed in shutdown. The SHUTDOWN pin must not be left floating. If the shutdown feature is unused, the pin may be connected to VDD.
FAULT REPORTING
The DRV593 and DRV594 include circuitry to sense three faults:
D Overcurrent D Undervoltage D Overtemperature
These three fault conditions are decoded via the FAULT1 and FAULT0 terminals. Internally, these are open-drain outputs, so an external pullup resistor of 5 k or greater is required. Table 2. Fault Indicators
FAULT1 0 1 0 1 FAULT0 0 0 1 1 Overcurrent Undervoltage Overtemperature Normal operation
The overcurrent fault is reported when the output current exceeds four amps. As soon as the condition is sensed, the overcurrent fault is set and the outputs go into a high-impedance state for approximately 3 s to 5 s (500 kHz operation). After 3 s to 5 s, the outputs are re-enabled. If the overcurrent condition has ended, the fault is cleared and the device resumes normal operation. If the overcurrent condition still exists, the above sequence repeats. The undervoltage fault is reported when the operating voltage is reduced below 2.8 V. This fault is not latched, so as soon as the power supply recovers, the fault is cleared and normal operation resumes. During the undervoltage condition, the outputs go into a high-impedance state to prevent overdissipation due to increased rDS(on).
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The overtemperature fault is reported when the junction temperature exceeds 115C. The device continues operating normally until the junction temperature reaches 150C, at which point the IC is disabled to prevent permanent damage from occurring. The system's controller must reduce the power demanded from the DRV593 or DRV594 once the overtemperature flag is set, or else the device switches off when it reaches 150C. This fault is not latched; once the junction temperature drops below 115C, the fault is cleared, and normal operation resumes.
POWER DISSIPATION AND MAXIMUM AMBIENT TEMPERATURE
Though the DRV593 and DRV594 are much more efficient than traditional linear solutions, the power drop across the on-resistance of the output transistors does generate some heat in the package, which may be calculated as shown in equation (11):
P DISS +I
2
(11) r DS(on), total
OUT
For example, at the maximum output current of 3 A through a total on-resistance of 130 m (at TJ = 25C), the power dissipated in the package is 1.17 W. Calculate the maximum ambient temperature using equation (12):
T A + TJ * JA P (12) DISS
PRINTED-CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS
Since the DRV593 and DRV594 are high-current switching devices, a few guidelines for the layout of the printed-circuit board (PCB) must be considered: 1. Grounding. Analog ground (AGND) and power ground (PGND) must be kept separated, ideally back to where the power supply physically connects to the PCB, minimally back to the bulk decoupling capacitor (10 F ceramic minimum). Furthermore, the PowerPAD ground connection should be made to AGND, not PGND. Ground planes are not recommended for AGND or PGND, traces should be used to route the currents. Wide traces (100 mils) should be used for PGND while narrow traces (15 mils) should be used for AGND. 2. Power supply decoupling. A small 0.1 F to 1 F ceramic capacitor should be placed as close to each set of PVDD pins as possible, connecting from PVDD to PGND. A 0.1 F to 1 F ceramic capacitor should also be placed close to the AVDD pin, connecting from AVDD to AGND. A bulk decoupling capacitor of at least 10 F, preferably ceramic, should be placed close to the DRV593 or DRV594, from PVDD to PGND. If power supply lines are long, additional decoupling may be required. 3. Power and output traces. The power and output traces should be sized to handle the desired maximum output current. The output traces should be kept as short as possible to reduce EMI, i.e., the output filter should be placed as close to the DRV593 or DRV594 outputs as possible. 4. PowerPAD. The DRV593 and DRV594 in the Quad Flatpack package use TI's PowerPAD technology to enhance the thermal performance. The PowerPAD is physically connected to the substrate of the DRV593 and DRV594 silicon, which is connected to AGND. The PowerPAD ground connection should therefore be kept separate from PGND as described above. The pad underneath the AGND pin may be connected underneath the device to the PowerPAD ground connection for ease of routing. For additional information on PowerPAD PCB layout, refer to the PowerPAD Thermally Enhanced Package application note, SLMA002. 5. Thermal performance. For proper thermal performance, the PowerPAD must be soldered down to a thermal land, as described in the PowerPAD Thermally Enhanced Package application note, SLMA002. In addition, at high current levels (greater than 2 A) or high ambient temperatures (greater than 25C), an internal plane may be used for heat sinking. The vias under the PowerPAD should make a solid connection, and the plane should not be tied to ground except through the PowerPAD connection, as described above.
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MECHANICAL DATA
VFP (S-PQFP-G32) PowerPAD PLASTIC QUAD FLATPACK
0,80 24 17
0,45 0,30
0,22 M
25
16 Thermal Pad (See Note D)
32
9 0,13 NOM 1 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,25 8
Gage Plane
1,45 1,35
0,05 MIN
0-7
Seating Plane 1,60 MAX 0,10
0,75 0,45
4200791/A 04/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments. 19
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