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MG1
0.6 Micron Sea of Gates
Introduction
The MG1 series is a 0.6 micron, array based, CMOS product family offering a new frontier in integration and speed. Several arrays up to 500k cells cover all system integration needs. The MG1 is manufactured using SCMOS 2/2, a 0.6 micron drawn, 3 metal layers CMOS process. The MG1 series base cell architecture provides high routability of logic with extremely dense compiled memories : RAM, DPRAM and FIFO, ROM can be generated using synthesis tools. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 200,000 random gates. Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery : Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level. The MG1 is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Compass, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle. The MG1 family continues the Atmel Wireless & Microcontrollers offering in array based commercial, automotive, industrial, military and space circuits.
Features
D D D D D Full Range of Matrices up to 500k Cells 0.6 m Drawn CMOS, 3 Metal Layers, Sea of Gates RAM, DPRAM, FIFO Compilers Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG) High Speed Performances : - 250 ps Typical Gate Delay @5 V - 350 MHz Toggle Frequency @5 V High System Frequency Skew Control : - 250 MHz PLL for Clock Generation - Clock Tree Synthesis Software 3 & 5 Volts Operation; Single or Dual Supply Modes Low Power Consumption : - 0.9 W/Gate/MHz @3 V - 2.4 W/Gate/MHz @5 V Integrated Power on Reset Matrices With More than 500 Pads Standard 3, 6, 12m, 24mA I/Os, parallelism up to 48mA Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface ESD (2 kV) And Latch-up Protected I/O D High Noise & EMC Immunity : - I/O with Slew Rate Control - Internal Decoupling - Signal Filtering between Periphery & Core - Application Dependent Supply Routing & Several Independent Supply Sources D Wide Range of Packages Including PGA & CQFP D Delivery in Die Form D Advanced CAD Support : Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management D Cadence, Compass, Mentor & Synopsys Reference Platforms D EDIF & VHDL Reference Formats D Upward Compatibility With MC & MF Gate Arrays, MCM Composite Arrays. D Full Compatibility with MG1M Composite Sea of Gates Series D Available In Commercial, Industrial, Automotive, Military & Space Quality Grades D Special Versions on Radiation Tolerant Process D QML Q
D
D D
D D D D D D
1 Rev. F - June 29, 2000
MG1
Product Outline
Type*
MG1001 MG1004 MG1009 MG1014* MG1020 MG1033 MG1042* MG1052 MG1070 MG1090* MG1120 MG1140* MG1200* MG1265* MG1480*
Total Cells
1 829 3 608 9 100 13 846 19 879 32 984 42 000 52 104 70 059 89 162 118 472 140 049 196 384 264 375 480 255
Maximum Usable Cells**
1 371 2 706 6 825 10 384 14 909 24 738 31 500 39 078 52 544 66 871 88 854 105 036 147 288 198 281 360 191
Full Programmable I/ Os***
30 48 72 88 104 130 146 162 188 212 244 264 312 360 484
Total Pads
50 66 91 106 123 148 165 181 206 231 262 282 331 378 503
Total Die Size with scribe line (um)
2250x2260 2710x2700 3380x3360 3800x3790 4240x4230 5020x4990 5620x5590 6070x6030 6740x6730 7230x7370 8090x8240 8660x8640 9960x10110 11460x11440 14690x14850
* Must be used when Ceramic Package is mandatory ** The maximum number of usable gates is application dependant *** I/O pads may be configured as VSS or VDD supplies according to circuit requirements
2 Rev. F - June 29, 2000
MG1
Libraries
The MG1 cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available in VHDL, as example : I2C, UART, Timer, ...
Block Generators
Block generators are used to create a customer specific simulation model and metallisation pattern for regular functions like RAM, DPRAM & FIFO. The basic cell architecture allows one bit per cell for RAM and DPRAM. The main characteristics of these generators are summarised below.
Typical characteristics (16 k bits) Function Maximum Size (bits)
72 k 72 k 72 k
bits/word access time (ns)
1-144 1-144 1-144 8 8 8
consumption (mA/MHz)
1.6 3.3 2.1
Used cells
20 k 23 k 23 k
RAM DPRAM FIFO
I/O buffer interfacing
I/O Fexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator is located close to each buffer.
Outputs
Several kinds of CMOS and TTL output drivers are offered : fast buffers with 3, 6, 12 and 24 mA drive, low noise buffers with 12 mA drive.
Inputs
Input buffers with CMOS or TTL thresholds are non inverting and feature versions with and without hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull down terminators. For special purposes, a buffer allowing direct input to the matrix core is available.
3 Rev. F - June 29, 2000
MG1
Clock generation & PLL
Clock generation
Atmel Wireless & Microcontrollers offers 4 different types of oscillators : low power 32KHz crystal oscillator (up to Industrial Range), high frequency crystal oscillator and 2 RC oscillators. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms; the other characteristics are summarised below :
Frequency (MHz) Minimum
Xtal 32K Xtal 50 M RC 10M RC 32 M 0.03 2 0.02 10
- Skew control : the internal clock transitions are synchronous with the reference clock whatever the load and the depth of logic in the clock tree. - Frequency synthesis : two frequency dividers are included in each PLL. One divides the reference clock frequency F0 by a factor M and the other divides the internal clock frequency F by N. The internal clock frequency is : F = F0 * M / N Both M and N can take values from 1 to 16. The maximum frequency at the PLL input after division by M is 70 MHz. The maximum internal clock frequency is 250 MHz at 5 V and 150 MHz at 3 V ; the minimum frequency is 20 MHz. Each PLL corner block has 6 dedicated pads : 2 VDD, 3 VSS and a filtering I/O connected to an RC network.
Maximum
0.034 50 10 32
Typical consumption (A)
30 2 000 15 00 2 500
PLL
Two independent PLL devices are located in upper left and lower right corners. Each may be used for the following functions : - Synchronisation of an internal clock on a reference system clock.
4 Rev. F - June 29, 2000
MG1
Power supply & noise protection
The speed and density of the SCMOS 2/2 technology causes large switching current spikes for example either when : 16 high current output buffers switch simultaneously, or 10% of the 500 000 gates are switching within a window of 1ns . Sharp edges and high currents cause some parasitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. These drops can affect the behaviour of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the MG core matrix, several mechanisms have been implemented inside the MG arrays. Two kinds of protection have been added : one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. The power supplies of the input and output buffers are separated. The rise and fall times of the output buffers can be controlled by an internal regulator. A design rule concerning the number of buffers connected on the same power supply line has been imposed.
Matrix switching current protection
This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added : Some decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution lessens the parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers.
I/O Buffers switching protection
Three features are implemented to limit the noise generated by the switching current :
5 Rev. F - June 29, 2000
MG1
Power consumption
The power consumption of an MG1 array is due to three factors : leakage (P1), core (P2) and I/O (P3) consumption. P = P1 + P2 + P3
I/O Power Consumption
The power consumption due to the I/Os is : P3 = Ni * CO * (VDD - VSS)2 * Fi/2 With Ni equals to the number of buffers running at Fi and CO is the output capacitance. Note : If a signal is a clock, Fi = F, if it is a data with random values, Fi = F/4.
Standby Power Consumption
The consumption due to leakage currents may be defined as : P1 = (VDD - VSS) * ICCSB * NCELL Where ICCSB is the leakage current through a polarised basic gate and NCELL is the number of used cells.
Power Consumption Example
Matrix Used gates (70 %) Voltage Frequency MG1265 185 k 5 V** 40 MHz
Core Power Consumption
The consumtion due to the switching of cells in the core of the matrix is bounded by : P2 = NCELL * PGATE * CACTIVITY * F Where NCELL is the number of used cells, F the data toggling frequency is equal to half the clock frequency for random data and PGATE is the power consumption per cell. PGATE = PCA + PCO ACTIVITY is the fraction of the total number of cells toggling per cycle.
Standby Power
Iccsb (125C) P1 = (VDD - VSS) * ICCSB * NCELL 1 nA 1 mW
Core Power
Power Consumption per Cell Cactivity P2 = NCELL * PGATE * Cactivity * F 2.4 W/Gate/MHz 20 % 1775 mW
Capacitance Power
PCA = C * (VDD - VSS)2/2 C is the total output capacitance and may be expressed as the sum of the drain capacitance of the driver, the wiring capacitance and the gate capacitance of the inputs. Worst case value : PCA # 1.8 W/gate/MHz @ 5 V
I/O Power
Total Number of Buffers Number of Outputs and I/O Buffers Output Capacitance P3 = Ni * CO * (VDD - VSS)2 * Fi/2 364 100 50 pF 625 mW
Commutation Power
PCO = (VDD - VSS) * Idsohm Where Idsohm is the current flowing into the driver between supply and ground during the commutation. Idsohm is about 15 % of the Pmos saturation currrent. Worst case value : Pco # 0.7 W/gate/MHz @ 5 V
Total Power
P = P1 + P2 + P3 2.41 W
** Using 3V supply the power consumption will be reduced to 900mW
6 Rev. F - June 29, 2000
MG1
Packaging
Atmel Wireless & Microcontrollers offers a wide range of packaging options which are listed below :
Package Type
DQFP PLCCJ PQFP TQFB VQFP SSOP PSO MLCC MQFP CQFP MPGA
Pins min/max**
100 128 28 84 44 240 44 64 64 140 16 8 28 68 84 100 352 44 176 256
Lead spacing (inch*)
0.0256 0.0315 0.050 0.050 0.0315 0.0197 0.0394 0.0315 0.0197 0.0197 0.0256 0.050 0.050 0.050 0.050 0.0256 0.020 0.050 0.10 0.10
Dimension (inch*)
0.546x0.782 1.1022 0.4532 0.6532 0.3892 1.262 0.3942 0.5512 0.3902 0.7872 0.209x0.244 0.153x0.194 0.705x0.295 0.9502 1.1502 0.787x0.551 1.8892 0.6502 1.52 2.02
* To get the linear values in milimeters, multiply by 25.4 ** Please contact Atmel Wireless & Microcontrollers Local Design Contes to check the availability of the use matrix and the plan package.
7 Rev. F - June 29, 2000
MG1
Design flows & tools
Design Flows and modes
A generic design flow for an MG1 array is sketched on next page. A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step, structural verification is performed which includes the following tasks : - Gate level logic simulation and comparison with high level simulation results. - Design and test rule check. - Power consumption analysis. - Timing analysis (only after floor plan). The main design stages are : - System specification, preferably in VHDL form. - Functional description at RTL level. - Logic synthesis. - Floor planning and bonding diagram generation. - Test insertion, ATG and/or fault simulation. - Physical cell placement, JTAG insertion and clock tree synthesis. - Routing To meet the various requirements of designers, several interface levels between the customer and Atmel Wireless & Microcontrollers are possible. For each of the possible design modes a review meeting is required for data transfer from the user to Atmel Wireless & Microcontrollers. In all cases the final routing and verifications are performed by Atmel Wireless & Microcontrollers. The design acceptance is formalised by a design review which authorises Atmel Wireless & Microcontrollers to proceed with sample manufacturing.
MG1 Design Flow
System Specifications RTL Simulation Logic synthesis Floor Plan Bonding diagram Scan insertion ATG & Fault Simulation
Placement
JTAG insertion Clock Tree Synthesis
Routing Samples Manufacturing and Test
8 Rev. F - June 29, 2000
MG1
Design tool and design kits (DK)
The basic content of a design kit is described in the table on the right. The interface formats to and from Atmel Wireless & Microcontrollers rely on IEEE or industry standard : - VHDL for functional descriptions - VHDL or EDIF for netlists - Tabular or .CAP for simulation results - SDF (VITAL format) and SPF for backannotation - LEF and DEF for physical floor plan information The design kit supported for several commercial tools is outlined in the table below.
Design Kit Support
Cadence Mentor Synopsys Compass Viewlogic
VHDL
* * * * *
Gate
* * *
Design kit Description
Design Tool or library
Design manual & libraries VHDL library for blocks Synthesis library Gate level simulation library Design rules analyser Power consumption analyser Floor plan library Timing analyser library Package & bonding software Scan path & JTAG insertion ATG & fault simulation library PIM ASIS/AJIS STAR COMET
Atmel Software Name
9 Rev. F - June 29, 2000
MG1
Operating characteristics
Absolute Maximum Ratings
Ambient temperature under bias (TA) Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125C Junction temperature . . . . . . . . . . . . . . . . . . TJ < TA + 20C Storage temperature . . . . . . . . . . . . . . . . . . . . -65 to +150C TTL/CMOS : Supply voltage VDD . . . . . . . . . . . . . . . . . . . -0.5 V to +7 V I/O voltage . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Stresses above those listed may cause permanent damage to the device. Explosure to absolute maximum rating conditions for extended period may affect device reliability.
DC Characteristics
Specified at VDD = +5 V +/- 10 %
Symbol
VIL
Parameter
Input LOW voltage CMOS input TTL input Input HIGH voltage CMOS input TTL input Output low voltage CMOS input TTL input Output high voltage CMOS input TTL input Schmitt trigger positive threshold CMOS input TTL input Schmitt trigger negative threshold CMOS input TTL input Input leakage No pull up/down Pull up Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current per cell Operating current per cell
Min
0 0 0.7VDD 2.2
Typ
Max
0.3VDD 0.8 VDD VDD 0.1VDD 0.4
Unit
V
Conditions
VIH
V V IOL = -12, 6, 3 mA*
VOL
VOH
V 3.9 2.4 2.6 1.7 1.3 1.1 1.4 1.2 +/-1 -50 +180 +/-1 +/-5 +450 +/-5 48 36 0.35 0.5 5 3.2 1.9 V
IOH = -12, 6, 3 mA*
VT+
VT-
V
IL
-250
A A A A mA mA nA A/MHz VOUT = VDD VOUT = VSS
IOZ IOS
ICCSB ISSOP
* For each of the following buffers: Bout12, Bout6, Bout3
10 Rev. F - June 29, 2000
MG1
DC Characteristics
Specified at VDD = +3 V - 10 % or 3.3 +/- 10%
Symbol
VIL
Parameter
Input LOW voltage CMOS input TTL input Input HIGH voltage CMOS input TTL input Output LOW voltage CMOS input TTL input Output HIGH voltage TTL input Schmitt trigger positive threshold CMOS input TTL input Schmitt trigger negative threshold CMOS input TTL input Input leakage No pull up/down Pull up Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current per cell Operating current per cell
Min
0 0 0.7VDD 2.2
Typ
Max
0.3VDD 0.8 VDD VDD 0.1VDD 0.4
Unit
V
Conditions
VIH
V V IOL = -6, 3, 1.5 mA*
VOL
VOH VT+
2.4 1.8 1.3 0.9 0.9 1.0 1.0 +/-1 +100 +/-1 24 12 0.1 0.3 2.0 1.4
V
IOH = -4, 2, 1 mA*
V V
VT-
IL
-50 -50
-10 20
A A A A m mA nA A/MHz VOUT = VDD VOUT = VSS
IOZ IOS
ISSDP ISSOP
* For each of the following buffers : Bout12, Bout6, Bout3
11 Rev. F - June 29, 2000
MG1
AC Characteristics
TJ = 25C, Process typical (all values in ns)
VDD Buffer
BOUT12
Description
Output buffer with 12 mA drive
Load
60pf
Transition 5V
Tplh Tphl 2.72 2.77
3V
4.72 4.42
VDD Cell
BINCMOS
Description
CMOS input buffer
Load
15
Transition 5V
Tplh Tphl 1.28 1.21 1.43 1.58 0.84 0.42 1.06 0.87 0.46 0.10
3V
1.96 1.78 2.10 1.75 1.36 0.64 1.82 1.47 1.11 0.22
BINTTL
TTL input buffer
16
Tplh Tphl
INV
Inverter
12
Tplh Tphl
FDFF
D flip-flop, Clk to Q
8
Tplh Tphl Ts Th
12 Rev. F - June 29, 2000

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