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CY2081
Low-Cost Three-PLL Clock Generator
Features
* Factory-EPROM configurable for quick availability and prototyping. * General purpose clock synthesizer for all applications - such as modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes, data/telecommunications, etc. * Three independent configurable clock outputs * Outputs ranging from 500 kHz to 100 MHz (5V) and up to 80 MHz for 3.3V operation * Configurable output control pin (pin 8) can be used as an output enable, power-down, suspend or select line. * Phase-locked loop oscillator input derived from external crystal (10 MHz to 25 MHz) or external reference clock (1 MHz to 30 MHz) * 3.3V or 5V operation (factory configured) * 8-pin 150-mil packaging achieves minimum footprint for space-critical applications * Sophisticated internal loop filter requires no external components or manufacturing tweaks as commonly required with external filters ured to operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10 MHz to 25 MHz crystals. Alternatively, a reference clock between 1 MHz and 30 MHz can be used. The CY2081 also features an output control pin (pin 8) which can be configured as an output enable, power down, frequency select, or suspend input. This gives the user the ability to three-state the output, power down the device, change the CLKA output frequency during operation, or suspend any of the outputs. Asserting the PD input will result in all the PLLs and the outputs being shut down. The PLLs will have to re-lock when the PD input is deasserted. The CY2081 outputs three clocks: CLKA, CLKB, and CLKC, whose frequencies can possess any value within the specified range. Additionally, the reference frequency can be obtained on any output. Custom configurations with user-defined features and frequencies can be obtained by filling out the custom configuration form located at the back of this data sheet and contacting your local Cypress representative. The CY2081 can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to manufacturers. Hence, this device is ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers. Consider using the CY2291, CY2292, or CY2907 for applications that require more than three output clocks.
Functional Description
The CY2081 is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes and data/telecommunications. This devices offers three configurable clock outputs in an 8-pin 150-mil SOIC package and can be config-
Logic Block Diagram
Pin Configuration
SOIC Top View
CLKA GND XTALIN XTALOUT
1 2 3 4 8 7 6 5
OE/PD/FS/SUSPEND V DD CLKC CLKB
2081-1
XTALIN XTALOUT
Reference Oscillator
PLL 1 EPROMConfigurable Multiplexer and Divide Logic
CLKA
PLL 2
CLKB
PLL 3
CLKC
OE/PD/FS/SUSPEND
2081-2
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 September 1995 - Revised July 1996
CY2081
Pin Summary
Name CLKA GND XTALIN[1] XTALOUT CLKB CLKC VDD
[1,2]
Number 1 2 3 4 5 6 7
Description Configurable clock output Ground Reference Crystal Input or External Reference Clock Input Reference Crystal Feedback Configurable clock output Configurable clock output Voltage Supply Output control pin; either active-HIGH Output Enable, active-LOW power down, CLKA Frequency Select, or active-LOW Suspend input Storage Temperature ................................ -65C to +150C Max. Soldering Temperature (10 sec)..........................260C Junction Temperature ..................................................150C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015)
OE / PD / FS / SUSPEND 8
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage............................................... -0.5V to +7.0V DC Input Voltage .....................................-0.5V to VDD+0.5V
Operating Conditions[3]
Parameter VDD TA CL fREF fREF Supply Voltage Operating Temperature, Ambient Max. Load Capacitance per output External Reference Crystal External Reference Clock[4, 5] 10.0 1.0 Description Min. 4.5 (3.0) 0 Max. 5.5 (3.6) 70 25 (15) 25.0 30.0 Unit V C pF MHz MHz
Electrical Characteristics VDD = 5V (3.3V) 10%, TA = 0C to +70C
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IDDS Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[7] VDD Power Supply Current in Powerdown Mode
[6]
Conditions IOH = -4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD - 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 5V (3.3V) operation, C L = 25 pF (15 pF) Powerdown Active, 5V Operation
Min. 2.4
Typ.
Max. 0.4
Unit V V V V A A A mA A
2.0 0.8 <100 <100 40 (24) 100 150 150 250 60 (40) 200
LOW-Level Output Voltage[6]
Notes: 1. For best accuracy, use a parallel-resonant crystal, CL=17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal). 3. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses. 4. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 5. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 6. Xtal inputs have CMOS thresholds. 7. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary.
2
CY2081
Switching Characteristics[8]
Parameter t1 t1 t1A t1B t1C t1D Name Output Period Output Period Clock Jitter[9] Clock Jitter[9] Clock Jitter[9] Clock Jitter[9] Output Duty Cycle[10] Description Clock output range, 5V operation Clock output range, 3.3V operation Peak-to-peak period jitter, % of clock period (fOUT 4 MHz) Peak-to-peak period jitter (4 MHz fOUT 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle for outputs, defined as t2 / t1[11] fOUT > 66.67 MHz Duty cycle for outputs, defined as t2 / t1[11] fOUT 66.67 MHz t3 t4 t5 t6 Rise time Fall time Output clock rise time[12] at CL=25 pF (15 pF at 3.3V operation) Output clock fall time[12] at CL=25 pF (15 pF at 3.3V operation) 1 40% 45% Min. 10 [100 MHz] 12.5 [80 MHz] <0.5 <0.7 <400 <250 50% 50% 3 2.5 5 < 25 Typ. Max. 2000 [500 KHz] 2000 [500 KHz] 1 1 500 350 60% 55% 5 4 40 50 ns ns MHz/ ms ms Unit ns ns % ns ps ps
Frequency Slew Rate Rate of change of frequency of CLKA Power Up Stabilization Time Output clock stable time after power up
Switching Waveforms
All Outputs Duty Cycle and Rise/Fall Time
t1 t2 OUTPUT 2.4V 0.4V t3 2.4V 0.4V t4
2081-3
3.3V 0V
Notes: 8. Guaranteed by design, not 100% tested. 9. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: "Jitter in PLL-Based Systems." 10. Reference Output duty cycle depends on XTALIN duty cycle. 11. Measured at 1.4V. 12. Measured between 0.4V and 2.4V.
3
CY2081
Test Circuit
VDD 0.1 F
7 OUTPUTS 2
2081-4
CLK output CLOAD
GND Ordering Information
Ordering Code CY2081SC-XXX CY2081SL-XXX
Notes: 13. 0C to +70C
Package Name S8 S8
Package Type 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC
Operating Range 5.0V, Commercial[13] 3.3V, Commercial[13]
Document #: 38-00463-A
4
CY2081
Package Diagrams
8-Lead (150-Mil) SOIC S8
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2081
CY2081 CONFIGURATION REQUEST FORM
Customer Phone # Engineer Fax # 3.3V FAE/Sales Date 5.0V
1. OPERATING VOLTAGE (circle one)
2. INPUT REFERENCE FREQUENCY (Circle one)
Crystal
External Clock
Default reference = 14.318 MHz. If a different reference is desired, specify the frequency in the box to the right (must be between 10 MHz and 25 MHz for crystal, 1 MHz and 30 MHz for external clock):
3. OUTPUT CONTROL PIN (PIN 8) CONFIGURATION (Circle one) OE (Default) PD FS SUSPEND
If the Suspend option is desired, please circle what outputs must be suspended
CLKA
CLKB
CLKC
4. OUTPUT CONFIGURATION
Fill in the desired frequencies, specifying kHz or MHz, for each output. Please adhere to the notes at the right. Contact your local Cypress representative for assistance. After configuration, please fax the form to your local Cypress representative.
Notes: CLKA (FS=0) CLKA (FS=1) CLKB CLKC
* * *
If pin 8 is OE, PD or SUSPEND, fill in only one value for CLKA Buffered reference clock is available on all outputs. CLKA, CLKB and CLKC, outputs can range from 500 kHz to 100 MHz (80 MHz at 3.3V)
5. FOR CYPRESS USE ONLY
Customer Configuration Date Marking Quantity
6

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