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CS5361 114 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
l Advanced
General Description
The CS5361 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-todigital conversion and anti-alias filtering, generating 24bit values for both left and right inputs in serial form at sample rates up to 192 kHz per channel. The CS5361 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADC uses a differential architecture which provides excellent noise rejection. The CS5361 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD-R, CD-R, digital mixing consoles, effects processors, and automotive applications. ORDERING INFORMATION CS5361-KS -10 to 70 C 24-pin SOIC CS5361-BS -40 to 85 C 24-pin SOIC CDB5361 Evaluation Board
Multi-bit Delta-Sigma Architecture l 24-Bit Conversion l 114 dB Dynamic Range l -100 dB THD+N l System Sampling Rates up to 192 kHz l Less than 150 mW Power Consumption l High Pass Filter or DC Offset Calibration l Supports Logic Levels Between 5 and 1.8V l Differential Analog Architecture l Linear Phase Digital Anti-Alias Filtering
VCOM
REFGND
VL SCLK
LRCK SDOUT
MCLK
FILT+
Voltage Reference
Serial Output Interface
RST DIF M/S HPF DIV
AINLAINL+ S/H
+ -
LP Filter
Q
Digital Decimation Filter
High Pass Filter
DAC AINRAINR+ S/H DAC + LP Filter Q Digital Decimation Filter High Pass Filter MODE0 MODE1
Advance Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved)
SEP `01 DS467PP1 1
CS5361
TABLE OF CONTENTS
1 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 4 ANALOG CHARACTERISTICS ................................................................................................ 4 DIGITAL FILTER CHARACTERISTICS.................................................................................... 5 POWER AND THERMAL CHARACTERISTICS....................................................................... 6 DIGITAL CHARACTERISTICS ................................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7 RECOMMENDED OPERATING CONDITIONS ....................................................................... 7 SWITCHING CHARACTERISTICS .......................................................................................... 8 2 TYPICAL CONNECTION DIAGRAM ....................................................................................... 10 3 PIN DESCRIPTIONS ............................................................................................................... 11 4 APPLICATIONS ....................................................................................................................... 13 4.1 General Description ......................................................................................................... 13 4.2 High Pass Filter ................................................................................................................ 13 4.3 Analog Connections ......................................................................................................... 13 4.4 Power-up ......................................................................................................................... 13 4.5 Synchronization of Multiple Devices ................................................................................ 13 4.6 Master/Slave Mode Operation ......................................................................................... 14 4.7 High Pass Filter and DC Offset Calibration ...................................................................... 14 4.8 Grounding and Power Supply Decoupling ....................................................................... 15 4.9 Digital Filter ...................................................................................................................... 15 5 PARAMETER DEFINITIONS ................................................................................................... 18 6 REFERENCES ......................................................................................................................... 19 7 PACKAGE DIMENSIONS......................................................................................................... 20
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
CS5361
LIST OF FIGURES
Figure 1. Master Mode, Left Justified (DIF low) .............................................................................. 9 Figure 2. Slave Mode, Left Justified (DIF low) ................................................................................ 9 Figure 3. Master Mode, I2S Format (DIF high)................................................................................ 9 Figure 4. Slave Mode, I2S Format (DIF high).................................................................................. 9 Figure 5. Typical Connection Diagram.......................................................................................... 10 Figure 6. CS5361 Master Mode: LRCK Generation...................................................................... 14 Figure 7. CS5361 Master Mode: SCLK Generation...................................................................... 14 Figure 8. Left Justified Format, DIF Low ....................................................................................... 15 Figure 9. I2S Format, DIF High ..................................................................................................... 15 Figure 10. Full Scale Input Voltage ............................................................................................... 15 Figure 11. Single Speed Mode Stopband Rejection ..................................................................... 16 Figure 12. Single Speed Mode Transistion Band.......................................................................... 16 Figure 13. Single Speed Mode Transition Band (Detail)............................................................... 16 Figure 14. Single Speed Mode Passband Ripple ......................................................................... 16 Figure 15. Double Speed Mode Stopband Rejection.................................................................... 16 Figure 16. Double Speed Mode Transistion Band ........................................................................ 16 Figure 17. Double Speed Mode Transition Band (Detail) ............................................................. 17 Figure 18. Double Speed Mode Passband Ripple ........................................................................ 17 Figure 19. Quad Speed Mode Stopband Rejection ...................................................................... 17 Figure 20. Quad Speed Mode Transistion Band........................................................................... 17 Figure 21. Quad Speed Mode Transition Band (Detail) ................................................................ 17 Figure 22. Quad Speed Mode Passband Ripple........................................................................... 17
LIST OF TABLES
Table 1. CS5361 Common Master Clock Frequencies ...................................................................... 12 Table 2. CS5361 Mode Control ........................................................................................................... 12 Table 3. CS5361 SCLK/LRCK Ratios ................................................................................................. 14 Table 4. CS5361 MCLK/LRCK Ratios................................................................................................. 14
3
CS5361
1 CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; Logic "0" = GND = 0 V; Logic "1" = VL = 5V; MCLK =
12.288 MHz, Fs for Single Speed Mode = 48 kHz, Fs for Double Speed Mode = 96 kHz, Fs for Quad Speed Mode = 192 kHz, SCLK = 64 Fs, Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 997Hz sine wave.) CS5361KS Typ 114 111 -100 -91 -51 114 111 -100 -91 -51 114 111 -100 -91 -51 110 0.0001 0.1 +/-100 0 2.0 82 CS5361BS Typ 114 111 -100 -91 -51 114 111 -100 -91 -51 114 111 -100 -91 -51 110 0.0001 0.1 +/-100 0 2.0 82
Parameter Symbol Single Speed Mode Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise THD+N -1 dB -20 dB -60 dB Double Speed Mode Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise THD+N -1 dB -20 dB -60 dB Quad Speed Mode Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise THD+N -1 dB -20 dB -60 dB Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error with HPF active Analog Input Characteristics Full-scale Input Voltage Input Impedance (Differential)* Common Mode Rejection Ratio CMRR * Measured between AIN+ and AIN-
Min TBD TBD TBD TBD TBD TBD TBD 37 -
Max TBD TBD TBD TBD TBD -
Min TBD TBD TBD TBD TBD TBD TBD 37 -
Max TBD TBD TBD TBD TBD -
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Degree dB % ppm/C LSB Vrms k dB
4
CS5361
DIGITAL FILTER CHARACTERISTICS
Parameter Single Speed Mode (2kHz to 50kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency Double Speed Mode (50kHz to 100kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency Quad Speed Mode (100kHz to 192kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple -3.0 dB -0.13 dB @ 20Hz (Note 1) (Note 1) 1 20 10 0 Hz Hz Deg dB tgd tgd (-0.1 dB) 0 148.8 -97 5/Fs 47 0.035 0.0 kHz dB kHz dB s s tgd tgd (-0.1 dB) 0 64.3 -92 9/Fs 43.2 0.035 0.0 kHz dB kHz dB s s tgd tgd (-0.1 dB) 0 27.8 -95 12/Fs 22.5 0.035 0.0 kHz dB kHz dB s s Symbol Min Typ Max Unit
Notes: 1. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
5
CS5361
POWER AND THERMAL CHARACTERISTICS (TA = 25 C; VA = 5V; MCLK=12.288 MHz;
Master Mode) Parameter Power Supply Current (Normal Operation) VA VL,VD = 5 V VL,VD = 3.3V VA VD=5V Symbol Min IA ID ID IA ID CS5361-KS Typ Max 15 12 TBD 2 2 135 TBD 20 65 TBD TBD TBD TBD TBD 135 Min CS5361-BS Typ 15 12 TBD 2 2 135 TBD 20 65 TBD Max TBD TBD TBD TBD 135 Unit mA mA mA mA mA mW mW mW dB C C/W
Power Supply Current (Power-Down Mode) (Note 2)
Power Consumption (Normal Operation) VD=5V VD = 3.3V (Power-Down Mode)
Power Supply Rejection Ratio (1 kHz) PSRR (Note 3) Allowable Junction Temperature Junction to Ambient Thermal Impedance
JA
-
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 20 A Low-Level Output Voltage at Io = 20 A Input Leakage Current
(TA = 25 C; VD = 5V5%) Symbol (% of VL) (% of VL) VIH VIL VOH VOL Iin Min 70% VL - 1.0 Typ Max 30% 0.4 10 Units V V V V A
Notes: 2. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 3. Valid with the recommended capacitor values on FILT+ and VCOM as shown in the Typical Connection Diagram.
6
CS5361
ABSOLUTE MAXIMUM RATINGS (GND = 0V, All voltages with respect to ground.)
Parameter DC Power Supplies: Analog Logic Digital (Note 4) (Note 5) (Note 5) Symbol VA VL VD Iin VIN VIND TA Tstg Min -0.3 -0.3 -0.3 GND-0.7 -0.7 -55 -65 Typ Max +6.0 +6.0 +6.0 10 VA+0.7 VL+0.7 +70 +150 Units V V V mA V V C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 4. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 5. The maximum over/under voltage is limited by the input current. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V, all voltages with respect to
ground.) Parameter DC Power Supplies: Positive Analog Positive Digital Positive Logic CS5361-KS CS5361-BS Symbol VA VD VL TA TA Min 4.75 3.1 1.7 -10 -40 Typ 5.0 Max 5.25 5.25 5.25 +70 +85 Units V V V C C
Ambient Operating Temperature (Power Applied)
7
CS5361
SWITCHING CHARACTERISTICS (TA = 25 C; Logic "0" = GND = 0 V; Logic "1" = VL = VA = VD =
5 V, CL = 20 pF) Parameter Input Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs tclkw tclkh tclkl tmslr tsdo Min 2 50 100 40 15 15 -20 0 Typ 50 64*Fs
MCLK/256
Max 50 100 192 1953 20 40 -
Unit kHz kHz kHz ns ns ns ns ns % Hz Hz
MCLK Specifications MCLK Period MCLK Pulse Width High MCLK Pulse Width Low Master Mode SCLK falling to LRCK SCLK falling to SDOUT valid SCLK Duty Cycle SCLK Output Frequency LRCK Output Frequency (Fs) Slave Mode Single Speed LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge Double Speed LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge Quad Speed LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge tsclkw tsclkhl tdss tslrd 40 81 20 -10 50 60 20 10 % ns ns ns ns tsclkw tsclkhl tdss tslrd 40 163 20 -20 50 60 40 20 % ns ns ns ns tsclkw tsclkhl tdss tslrd 40 163 20 -20 50 60 40 20 % ns ns ns ns
8
CS5361
t sclkh t sclkl
SCLK output t mslr LRCK output t sdo SDOUT MSB MSB-1
SDOUT LRCK input t lrdss MSB MSB-1 t dss MSB-2 SCLK input t sl rd t sclkw
Figure 1. Master Mode, Left Justified (DIF low)
Figure 2. Slave Mode, Left Justified (DIF low)
t sclkh t sclkl
SCLK output t mslr LRCK output t sdo SDOUT MSB
SDOUT
LRCK input t dss MSB MSB-1 SCLK input t sclkw
Figure 3. Master Mode, I2S Format (DIF high)
Figure 4. Slave Mode, I2S Format (DIF high)
9
CS5361
2 TYPICAL CONNECTION DIAGRAM
+5 V to 3.3 V
+ 1 F
0.1 F
0.1 F
+
1 F
+5V to 1.8V
+5V
+
1 F
0.1 F VA FILT+
5.1 VD
0.1 F
VL
10 F
+
0.1 F
REFGND +
1 F 0.1 F
VCOM Left Analog Input + 150 1000 pF 150 Left Analog Input Right Analog Input + 150 1000 pF 150 Right Analog Input AINR+
*
AINL+
*
CS5361 A/D CONVERTER
RST DIF M/S HPF M0 M1 DIV
Power Down and Mode Settings
AINLSDOUT Audio Data Processor
LRCK SCLK MCLK Timing Logic and Clock
AINR-
GND
* Capacitors should be of the type COG or equivalent
GND
Figure 5. Typical Connection Diagram
10
CS5361
3 PIN DESCRIPTIONS
Reset RST Master/Slave Mode M/S Left/Right Clock LRCK Serial Data Clock SCLK Master Clock MCLK Digital Power VD Ground GND Logic Level VL Serial Data SDOUT MCLK Divider DIV High Pass Filter Enable HPF Digital Interface Format DIF 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FILT+ REFGND VCOM AINR+ AINRVA GND AINLAINL+ TST M1 M0 Voltage Reference Reference Ground Common Mode Voltage Right Channel Analog Input+ Right Channel Analog InputAnalog Power Ground Left Channel Analog InputLeft Channel Analog Input+ Test Pin Mode Select Mode Select
Power Supply and Ground Pin Name
RST M/S
# 1 2
Pin Description
Reset (Input) - The device enters a low power mode when low. Master/Slave Mode (Input) - In Master mode, SCLK and LRCK are outputs. Internal dividers divide the master clock to generate the serial clock and the left/right clock. In Slave mode, LRCK and SCLK become inputs. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 1 illustrates several standard audio sample rates and the required master clock frequency. Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages.
LRCK SCLK MCLK VD GND VL SDOUT DIV HPF
3 4 5 6
7,18 Ground (Input) - Ground reference. Must be connected to analog ground. 8 9 10 11
Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to the Recommended Operating Conditions for appropriate voltages. Serial Audio Data Output (Output) - Output for two's complement serial audio data. MCLK Divider (Input) - When high, the externally supplied MCLK is divided by two prior to all other chip circuitry. High Pass Filter Enable (Input) - The device includes a high pass filter after the decimator to remove the indeterminate DC offsets introduced by the analog buffer stage and the analog modulator. The firstorder high pass filter response characteristics are detailed in the Digital Filter specifications table. The filter response scales linearly with sample rate. Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format selection. Refer to Figures 8 and 9.
DIF M0 M1 TST AINL+ AINL-
12
13, Mode Selection (Input) - Determines the operational mode of the device as detailed in Table 2. 14 15
Test Pin (Input) - This pin needs to be connected to GND.
16, Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma 17 modulators via the AINL+/- pins. The full scale differential analog input level is specified in the Analog
Characteristics Specification table.
11
CS5361
VA AINR+ AINRVCOM REF_GND FILT+
19
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages.
20, Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma 21 modulators via the AINR+/- pins. The full scale differential analog input level is specified in the Analog
Characteristics Specification table.
22 23 24
Common Mode Voltage (Output) - Nominally 2.5 volts; can be used to bias the analog input circuitry to the common mode voltage of the CS5361. VCOM is not buffered and the maximum current is 10 uA. Reference Ground (Input) - Ground reference for the internal sampling circuits and must be connected to analog ground. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to GND as shown in the Typical Connection Diagram.
SAMPLE RATE (kHz) 32 44.1 48 64 88.2 96 176.4 192
DIV = 1 MCLK (MHz) 8.192 11.2896 12.288 8.192 11.2896 12.288 11.2896 12.288
DIV = 0 MCLK (MHz) 16.384 22.5792 24.576 16.384 22.5792 24.576 22.5792 24.576
Table 1. CS5361 Common Master Clock Frequencies
Mode 1 0 0 1 1
Mode 0 0 1 0 1
MODE Single Speed Mode Double Speed Mode Quad Speed Mode Reserved
Table 2. CS5361 Mode Control
12
CS5361
4 APPLICATIONS 4.1 General Description
The CS5361 is a 24-bit, stereo A/D converter designed for digital audio applications. The analog input channels are simultaneously sampled by separate, 5th-order delta-sigma modulators. The resulting serial bit streams are digitally filtered, yielding pairs of 24-bit values at output sample rates (Fs) of up to 192 kHz. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converter does not require anti-alias filters, external sample-and-hold amplifiers or voltage references. Only normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for anti-aliasing are required, as shown in Figure 5. Output data is available in serial form, coded as 2's complement 24-bit numbers. For more information on delta-sigma modulation techniques see the references at the end of this data sheet. 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. If active circuitry precedes the ADC, it is recommended that the above RC filter is placed between the active circuitry and the AINR and AINL pins.
4.4
Power-up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. Due to the presence of external capacitance on the FILT+ pin, a time delay of approximately 10ns/F is required after applying power to the device or after exiting a reset state for the reference to come up. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the reset pin high.
4.2
High Pass Filter
The CS5361 includes a digital high pass filter after the decimator to remove the indeterminate DC offsets introduced by the analog buffer stage and the CS5361 analog modulator. The first-order high pass filter is detailed in the Digital Filter specifications table. The filter response scales linearly with the sample rate.
4.5
Synchronization of Multiple Devices
4.3
Analog Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to the Typical Connection Diagram which shows the suggested filter that will attenuate any noise energy at
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all CS5361's in the system. If only one master clock source is needed, one solution is to place one CS5361 in Master mode, and slave all of the other CS5361's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5361 reset with the inactive edge of MCLK. This will ensure that all of the CS5361's in the system will begin sampling on the same clock edge.
13
CS5361
4.6 Master/Slave Mode Operation
Master Mode Slave Mode Mode0 (SSM) 64x 32x, 64x, 128x Mode1 (DSM) 64x 32x, 64x Mode2 (QSM) 64x 64x
The CS5361 can operate in Master or Slave mode, which is selectable via pin 2 (M/S). In Master mode, LRCK and SCLK are outputs. The CS5361 will produce an LRCK that is equal to the output sample rate, Fs, and an SCLK that is 64x Fs.
MCLK / 64 Quad Speed
Table 3. CS5361 SCLK/LRCK Ratios
The MCLK/LRCK ratio requirements for Master and Slave mode operation is described in Table 4.
Mode0 (SSM) Master Mode 256x 256x Mode1 (DSM) 128x 128x Mode2 (QSM) 64x 128x
/ 128
Double Speed Single Speed
MUX
LRCK
Slave Mode
Table 4. CS5361 MCLK/LRCK Ratios
/ 256
4.7
High Pass Filter and DC Offset Calibration
M0 M1
Figure 6. CS5361 Master Mode: LRCK Generation
MCLK /1 Quad Speed Double Speed Single Speed MUX SCLK
/2
The operational amplifiers in the input circuitry driving the CS5361 may generate a small DC offset into the A/D converter. The CS5361 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter can be removed from the signal path by keeping the HPF pin high as the part comes out of reset. The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:
1) running the CS5361 with the high pass filter enabled for approximately 1 second until the filter settles followed by 2) disabling the high pass filter and freezing the stored DC offset.
/4
M0 M1
Figure 7. CS5361 Master Mode: SCLK Generation In
Slave mode, LRCK and SCLK become inputs. The LRCK must be equal to the sample rate, Fs. The SCLK must be equal to 128x, 64x, or 32x Fs. It is recommended that SCLK be equal to 64x Fs to avoid potential interference effects which may degrade system performance. See Table 3 for more details.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5361.
14
CS5361
4.8 Grounding and Power Supply Decoupling
evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
As with any high resolution converter, the CS5361 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 5 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Please refer to the Recommended Operating Conditions for supply voltage ranges. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VCOM pins in order to avoid unwanted coupling into the modulators. The FILT+ and VCOM decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and pin 23, REFGND. The CDB5361
LRCK Left Channel
4.9
Digital Filter
Figures 11-22 show the performance of the digital filter included in the CS5361. All plots are normalized to Fs. Assuming a sample rate of 48 kHz, the 0.5 frequency point on the plot refers to 24 kHz. The filter frequency response scales precisely with Fs.
Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 8. Left Justified Format, DIF Low
LRCK Left Channel Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 9. I2S Format, DIF High
CS5361
3.9 V 2.5 V 1.0 V 3.9 V 2.5 V 1.0 V
AIN+
AIN-
Full Scale Input level= (AIN+) - (AIN-)= 5.6 Vpp
Figure 10. Full Scale Input Voltage
15
CS5361
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 11. Single Speed Mode Stopband Rejection
0
Figure 12. Single Speed Mode Transition Band
0.10
-1
0.08
-2
0.05
-3
Amplitude (dB)
-5
Amplitude (dB)
0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
-4
0.03
0.00
-6
-0.03
-7
-0.05
-8
-9
-0.08
-10 0.45
Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 13. Single Speed Mode Transition Band (Detail)
0 -10 -20 -30 -40 -50 Amplitude (dB)
Figure 14. Single Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
-60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Figure 15. Double Speed Mode Stopband Rejection
Figure 16. Double Speed Mode Transition Band
16
CS5361
0
0.10
-1
0.08
-2
0.05
-3
Amplitude (dB)
-5
Amplitude (dB)
0.43 0.45 0.48 Frequency (normalized to Fs) 0.50 0.53 0.55
-4
0.03
0.00
-6
-0.03
-7
-8
-0.05
-9
-0.08
-10 0.40
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 17. Double Speed Mode Transition Band (Detail)
Figure 18. Double Speed Mode Passband Ripple
0 -10 -20 -30 -40 Amplitude (dB) -50 -60 -70 -80
Amplitude (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
-90 -100 -110 -120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
-100 -110 -120 -130 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Frequency (normalized to Fs)
Figure 19. Quad Speed Mode Stopband Rejection
0
Figure 20. Quad Speed Mode Transition Band
0.10
-1
0.08
-2
0.06
-3
0.04
Amplitude (dB)
-5
Amplitude (dB)
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-4
0.02
0.00
-6
-0.02
-7
-0.04
-8
-0.06
-9
-0.08
-10 Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
Figure 21. Quad Speed Mode Transition Band (Detail)
Figure 22. Quad Speed Mode Passband Ripple
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CS5361
5 PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Dynamic Range
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CS5361
6 REFERENCES
3) "The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's" by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 4) "An 18-Bit Dual-Channel Oversampling DeltaSigma A/D Converter, with 19-Bit Mono Application Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 5) "How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters" by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.
1) "Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit" by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. 2) "A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio" by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988.
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CS5361
7 PACKAGE DIMENSIONS
24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.27 0 8
20
* Notes *

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