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* 8 AVR(R) * RISC
- 131 - - 32 8 - - 16 MHz 16 MIPS - - 32K Flash : 10,000 - Boot Boot - 1024 EEPROM : 100,000 - 2K SRAM - JTAG ( IEEE 1149.1 ) - JTAG - - JTAG Flash EEPROM - 8 / - 16 / - RTC - PWM - 8 10 ADC 8 TQFP 7 2 1x, 10x, 200x - - USART - / SPI - - - - RC - / - 6 : ADC Standby Standby I/O - 32 I/O - 40 PDIP , 44 TQFP , 44 MLF - ATmega32L2.7 - 5.5V - ATmega324.5 - 5.5V - ATmega32L0 - 8 MHz - ATmega320 - 16 MHz ATmega32L 1 MHz, 3V, 25C - : 1.1 mA - : 0.35 mA - : < 1 A
*
*
32KB Flash 8 ATmega32 ATmega32L
*
*
* * * *

2503F-AVR-12/03
Figure 1. ATmega32
PDIP
(XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP) PD6 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2)
TQFP/MLF
PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2
PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO)
AVR
2
ATmega32(L)
2503F-AVR-12/03
(INT1) (OC1B) (OC1A) (ICP) (OC2)
PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 (TCK) PC2 (TMS) PC3
ATmega32(L)
ATmega32 AVR RISC 8 CMOS ATmega32 1 MIPS/MHz Figure 2.
PA0 - PA7 VCC PC0 - PC7
PORTA DRIVERS/BUFFERS
PORTC DRIVERS/BUFFERS
GND
PORTA DIGITAL INTERFACE
PORTC DIGITAL INTERFACE
AVCC
MUX & ADC
AREF PROGRAM COUNTER
ADC INTERFACE
TWI
STACK POINTER
TIMERS/ COUNTERS
OSCILLATOR
PROGRAM FLASH
SRAM
INTERNAL OSCILLATOR XTAL1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS X
WATCHDOG TIMER
OSCILLATOR
XTAL2 MCU CTRL. & TIMING RESET
INSTRUCTION DECODER
Y Z
CONTROL LINES
ALU
INTERRUPT UNIT
INTERNAL CALIBRATED OSCILLATOR
AVR CPU
STATUS REGISTER
EEPROM
PROGRAMMING LOGIC
SPI
USART
+ -
COMP. INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
PB0 - PB7
PD0 - PD7
3
2503F-AVR-12/03
AVR 32 (ALU) CISC 10 ATmega32:32K Flash( RWW) 1024 EEPROM 2K SRAM I/O 32 32 JTAG / (T/C), / USART 8 10 (TQFP ) ADC SPI CPU USART A/D SRAM T/C SPI ADC CPU ADC I/O ADC Standby Standby Atmel ISP Flash ISP AVR Flash(Application Flash Memory) FlashFlash(Boot Flash Memory) RWW 8 RISC CPU Flash ATmega32 ATmega32 C /
VCC GND A(PA7..PA0) A A/D A 8 I/O A B(PB7..PB0) B 8 I/O B B P55 C(PC7..PC0) C 8 I/O C JTAG PC5(TDI)PC3(TMS) PC2(TCK) TAP TD0 C P58
4
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
D(PD7..PD0) D 8 I/O D D P60 RESET XTAL1 XTAL2 AVCC AREF P35 Table 15 ADC AVCCAA/D ADC VCC VCC A/D C C
5
2503F-AVR-12/03
AVR CPU

AVR CPU Figure 3. AVR
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
AVR Harvard CPU ( ) Flash 32 8 ALU ALU 6 3 16 16 X Y Z ALU ALU / 16 16 32 (Boot ) / SPM (PC) SRAM SRAM
6
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
SP I/O SRAM 5 AVR AVR I/O I/O 64 CPU SPI I/O 0x20 - 0x5F
ALU
AVR ALU 32 ALU ALU 3 /
7
2503F-AVR-12/03
ALU AVR SREG
Bit / 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* Bit 7 - I: I I I RETI I I SEI CLI * Bit 6 - T: BLD BST T BST T BLD T * Bit 5 - H: H BCD * Bit 4 - S: , S = N
V
S N 2 V * Bit 3 - V: 2 2 * Bit 2 - N: * Bit 1 - Z: * Bit 0 - C:
AVR RISC / * * * * 8 8 8 8 8 16 16 16
Figure 4 CPU 32
8
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 4. AVR CPU
7 R0 R1 R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X X Y Y Z Z $0D $0E $0F $10 $11 0 Addr. $00 $01 $02
Figure 4 32 SRAM X Y Z
9
2503F-AVR-12/03
XYZ
R26..R31 Figure 5 Figure 5. X Y Z
15 X 7 R27 ($1B) XH 0 7 R26 ($1A) XL 0 0
15 Y 7 R29 ($1D)
YH 0 7 R28 ($1C)
YL
0 0
15 Z 7 R31 ($1F)
ZH 0 7 R30 ($1E)
ZL 0
0

/ AVR SRAM 0x60 PUSH POP RET RETI AVRI/O8 AVR SPL SPH
Bit 15 SP15 SP7 7 / R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL
10
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
AVR CPU clkCPU Figure 6 Harvard 1 MIPS/MHz / / Figure 6.
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 7 ALU Figure 7. ALU
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
AVR I PC BLB02 BLB12 P240 " " P42 "" RESET INT0 - 0 (GICR) IVSEL Flash P42 "" BOOTRST Flash P228 " - (RWW, Read-While-Write) " I I RETI I
11
2503F-AVR-12/03
"1" "0" I AVR CLI CLI CLI EEPROM EEPROM
in cli r16, SREG ; ; EEPROM ; SREG (I ) ; SREG
sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16
C
char cSREG; cSREG = SREG; /* */ _CLI(); EECR |= (1< SEI
sei ; sleep ; ; : MCU
C
_SEI(); /* */ _SLEEP(); /* */ /* : MCU */
AVR 4 4 4 PC 3 MCU MCU 4
12
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
4 PC( ) SREG I
13
2503F-AVR-12/03
AVR ATmega32
ATmega32 AVR ATmega32 EEPROM
Flash ATmega32 32K Flash AVR 16 32 Flash 16K x 16
Flash (Boot) Flash10,000 ATmega32(PC)14 16K P228 " - (RWW, Read-While-Write)" P240 " " SPI JTAG Flash ( LPM ) P11 " " Figure 8.
$0000
Application Flash Section
Boot Flash Section $3FFF
14
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
SRAM
Figure 9 ATmega32 SRAM 2144 I/O SRAM 96 I/O 2048 SRAM 5 R26 R31 Y Z 63 X Y Z ATmega3232 64I/O 2048SRAM P8 " " Figure 9.
Register File R0 R1 R2 ... R29 R30 R31 I/O Registers $00 $01 $02 ... $3D $3E $3F Data Address Space $0000 $0001 $0002 ... $001D $001E $001F $0020 $0021 $0022 ... $005D $005E $005F Internal SRAM $0060 $0061 ... $085E $085F
15
2503F-AVR-12/03
Figure 10 SRAM clkCPU Figure 10. SRAM
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address Valid
Memory Access Instruction
Next Instruction
EEPROM
ATmega321024 EEPROM EEPROM 100,000 EEPROM P240 " " SPI JTAG EEPROM
EEPROM /
EEPROM I/O EEPROM Table 1 EEPROM / VCC / CPU P20 " EEPROM " EEPROM EEPROM EEPROM EEPROM CPU 4 EEPROM CPU 2
16
ATmega32(L)
2503F-AVR-12/03
Read
Write
ATmega32(L)
EEPROM EEARH EEARL
Bit
15 - EEAR7 7
14 - EEAR6 6 R R/W 0 X
13 - EEAR5 5 R R/W 0 X
12 - EEAR4 4 R R/W 0 X
11 - EEAR3 3 R R/W 0 X
10 - EEAR2 2 R R/W 0 X
9 EEAR9 EEAR1 1 R/W R/W 0 X
8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
/
R R/W 0 X
* Bits 15..10 - Res: * Bits 9..0 - EEAR9..0: EEPROM EEPROM- EEARHEEARL1024EEPROM EEPROM 0 1023 EEAR EEPROM EEPROM EEDR
Bit / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR
* Bits 7..0 - EEDR7.0: EEPROM EEPROM EEDR EEAR EEDR EEAR EEPROM EECR
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W X 0 EERE R/W 0 EECR
* Bits 7..4 - Res: * Bit 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * Bit 2 - EEMWE: EEPROM EEMWEEEWEEEPROM EEMWE"1" 4 EEWE EEPROM EEMWE "0" EEWE EEMWE 4 EEPROM EEWE
17
2503F-AVR-12/03
* Bit 1 - EEWE: EEPROM EEWE EEPROM EEPROM EEWE EEPROM EEMWE EEPROM ( 3 4 ) 1. EEWE 2. SPMCSR SPMEN 3. EEPROM EEAR( ) 4. EEPROM EEDR( ) 5. EECR EEMWE "1" EEWE 6. EEMWE 4 EEWE CPU Flash EEPROM EEPROM Flash (2) CPU Flash CPU Flash (2) P228 " - (RWW, Read-While-Write) " 5 6 EEPROM EEPROM EEPROM EEAR EEDR EEPROM I EEWE EEWE CPU * Bit 0 - EERE: EEPROM EEREEEPROM EEPROM EERE EEAR EEPROM EEPROM CPU 4 EEPROM EEWE EEPROM EEAR EEPROM Table 1 CPU EEPROM Table 1. EEPROM
EEPROM (CPU) Note: RC (1) 8448 1. 1 MHz CKSEL 8.5 ms
18
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
C EEPROM Boot Loader Boot Loader EEPROM SPM
EEPROM_write: ; sbic EECR,EEWE rjmp EEPROM_write ; (r18:r17) out out out sbi sbi ret EEARH, r18 EEARL, r17 EEDR,r16 EECR,EEMWE EECR,EEWE
; (r16) ; EEMWE ; EEWE
C
void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* */ while(EECR & (1<19
2503F-AVR-12/03
C EEPROM
EEPROM_read: ; sbic EECR,EEWE rjmp EEPROM_read ; (r18:r17) out out sbi in ret EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR
; EERE ;
C
unsigned char EEPROM_read(unsigned int uiAddress) { /* */ while(EECR & (1< EEPROM EEPROM
EEPROM EEPROM EEPROM CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD
I/O
ATmega32 I/O P283 " " ATmega32I/OI/O I/OIN OUT 32 I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC IN OUT 0x00 - 0x3F SRAM LD ST I/O 0x20
20
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
"0" I/O "1" AVR CBI SBI CBI SBI 0x00 0x1F I/O
21
2503F-AVR-12/03
Figure 11AVR P30 " " Figure 11 Figure 11.
Asynchronous Timer/Counter General I/O Modules ADC CPU Core RAM Flash and EEPROM
clkADC clkI/O clkASY clkCPU clkFLASH
AVR Clock Control Unit
Reset Logic
Watchdog Timer
Source Clock Clock Multiplexer
Watchdog Clock Watchdog Oscillator
Timer/Counter Oscillator
External RC Oscillator
External Clock
Crystal Oscillator
Low-frequency Crystal Oscillator
Calibrated RC Oscillator
CPU clkCPU I/O clkI/O
CPUAVR CPU I/O I/O / SPI USART I/O I/O USI clkI/O Flash Flash CPU / 32 kHz / ADC ADCCPUI/O ADC
Flash clkFLASH clkASY ADC clkADC
22
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ATmega32 Flash AVR Table 2. (1)
/ RC RC Note: 1. "1" "0" CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000
CPU CPU MCU WDT Table 3 P283 " " Table 3.
(VCC = 5.0V) 4.1 ms 65 ms (VCC = 3.0V) 4.3 ms 69 ms 4K (4,096) 64K (65,536)
CKSEL = "0001" SUT = "10" RC ISP
23
2503F-AVR-12/03
XTAL1 XTAL2 Figure 12 CKOPT CKOPT XTAL2 CKOPT CKOPT 8 MHz CKOPT 16 MHz C1 C2 Table 4 Figure 12.
C2 C1 XTAL2 XTAL1 GND
CKSEL3..1 Table 4 Table 4.
CKOPT 1 1 1 0 Note: CKSEL3..1 101(1) 110 111 101, 110, 111 (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 1.0 C1 C2 (pF) - 12 - 22 12 - 22 12 - 22
1.
24
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 5 CKSEL0 SUT1..0 Table 5.
258 CK(1) 258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK (VCC = 5.0V) 4.1 ms 65 ms - 4.1 ms 65 ms - 4.1 ms 65 ms
CKSEL0 0 0 0 0 1 1 1 1 Notes:
SUT1..0 00 01 10 11 00 01 10 11
BOD BOD
1. 2.
25
2503F-AVR-12/03
32.768 kHz CKSEL "1001" Figure 12 CKOPT XTAL1 XTAL2 36 pF SUT Table 6 Table 6.
SUT1..0 00 01 10 11 Note: 1K CK 1K CK
(1) (1)
(VCC = 5.0V) 4.1 ms 65 ms 65 ms
BOD
32K CK
1.
RC
Figure 13 RC f = 1/(3RC) C 22 pF CKOPT XTAL1 GND 36 pF R C RC Figure 13. RC
VCC NC
R
XTAL2 XTAL1
C GND
CKSEL3..0 Table 7
26
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 7. RC
CKSEL3..0 0101 0110 0111 1000 (MHz) 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0
SUT Table 8 Table 8. RC
SUT1..0 00 01 10 11 Note: 18 CK 18 CK 18 CK 6 CK(1) (VCC = 5.0V) - 4.1 ms 65 ms 4.1 ms BOD BOD
1.
RC
RC 1.0 2.0 4.0 8.0 MHz 5V 25C Table 9 CKSEL (CKOPT) OSCCAL RC 5V 25C 1.0 MHz 3% www.atmel.com/avr 1% P242 " " Table 9. RC
CKSEL3..0 0001(1) 0010 0011 0100 Note: 1. (MHz) 1.0 2.0 4.0 8.0
27
2503F-AVR-12/03
SUT Table 10 XTAL1 XTAL2 (NC) Table 10. RC
SUT1..0 00 01 10(1) 11 Note: 1. 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD
OSCCAL
Bit / 7 CAL7 R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL
* Bits 7..0 - CAL7..0: 1 MHz ( 0x00) OSCCAL RC Flash EEPROM OSCCAL OSCCAL 0xFF EEPROM Flash EEPROM Flash 10% 1.0 2.0 4.08.0 MHz Table 11 Table 11. RC .
OSCCAL $00 $7F $FF (%) 50 75 100 (%) 100 150 200
28
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
XTAL1 Figure 14 CKSEL"0000" CKOPT XTAL1 GND 36 pF Figure 14.
EXTERNAL CLOCK SIGNAL
SUT Table 12 Table 12.
SUT1..0 00 01 10 11 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD
MCU 2% MCU
/
/ (TOSC1 TOSC2) AVR 32.768 kHz TOSC1
29
2503F-AVR-12/03
MCU AVR MCUCR SE SLEEP ( ADC Standby Standby ) MCUCR SM2 SM1 SM0 Table 13 MCU 4 MCU SLEEP SRAM MCU P22 Figure 11 ATmega32
MCU MCUCR
Bit / 7 SE R/W 0 6 SM2 R/W 0 5 SM1 R/W 0 4 SM0 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 7 - SE: MCU SLEEP SE SLEEP SEMCU SE * Bits 6...4 - SM2..0: 2 1 0 Table 13 Table 13.
SM2 0 0 0 0 1 1 1 1 Note: SM1 0 0 1 1 0 0 1 1 SM0 0 1 0 1 0 1 0 1 ADC Standby(1) Standby(1)
1. Standby Standby
30
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
SM2..0 000 SLEEP MCU CPU SPI USART ADC / clkCPU clkFLASH USART MCU MCU ACSR ACD ADC
ADC
SM2..0 001 SLEEP MCU CPU ADC / 2 clkI/O clkCPU clkFLASH ADC ADC AD ADC BOD / 2 SPM/EEPROM INT0 INT1 INT2 MCU ADC
SM2..0 010 SLEEP MCU BOD INT0 INT1 INT2 MCU MCU P64 " " CKSEL P23 " "
SM2..0 011 SLEEP MCU / 2 ASSR AS2 / 2 / 2 MCU TIMSK SREG I AS2 0 MCU clkASY
Standby
SM2..0 110 SLEEP MCU Standby 6
31
2503F-AVR-12/03
Standby
SM2..0 111 SLEEP MCU Standby 6 Table 14.
X X X(2) X(2)
SPM / EEP ROM
clkFLASH
clkADC
clkCPU
clkASY
ADC Standby (1) Standby (1) Notes:
X X X X X
TWI
INT2 INT1 INT0
clkIO
2
X X
A D C
I/O
X
X X
X X
X X(3) X(3)
X X
X X
X
X
(2)
X X
(2)
X
(3)
X(2)
X(3) X(2) X(3)
X(2)
X
X
X(2)
1. 2. ASSR AS2 3. INT2 INT1 INT0
AVR ADC ADC P187 " "
32
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ADC P184 " " BOD BODEN BOD P37 " " BOD BOD ADC P39 " " P39 " " I/O clkI/O ADC clkADC P51 " " VCC/2 OCDEN * * * OCDEN JTAGEN MCUCSR JTD
BOD
JTAG
JTAG JTAG TAP TDO TDO TDI TDO MCUCSR JTD JTAG JTAG
33
2503F-AVR-12/03
AVR I/O JMP Boot -- -- Figure 15 Table 15 I/O MCU SUT CKSEL P23 " " ATmega32 5 * * * * * VPOT MCU RESET MCU VBOT MCU JTAG AVR 1 MCU P210 "IEEE 1149.1 (JTAG) "
Figure 15.
DATA BUS
MCU Control and Status Register (MCUCSR)
PORF BORF EXTRF WDRF JTRF
Power-on Reset Circuit
Pull-up Resistor
SPIKE FILTER
Reset Circuit
COUNTER RESET
JTAG Reset Register
Watchdog Timer
Watchdog Oscillator
Clock Generator
CK
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
34
ATmega32(L)
2503F-AVR-12/03
INTERNAL RESET
BODEN BODLEVEL
Brown-out Reset Circuit
ATmega32(L)
Table 15.
1.4 1.3 0.1 VCC
(2)
( ) ( )(1) RESET RESET
2.3 2.3 0.9VCC 1.5
V V V s V s s mV
VPOT
VRST tRST VBOT tBOD VHYST Notes:
BODLEVEL = 1 BODLEVEL = 0
2.5 3.7
2.7 4.0 2 2 50
3.2 4.2

BODLEVEL = 1 BODLEVEL = 0
1. VPOT 2. VBOT VCC = VBOT VCC ATmega32L BODLEVEL=1 ATmega32 BODLEVEL=0 BODLEVEL=1 ATmega32
35
2503F-AVR-12/03
(POR) Table 15 VCC POR POR POR CC V VCC RESET Figure 16. MCU RESET VCC.
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure 17. MCU RESET
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
36
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
RESET ( Table 15) VRST( ) tTOUT MCU Figure 18.
CC
ATmega32 BOD(Brown-out Detection) V CC BODLEVEL 2.7V (BODLEVEL )4.0V (BODLEVEL )BOD VBOT+ = VBOT + VHYST/2 VBOT- = VBOT - VHYST/2 BOD BODEN BOD(BODEN) VCC (VBOT- Figure 19) BOD VCC (VBOT+ Figure 19) tTOUT MCU VCC Table 15 tBOD BOD Figure 19.
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
37
2503F-AVR-12/03
1 CK tTOUT P39 Figure 20.
CC
CK
MCU MCUCSR
MCU MCU
Bit / 7 JTD R/W 0 6 ISC2 R/W 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUCSR
* Bit 4 - JTRF: JTAG JTAG AVR_RESET JTAG MCU JTRF "0" * Bit 3 - WDRF: "0" * Bit 2 - BORF: "0" * Bit 1 - EXTRF: "0" * Bit 0 - PORF: "0"
38
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ATmega32 ADC ADC 2.56V Table 16 1. BOD ( BODEN ) 2. (ACSR ACBG ) 3. ADC BOD ACBG ADC Table 16.
VBG tBG IBG 1.15 1.23 40 10 1.35 70 V s A
1 Mhz VCC = 5V VCC P40 Table 17 WDR 8 ATmega32 P38 Figure 21.
WATCHDOG OSCILLATOR
WDTCR
Bit /
7 - R 0
6 - R 0
5 - R 0
4 WDTOE R/W 0
3 WDE R/W 0
2 WDP2 R/W 0
1 WDP1 R/W 0
0 WDP0 R/W 0 WDTCR
39
2503F-AVR-12/03
* Bits 7..5 - Res: * Bit 4 - WDTOE: WDE WDTOE 4 WDE * Bit 3 - WDE: WDE "1" WDTOE "1" WDE 1. WDTOE WDE "1" WDE "1" 2. 4 WDE "0" * Bits 2..0 - WDP2, WDP1, WDP0: 2, 1 0 WDP2 WDP1 WDP0 Table 18 Table 17.
WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 WDT 16K (16,384) 32K (32,768) 64K (65,536) 128K (131,072) 256K (262,144) 512K (524,288) 1,024K (1,048,576) 2,048K (2,097,152) VCC = 3.0V 17.1 ms 34.3 ms 68.5 ms 0.14 s 0.27 s 0.55 s 1.1 s 2.2 s VCC = 5.0V 16.3 ms 32.5 ms 65 ms 0.13 s 0.26 s 0.52 s 1.0 s 2.1 s
C WDT ( )
40
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
WDT_off: ; WDTOE WDE ldi out ldi out ret r16, (1<; WDT
C
void WDT_off(void) { /* WDTOE WDE */ WDTCR = (1<41
2503F-AVR-12/03
ATmega32
ATmega32 AVR P11 ""
Table 18.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Notes: (2) $000
(1)
RESET INT0 INT1 INT2 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMP TIMER0 OVF SPI, STC USART, RXC USART, UDRE USART, TXC ADC EE_RDY ANA_COMP TWI SPM_RDY
JTAG AVR 0 1 2 / 2 / 2 / 1 / 1 A / 1 B / 1 / 0 / 0 SPI USART Rx USART USART Tx ADC EEPROM
$002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 $022 $024 $026 $028
1. BOOTRST MCU Boot Loader P228 " - (RWW, Read-While-Write) " 2. GICRIVSEL Boot Boot
Table 19BOOTRST/IVSEL Boot
42
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 19. (1)
BOOTRST 1 1 0 0 Note: IVSEL 0 1 0 1 $0000 $0000 Boot Boot $0002 Boot + $0002 $0002 Boot + $0002
1. Boot P237 Table 100 BOOTRST "0" "1"
; ; IRQ0 ; IRQ1 ; IRQ2 ; Timer2 ; Timer2 ; Timer1 ; Timer1 A ; Timer1 B ; Timer1 ; Timer0 ; Timer0 ; SPI ; USART RX ; UDR ; USART TX ; ADC ; EEPROM ; ; ; SPM
ATmega32
$000 $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 $022 $024 $026 $028 ; $02A $02B $02C $02D $02E $02F ... ... RESET: ldi out ldi out sei ... xxx jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET EXT_INT0 EXT_INT1 EXT_INT2 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMP TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY
r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; ; RAM
43
2503F-AVR-12/03
BOOTRST Boot 4K GICR IVSEL
$000 $001 $002 $003 $004 $005 ; .org $3802 $3802 $3804 ... $3828 .... jmp jmp .. jmp SPM_RDY EXT_INT0 EXT_INT1 ; IRQ0 ; IRQ1 ; ; SPM RESET: ldi out ldi out sei xxx r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; ; RAM
BOOTRST Boot 4K
.org $002 $002 $004 ... $028 ; .org $3800 $3800 RESET: $3801 $3802 $3803 $3804 $3805 ldi out ldi out sei xxx r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; ; RAM .... jmp jmp .. jmp SPM_RDY EXT_INT0 EXT_INT1 ; IRQ0 ; IRQ1 ; ; SPM
BOOTRST Boot 4K GICR IVSEL
.org $3800 $3800 $3802 $3804 ... $3828 ; $382A $382B $382C $382D $382E $382F RESET: ldi out ldi out sei xxx r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; ; RAM .... ; Reset ; IRQ0 ; IRQ1 ; SPM_RDY ; SPM
jmp jmp jmp .. jmp
RESET EXT_INT0 EXT_INT1
44
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Boot GICR
Bit / 7 INT1 R/W 0 6 INT0 R/W 0 5 INT2 R/W 0 4 - R 0 3 - R 0 2 - R 0 1 IVSEL R/W 0 0 IVCE R/W 0 GICR
* Bit 1 - IVSEL: IVSEL "0" Flash IVSEL "1" Boot Boot BOOTSZ P228 " - (RWW, Read-While-Write) " IVSEL 1. IVCE 2. 4 IVSEL IVCE "0" IVCE IVSEL IVSEL IVCE 4 I
Note: Boot BootBLB02 Boot BLB12 Boot Boot P228 " - (RWW, Read-While-Write) "
45
2503F-AVR-12/03
* Bit 0 - IVCE: IVSEL IVCE IVCE IVSEL 4 IVCE IVCE
Move_interrupts: ; ldi out ldi out ret r16, (1<; boot Flash
C
void Move_interrupts(void) { /* */ GICR = (1<46
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
I/O
I/O AVR I/O - - SBI CBI ( / ) ( / ) LED VCC Figure 22 P269 " " Figure 22. I/O
Rpu
Pxn
Logic Cpin
See Figure 23 "General Digital I/O" for Details
"x" "n" PORTB3 B 3 PORTxn I/O P61 "I/O " I/O - PORTx - DDRx - PINx / PINx "1" "0" "1" SFIOR PUD I/O P47 " I/O " P52 " " I/O
I/O
I/O Figure 23 I/O
47
2503F-AVR-12/03
Figure 23. I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx
RDx
Pxn
Q
D
PORTxn Q CLR
WPx RESET SLEEP RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WPx: RRx: RPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN
Note:
1. WPx, WDx, RRx, RPx RDx clkI/O, SLEEP PUD
: DDxn PORTxn PINxn P61 "I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0") ( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) SFIOR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11)
48
ATmega32(L)
2503F-AVR-12/03
DATA BUS
ATmega32(L)
Table 20 Table 20.
DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD (in SFIOR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( )
DDxn PINxn Figure 23 PINxn Figure 24 tpd,max tpd,min Figure 24.
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 tpd, max tpd, min 0xFF XXX XXX in r17, PINx
SYNC LATCH PINxn tpd,max tpd,min 1/2 ~ 11/2 Figure 25 out in nop out SYNC LATCH tpd
49
2503F-AVR-12/03
Figure 25.
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 tpd 0xFF out PORTx, r16 nop 0xFF
in r17, PINx
50
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
B 0 1 2 3 4 7 6 7 nop (1)
... ; ; ldi ldi out out nop ; in ... r16,PINB r16,(1<; nop
C (1)
unsigned char i; ... /* */ /* */ PORTB = (1<Note:
1. 0 1 6 7 2 3 0 1
Figure 23 ( ) SLEEP MCU Standby VCC/2 SLEEP SLEEP SLEEP P52 " " ("1") " " "1" "0" "0" "1"
( ) 51
2503F-AVR-12/03
VCC GND
I/O Figure 26 Figure 23 AVR Figure 26. (1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D PORTxn
DIEOExn DIEOVxn
1 0
Q CLR
WPx RESET RRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL
PUD: WDx: RDx: RRx: WPx: RPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WPx, WDx, RRx, RPxRDx I/O, SLEEP clk PUD
Table 21 Figure 26
52
ATmega32(L)
2503F-AVR-12/03
DATA BUS
ATmega32(L)
Table 21.
PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE DDxnPORTxn PUD PUOV / / DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn DIEOV DIEOE MCU ( ) DIEOE DIEOV / / MCU ( ) /
PUOV
DDOE DDOV PVOE
PVOV DIEOE
DIEOV
DI
AIO
/

53
2503F-AVR-12/03
I/O SFIOR
Bit / 7 ADTS2 R/W 0 6 ADTS1 R/W 0 5 ADTS0 R/W 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 2 - PUD: DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P48 " " A A ADC Table 22 A Table 22. A
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 ADC7 (ADC 7) ADC6 (ADC 6) ADC5 (ADC 5) ADC4 (ADC 4) ADC3 (ADC 3) ADC2 (ADC 2) ADC1 (ADC 1) ADC0 (ADC 0)
Table 23 Table 24 A P52 Figure 26 Table 23. PA7..PA4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PA7/ADC7 0 0 0 0 0 0 0 0 - ADC7 PA6/ADC6 0 0 0 0 0 0 0 0 - ADC6 PA5/ADC5 0 0 0 0 0 0 0 0 - ADC5 PA4/ADC4 0 0 0 0 0 0 0 0 - ADC4
54
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 24. PA3..PA0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PA3/ADC3 0 0 0 0 0 0 0 0 - ADC3 PA2/ADC2 0 0 0 0 0 0 0 0 - ADC2 PA1/ADC1 0 0 0 0 0 0 0 0 - ADC1 PA0/ADC0 0 0 0 0 0 0 0 0 - ADC0
B
B Table 25 Table 25. B
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 SCK (SPI ) MISO (SPI / ) MOSI (SPI / ) SS (SPI ) AIN1 ( ) OC0 (T/C0 ) AIN0 ( ) INT2 ( 2 ) T1 (T/C1 ) T0 (T/C0 ) XCK (USART / )
* SCK - B, Bit 7 SCKSPI DDB7 DDB7 PORTB7 * MISO - B, Bit 6 MISOSPI DDB6 DDB6 PORTB6
55
2503F-AVR-12/03
* MOSI - B, Bit 5 MOSI SPI DDB5 DDB5 PORTB5 * SS - B, Bit 4 SS DDB4 SPI DDB4 PORTB4 * AIN1/OC0 - B, Bit 3 AIN1 OC0PB3 T/C0 PB3 ( DDB3 1) PWM OC0 * AIN0/INT2 - B, Bit 2 AIN0 INT2 2 PB2 MCU * T1 - B, Bit 1 T1 T/C1 * T0/XCK - B, Bit 0 T0 T/C0 XCK USART (DDB0) (DDB0 ) (DDB0 ) USART XCK Table 26 Table 27 B P52 Figure 26 SPI MSTR INPUT SPI SLAVE OUTPUT MISO MOSISPI MSTR OUTPUT SPI SLAVE INPUT
56
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 26. PB7..PB4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB7/SCK SPE * MSTR PORTB7 * PUD SPE * MSTR 0 SPE * MSTR SCK 0 0 SCK - PB6/MISO SPE * MSTR PORTB6 * PUD SPE * MSTR 0 SPE * MSTR SPI 0 0 SPI - PB5/MOSI SPE * MSTR PORTB5 * PUD SPE * MSTR 0 SPE * MSTR SPI 0 0 SPI - PB4/SS SPE * MSTR PORTB4 * PUD SPE * MSTR 0 0 0 0 0 SPI SS -
Table 27. PB3..PB0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB3/OC0/AIN1 0 0 0 0 OC0 OC0 0 0 - AIN1 PB2/INT2/AIN0 0 0 0 0 0 0 INT2 1 INT2 AIN0 PB1/T1 0 0 0 0 0 0 0 0 T1 - PB0/T0/XCK 0 0 0 0 UMSEL XCK 0 0 XCK /T0 -
57
2503F-AVR-12/03
C
C Table 28 JTAG PC5(TDI) PC3(TMS) PC2(TCK) Table 28. C
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 TOSC2 ( 2) TOSC1 ( 1) TDI (JTAG ) TDO (JTAG ) TMS (JTAG ) TCK (JTAG ) SDA ( / ) SCL ( )
* TOSC2 - C, Bit 7 TOSC2 2 ASSR AS2 1 T/C2 PC7 I/O * TOSC1 - C, Bit 6 TOSC1 1 ASSR AS2 1 T/C2 PC6 I/O * TDI - C, Bit 5 TDI JTAG () JTAG I/O * TDO - C, Bit 4 TDO JTAG ( ) JTAG I/O TD0 TAP * TMS - C, Bit 3 TMSJTAG TAP JTAG I/O * TCK - C, Bit 2 TCK JTAG JTAG JTAG I/O * SDA - C, Bit 1 SDA TWCR TWEN 1 PC1 I/O 58
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
50 ns PORTC1 * SCL - C, Bit 0 SCL TWCR TWEN 1 PC0 I/O 50 ns PORTC0 Table 29 Table 30 C P52 Figure 26 Table 29. PC7..PC4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PC7/TOSC2 AS2 0 AS2 0 0 0 AS2 0 - T/C2 OSC PC6/TOSC1 AS2 0 AS2 0 0 0 AS2 0 - T/C2 OSC PC5/TDI JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TDI PC4/TDO JTAGEN 0 JTAGEN SHIFT_IR + SHIFT_DR JTAGEN TDO JTAGEN 0 - -
Table 30. PC3..PC0 (1)
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PC3/TMS JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TMS PC2/TCK JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TCK PC1/SDA TWEN PORTC1 * PUD TWEN SDA_OUT TWEN 0 0 0 - SDA PC0/SCL TWEN PORTC0 * PUD TWEN SCL_OUT TWEN 0 0 0 - SCL
1. PC0 PC1 AIO TWI
59
2503F-AVR-12/03
D
D Table 31 Table 31. D
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 OC2 (T/C2 ) ICP1 (T/C1 ) OC1A (T/C1 A ) OC1B (T/C1 B ) INT1 ( 1 ) INT0 ( 0 ) TXD (USART ) RXD (USART )
* OC2 - D, Bit 7 OC2T/C2 PD7 T/C2 (DDD7 1) PWM OC2 * ICP - D, Bit 6 ICP1 - PD6 T/C1 * OC1A - D, Bit 5 OC1A A PD5 T/C1 A (DDD5 1) PWM OC1A * OC1B - D, Bit 4 OC1A A PD5 T/C1 A (DDD5 1) PWM OC1A * INT1 - D, Bit 3 INT1 1 PD3 MCU * INT0 - D, Bit 2 INT0 0 PD2 MCU * TXD - D, Bit 1 TXDUSART USART DDD1 * RXD - D, Bit 0 RXDUSART USART DDD0 PORTD0
60
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 32 Table 33 D P52 Figure 26 Table 32. PD7..PD4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PD7/OC2 0 0 0 0 OC2 OC2 0 0 - - PD6/ICP 0 0 0 0 0 0 0 0 ICP - PD5/OC1A 0 0 0 0 OC1A OC1A 0 0 - - PD4/OC1B 0 0 0 0 OC1B OC1B 0 0 - -
Table 33. PD3..PD0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PD3/INT1 0 0 0 0 0 0 INT1 1 INT1 - PD2/INT0 0 0 0 0 0 0 INT0 1 INT0 - PD1/TXD TXEN 0 TXEN 1 TXEN TXD 0 0 - - PD0/RXD RXEN PORTD0 * PUD RXEN 0 0 0 0 0 RXD -
I/O
A PORTA
Bit / 7
PORTA7
6
PORTA6
5
PORTA5
4
PORTA4
3
PORTA3
2
PORTA2
1
PORTA1
0
PORTA0 PORTA
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
A DDRA
Bit / 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA
61
2503F-AVR-12/03
A PINA
Bit / 7 PINA7 R N/A 6 PINA6 R N/A 5 PINA5 R N/A 4 PINA4 R N/A 3 PINA3 R N/A 2 PINA2 R N/A 1 PINA1 R N/A 0 PINA0 R N/A PINA
B PORTB
Bit / 7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
B DDRB
Bit / 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB
B PINB
Bit / 7 PINB7 R N/A 6 PINB6 R N/A 5 PINB5 R N/A 4 PINB4 R N/A 3 PINB3 R N/A 2 PINB2 R N/A 1 PINB1 R N/A 0 PINB0 R N/A PINB
C PORTC
Bit / 7
PORTC7
6
PORTC6
5
PORTC5
4
PORTC4
3
PORTC3
2
PORTC2
1
PORTC1
0
PORTC0 PORTC
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
C DDRC
Bit / 7 DDC7 R/W 0 6 DDC6 R/W 0 5 DDC5 R/W 0 4 DDC4 R/W 0 3 DDC3 R/W 0 2 DDC2 R/W 0 1 DDC1 R/W 0 0 DDC0 R/W 0 DDRC
C PINC
Bit / 7 PINC7 R N/A 6 PINC6 R N/A 5 PINC5 R N/A 4 PINC4 R N/A 3 PINC3 R N/A 2 PINC2 R N/A 1 PINC1 R N/A 0 PINC0 R N/A PINC
D PORTD
Bit / 7
PORTD7
6
PORTD6
5
PORTD5
4
PORTD4
3
PORTD3
2
PORTD2
1
PORTD1
0
PORTD0 PORTD
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
D DDRD
Bit 7 DDD7 6 DDD6 5 DDD5 4 DDD4 3 DDD3 2 DDD2 1 DDD1 0 DDD0 DDRD
62
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
/ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
D PIND
Bit / 7 PIND7 R N/A 6 PIND6 R N/A 5 PIND5 R N/A 4 PIND4 R N/A 3 PIND3 R N/A 2 PIND2 R N/A 1 PIND1 R N/A 0 PIND0 R N/A PIND
63
2503F-AVR-12/03
INT0 INT1 INT2 INT0..2 MCU MCUCR MCU MCUCSR (INT2 ) ( INT0/INT1) INT0 INT1 I/O P22 " " INT0/INT1 INT2 ( ) I/O MCU MCU 5.0V 25C 1 s P269 " " MCU SUT P22 " " MCU MCU
MCU MCUCR
MCU MCU
Bit / 7 SE R/W 0 6 SM2 R/W 0 5 SM1 R/W 0 4 SM0 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 3, 2 - ISC11, ISC10: 1 Bit1 Bit 0 SREG I 1 INT1 Table 34 MCU INT1 Table 34. 1
ISC11 0 0 1 1 ISC10 0 1 0 1 INT1 INT1 INT1 INT1
* Bit 1, 0 - ISC01, ISC00: 0 Bit 1 Bit 0 SREG I Table 35 0 INT0 MCU INT0
64
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 35. 0
ISC01 0 0 1 1 ISC00 0 1 0 1 INT0 INT0 INT0 INT0
MCU MCUCSR
Bit /
7 JTD R/W 0
6 ISC2 R/W 0
5 - R 0
4 JTRF R/W
3 WDRF R/W
2 BORF R/W
1 EXTRF R/W
0 PORF R/W MCUCSR
* Bit 6 - ISC2: 2 SREG I GICR 2 INT2 ISC2 0 INT2 ISC2 1 INT2 INT2 INT2 Table 36 ISC2 GICR INT2 ISC2 GIFR INTF2 '1' Table 36. ( )
tINT ( ) 50 ns
GICR
Bit / 7 INT1 R/W 0 6 INT0 R/W 0 5 INT2 R/W 0 4 - R 0 3 - R 0 2 - R 0 1 IVSEL R/W 0 0 IVCE R/W 0 GICR
* Bit 7 - INT1: 1 INT1 '1' SREG I MCU- MCUCSR1 1/0 (ISC11ISC10) INT1 INT1 * Bit 6 - INT0: 0 INT0 '1' SREG I MCU- MCUCSR0 1/0 (ISC01ISC00) INT0 INT0
65
2503F-AVR-12/03
* Bit 5 - INT2: 2 INT2 '1' SREG I MCU- MCUCSR2 1/0 (ISC2ISC2) INT2 INT2 GIFR
Bit / 7 INTF1 R/W 0 6 INTF0 R/W 0 5 INTF2 R/W 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR
* Bit 7 - INTF1: 1 INT1 INTF1 SREG I GICR INT1 "1" MCU "1" * Bit 6 - INTF0: 0 INT0 INTF0 SREG I GICR INT0 "1" MCU "1" INT0 * Bit 5 - INTF2: 2 INT2 INTF2 SREG I GICR INT2 "1" MCU "1" INT2 INTF2 P51 " "
66
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
PWM 8 / 0
T/C0 8 / * * ( ) * PWM * * * 10 * (TOV0 OCF0) Figure 27 8 / P2 "ATmega32 " CPU I/O I/O P76 "8 / " Figure 27. 8 T/C
TCCRn
count clear direction Control Logic Clock Select Edge Detector BOTTOM TOP
TOVn (Int.Req.) clk Tn
Tn
DATABUS
( From Prescaler ) Timer/Counter TCNTn
=0
= 0xFF
OCn (Int.Req.)
=
Waveform Generation
OCn
OCRn
T/C(TCNT0) (OCR0) 8 ( Int.Req. ) TIFR TIMSK TIFR TIMSK T/C T0 ( )T/C T/C clkT0 OCR0 T/C PWM OC0 P68 " " OCF0
"n" T/C 0 TCNT0 T/C0
67
2503F-AVR-12/03
Table 37 Table 37. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR0
T/C
T/C T/C TCCR0 CS02:0 P79 "T/C0 T/C1 " 8 T/C Figure 28 Figure 28.
DATA BUS
TOVn (Int. Req.)
Clock Select count TCNTn clear direction ( From Prescaler ) BOTTOM TOP Control Logic clkTn Edge Detector Tn
( ) count direction clear clkTn top bottom TCNT0 1 1 TCNT0 ( ) T/C clkT0 TCNT0 TCNT0 (0)
clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( ) T/C (TCCR0) WGM01 WGM00 OC0 P70 " " T/CTOV0WGM01:0 TOV0CPU
8TCNT0OCR0 TCNT0OCR0 OCF0 OCIE0 = 1 SREG I CPU OCF0 "1" WGM01:0
68
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
COM01:0 max bottom (P70 " " ) Figure 29 Figure 29.
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top bottom FOCn
Waveform Generator
OCn
WGMn1:0
COMn1:0
PWM OCR0 OCR0 top bottom PWM OCR0 CPU OCR0 CPU OCR0 PWM FOC0 "1" OCF0 / OC0 (COM01:0 OC0A "0"-"1" ) CPU TCNT0 OCR0 TCNT0 TCNT0 TCNT0 T/C TCNT0 OCR0 TCNT0 BOTTOM OC0 OC0 FOC0 OC0 COM01:0 COM01:0
TCNT0
69
2503F-AVR-12/03
COM01:0 COM01:0 (OC0) COM01:0 OC0 Figure 30 COM01:0 I/O I/O I/O COM01:0 I/O (DDR PORT) OC0 OC0 OC0 OC0 Figure 30.
COMn1 COMn0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCn D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM01:0 I/O OC0 DDR OC0 DDR_OC0 OC0 COM01:0 P76 "8 / " COM01:0 CTC PWM COM01:0 = 0 OC0 PWM P76 Table 39 PWM P77 Table 40 PWM P77 Table 41 COM01:0 PWM FOC0
- T/C - (WGM01:0) (COM01:0) COM01:0 PWM PWM COM01:0 (P70 " " ) P74 "T/C " Figure 34Figure 35Figure 36 Figure 37
(WGM01:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV0 TOV0 9 TOV0
70
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
CPU CTC( ) CTC (WGM01:0 = 2) OCR0 TCNT0 OCR0 OCR0 TOP CTC Figure 31 TCNT0TCNT0OCR0 TCNT0 Figure 31. CTC
OCn Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMn1:0 = 1)
OCF0 TOP TOP CTC TOP BOTTOM OCR0 TCNT0 0xFF 0x00 OCF0 CTC OC0 COM01:0 = 1 OC0 fOC0 = fclk_I/O/2 (OCR0 = 0x00) f clk_I/O f OCn = -----------------------------------------------2 N ( 1 + OCRn ) N (1 8 64 256 1024) TOV0 MAX 0x00 PWM PWM (WGM01:0 = 3) PWM PWM PWM BOTTOMMAX BOTTOM OC0 TCNT0 OCR0 BOTTOM OC0 PWM PWM PWM DAC ( ) PWM MAX Figure 32 TCNT0 71
2503F-AVR-12/03
PWM PWM TCNT0 OCR0 TCNT0 Figure 32. PWM
OCRn Interrupt Flag Set
OCRn Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
4
5
6
7
MAX T/C TOV0 PWM OC0 PWM COM01:0 2 PWM 3 PWM ( P77 Table 40 ) OC0 PWM OC0 OCR0 TCNT0 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnPWM = -----------------N 256 N (1 8 64 256 1024) OCR0 PWM OCR0 BOTTOM MAX+1 OCR0 MAX COM01:0 OC0 (COM01:0 = 1) 50% OCR0 0 fOC0 = fclk_I/O/2 CTC OC0 PWM PWM PWM (WGM01:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT0 OCR0 OC0 BOTTOM TCNT0 OCR0 OC0 PWM PWM 8 MAX TCNT0 MAX Figure 33 TCNT0 PWM PWM TCNT0 OCR0 TCNT0 72
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 33. PWM
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV0 PWM OC0 PWM COM01:0 2 PWM COM01:0 3 PWM ( P77 Table 41 ) OC0 OCR0 TCNT0 OC0 PWM PWM f clk_I/O f OCnPCPWM = -----------------N 510 N (1 8 64 256 1024) OCR0 PWM PWM OCR0 BOTTOM OCR0 MAX PWM Figure 33 2 OCn BOTTOM * Figure 33 OCR0A MAX OCR0A MAX OCn BOTTOM T/C MAX OCn OCR0A OCn
*
T/C
T/C clkT0 Figure 34 T/C PWM MAX
73
2503F-AVR-12/03
Figure 34. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 35 Figure 35. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 36 ( CTC )OCF0 Figure 36. T/C OCF0 fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
74
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 37 CTC OCF0 TCNT0 Figure 37. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
75
2503F-AVR-12/03
8 /
T/C TCCR0
Bit / 7 FOC0 W 0 6 WGM00 R/W 0 5 COM01 R/W 0 4 COM00 R/W 0 3 WGM01 R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0
* Bit 7 - FOC0: FOC0 WGM00 PWM PWM TCCR0 1 OC0 COM01:0 FOC0 COM01:0 FOC0 OCR0TOPCTC FOC0 0 * Bit 6, 3 - WGM01:0: TOP T/C (CTC) PWM Table 38 P70 " " Table 38. (1)
0 1 2 3 Note: WGM01 (CTC0) 0 0 1 1 WGM00 (PWM0) 0 1 0 1 T/C PWM CTC PWM TOP 0xFF 0xFF OCR0 0xFF OCR0 TOP TOP TOV0 MAX BOTTOM MAX MAX
1. CTC0 PWM0 WGM01:0
* Bit 5:4 - COM01:0: OC0 COM01:0 OC0 1 OC0 COM01:0 WGM01:0 Table 39 WGM01:0 CTC COM01:0 . Table 39. PWM
COM01 0 0 1 1 COM00 0 1 0 1 OC0 OC0 OC0 OC0
76
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 40 WGM01:0 PWM COM01:0 Table 40. PWM (1)
COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0 OC0A TOP OC0 OC0A TOP OC0
1. OCR0 TOP COM01 TOP OC0 P71 " PWM "
Table 41 WGM01:0 PWM COM01:0 Table 41. PWM (1)
COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0 OC0 OC0 OC0 OC0
1. OCR0 TOP COM01 TOP OC0 P72 " PWM "
* Bit 2:0 - CS02:0: T/C Table 42.
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T0 T0
T/C0 T0 T/C TCNT0
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0 TCNT0[7:0]
77
2503F-AVR-12/03
T/C 8 TCNT0 TCNT0 TCNT0 OCR0 OCR0
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0 R/W 0 OCR0[7:0]
8 TCNT0 OC0 T/C TIMSK
Bit / 7 OCIE2 R/W 0 6 TOIE2 R/W 0 5 TICIE1 R/W 0 4 OCIE1A R/W 0 3 OCIE1B R/W 0 2 TOIE1 R/W 0 1 OCIE0 R/W 0 0 TOIE0 R/W 0 TIMSK
* Bit 1 - OCIE0: T/C0 OCIE0 I "1" T/C0 T/C0 TIFR OCF0 * Bit 0 - TOIE0: T/C0 TOIE0 I "1" T/C0 T/C0 TIFR TOV0 T/C TIFR
Bit / 7 OCF2 R/W 0 6 TOV2 R/W 0 5 ICF1 R/W 0 4 OCF1A R/W 0 3 OCF1B R/W 0 2 TOV1 R/W 0 1 OCF0 R/W 0 0 TOV0 R/W 0 TIFR
* Bit 1 - OCF0: 0 T/C0 OCR0( 0) OCF0 1 SREG I OCIE0(T/C0 ) OCF0 * Bit 0 - TOV0: T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0 PWM T/C0 0x00 TOV0
78
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
T/C0 T/C1
T/C1 T/C0 T/C1 T/C0 CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C1 T/C0 T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T/C T/C T1/T0 T/C clkT1/clkT0 T1/T0 ( ) Figure 38 T1/T0 clkI/O CSn2:0 = 7 clkT1 CSn2:0 = 6 clkT0 Figure 38. T1/T0
Tn
D LE
Q
D
Q
D
Q
Tn_sync (To Clock Select Logic)
clk I/O
Synchronization Edge Detector
T1/T0 2.5 3.5 T1/T0 T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5
79
2503F-AVR-12/03
Figure 39. T/C0 T/C1 (1)
clk I/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. (T1/T0) Figure 38
IO SFIOR
Bit / 7 ADTS2 R/W 0 6 ADTS1 R/W 0 5 ADTS0 R/W 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 0 - PSR10: T/C1 T/C0 T/C1 T/C0 T/C1 T/C0 0
80
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
16 / 1
16 T/C ( ) * 16 ( 16 PWM) * 2 * * * * ( ) * PWM * PWM * * * 4 (TOV1OCF1A OCF1B ICF1) "n" T/C "x" TCNT1 T/C1 16 T/C Figure 40 P2 Figure 1 CPU I/O I/O I/O I/O I/O P100 "16 / " Figure 40. 16 T/C (1)
Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Values
Waveform Generation
OCnA
OCnB (Int.Req.) Waveform Generation OCnB
DATABUS
=
OCRnB ICFn (Int.Req.) Edge Detector
( From Analog Comparator Ouput )
ICRn
Noise Canceler ICPn
TCCRnA
TCCRnB
Note:
1. P2 Figure 1 P55 Table 25 P60 Table 31 T/C1
81
2503F-AVR-12/03
/ TCNT1 OCR1A/B ICR1 16 16 P84 " 16 " T/C TCCR1A/B 8 CPU ( Int.Req.) TIFR1 TIMSK1 TIFR1 TIMSK1 T/CT1 T/C( ) T/C clkT1 OCR1A/B T/C PWM OC1A/B P89 " " OCF1A/B ICP1 ( P184 " " ) ( ) T/C ( ) TOP T/C OCR1A ICR1 PWM OCR1A TOP OCR1A PWM OCR1A TOP TOP ICR1 OCR1A PWM
Table 43.
BOTTOM MAX TOP 0x0000 BOTTOM 0xFFFF ( 65535) MAX TOP TOP 0x00FF 0x01FF 0x03FF OCR1A ICR1
16T/C16AVRT/C * * * * * * * * 16 T/C I/O 16 T/C PWM10 WGM10 PWM11 WGM11 CTC1 WGM12 TCCR1A FOC1A FOC1B TCCR1B WGM13
16 T/C
16 T/C
82
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
16
TCNT1 OCR1A/B ICR1 AVR CPU 8 16 16 1688 16 16 16 CPU 16 8 8 16 16 CPU 16 16 OCR1A/B 16 16 16 OCR1A/B ICR1 "C" 16 (1)
... ; TCNT1 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; TCNT1 r17:r16 in in ... r16,TCNT1L r17,TCNT1H
C (1)
unsigned int i; ... /* TCNT1 0x01FF */ TCNT1 = 0x1FF; /* TCNT1 i */ i = TCNT1; ...
Note:
1.
TCNT1 r17:r16 16 16 16 16 16
83
2503F-AVR-12/03
TCNT1 OCR1A/B ICR1 (1)
TIM16_ReadTCNT1: ; in cli ; TCNT1 r17:r16 in in r16,TCNT1L r17,TCNT1H r18,SREG ;
; out SREG,r18 ret
C (1)
unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ i = TCNT1; /* */ SREG = sreg; return i; }
Note:
1.
TCNT1 r17:r16
84
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
TCNT1 OCR1A/B ICR1 (1)
TIM16_WriteTCNT1: ; in cli ; TCNT1 r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; out SREG,r18 ret r18,SREG ;
C (1)
void TIM16_WriteTCNT1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ TCNT1 = i; /* */ SREG = sreg; }
Note:
1.
r17:r16 TCNT1 16 T/C T/C B(TCCR1B) (CS12:0) P79 "T/C0 T/C1 " 16 T/C 16 Figure 41
T/C
85
2503F-AVR-12/03
Figure 41.
DATA BUS
(8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction Control Logic clkTn Edge Detector Tn
TCNTn (16-bit Counter)
( From Prescaler ) TOP BOTTOM
( ) Count Direction Clear clkT1 TOP BOTTOM TCNT1 1 1 TCNT1 / TCNT1 TCNT1 (0)
16 8 I/O TCNT1H 8 TCNT1L 8 CPU TCNT1H CPU TCNT1H (TEMP) TCNT1L TCNT1HTCNT1L TCNT1H CPU 8 16 TCNT1 clkT1 1 1 clkT1 CS12:0 CS12:0= 0 CPU TCNT1 clkT1 CPU TCCR1A TCCR1B WGM13:0 ( ) OC1x P91 " " WGM13:0 TOV1 TOV1 CPU
86
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
T/C ICP1 Figure 42 "n" / Figure 42.
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACO* Analog Comparator ICPn
ACIC*
ICNC
ICES
Noise Canceler
Edge Detector
ICFn (Int.Req.)
ICP1 ( ) ACO 16 TCNT1 ICR1 ICF1 ICIE1 = 1 ICF1 I/O "1" ICR1 ICR1L ICR1H TEMP CPU ICR1H TEMP ICR1 ICR1 TOP ICR1 WGM13:0 ICR1 ICR1H I/O ICR1L P84 " 16 " 16 ICP1T/C1 ACSR ACIC ICP1 ACO T1 (P79 Figure 38 ), 4 ICR1 TOP T/C
87
2503F-AVR-12/03
ICP1 4 4 TCCR1B ICNC1 ICR1 4 ICR1 ICR1 ICR1 TOP ICR1 ICF1 ( I/O "1") ICF1
16 TCNT1 OCR1x OCF1x OCIE1x = 1 OCF1x OCF1x I/O "1" WGM13:0 COM1x1:0 TOP BOTTOM (P91 " " ) A T/C TOP ( ) TOP Figure 43 "n" (n = 1 T/C1) "x" (A/B)
88
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 43.
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.) TOP BOTTOM
Waveform Generator
OCnx
WGMn3:0
COMnx1:0
T/C 12 PWM OCR1x (CTC) OCR1x TOP BOTTOM PWM OCR1x CPU OCR1x CPU OCR1x OCR1x( ) (T/C TCNT1 ICR1 ) OCR1x TEMP 16 OCR1x TEMP OCR1xH CPU I/O TEMP OCR1xL TEMP OCR1x OCR1x P84 " 16 " 16 PWM FOC1x "1" OCF1x / OC1x (COMx1:0 OC1x ) CPUTCNT1 OCR1x TCNT1 TCNT1 TCNT1 T/C TCNT1OCR1x PWM TOP TCNT1 TOP 0xFFFF TCNT1BOTTOM OC1x OC1x FOC1x OC1x 89
2503F-AVR-12/03
TCNT1
COM1x1:0 COM1x1:0
COM1x1:0 COM1x1:0 OC1x COM1x1:0 OC1x Figure 44 COM1x1:0 I/O I/O I/O COM1x1:0 I/O (DDR PORT) OC1x OC1x OC1x COM1x "0" Figure 44.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D
DATABUS
0
Q
PORT D Q
DDR
clk I/O
COM1x1:0 OC1x I/O OC1x (DDR) OC1x DDR_OC1x Table 44Table 45 Table 46 OC1x COM1x1:0 P100 "16 / " COM1x1:0 COM1x1:0 CTC PWM COM1x1:0 = 0 OC1x PWM P99 Table 44 PWM P100 Table 45 PWM P100 Table 46 COM1x1:0 PWM FOC1x
- T/C - (WGM13:0) (COM1x1:0) COM1x1:0 PWM PWM COM1x1:0 (P91 " " ) P97 " / "
90
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
(WGM13:0 = 0) (TOP = 0xFFFF) 0x0000 TCNT1T/CTOV1 TOV117 TOV1 CPU CTC( ) CTC (WGM13:0 = 4 12) OCR1A ICR1 TCNT1 OCR1A(WGM13:0 = 4) ICR1 (WGM13:0 = 12) OCR1A ICR1 TOP CTCFigure 45 TCNT1TCNT1OCR1A ICR1 TCNT1 Figure 45. CTC
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnA (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
OCF1A ICF1 TOP TOP CTC TOP BOTTOM OCR1A ICR1 TCNT1 0xFFFF 0x0000 OCR1A ICR1 PWM OCR1A TOP (WGM13:0 = 15) OCR1A CTC OC1A COM1A1:0 = 1 OC1A (DDR_OC1A = 1) fOC1A = fclk_I/O/2 (OCR1A = 0x0000) f clk_I/O f OCnA = ---------------------------------------------------2 N ( 1 + OCRnA ) N (1 8 64 256 1024) TOV1 MAX 0x0000
91
2503F-AVR-12/03
PWM
PWM (WGM13:0 = 5 6 7 14 15) PWM PWM PWM BOTTOM TOP BOTTOM OC1x TCNT1 OCR1x TOP OCR1x PWM PWM PWM DAC ( ) PWM PWM 89 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R FPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 5 6 7)ICR1 (WGM13:0 = 14) OCR1A (WGM13:0 = 15) Figure 46 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 46. PWM
OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set OCnA Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
TOP T/C TOV1 TOP OCR1A ICR1 OC1A ICF1 TOV1 TOP TOPTOP TCNT1OCR1x TOP OCR1x "0" TOP ICR1 OCR1A ICR1 ICR1 ICR1 TCNT1 0xFFFF 0x0000 OCR1A OCR1A OCR1A TCNT1 TOP 92
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
OCR1A TCNT1 TOV1 TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P99 Table 44 ) OC1x DDR_OC1x PWM OC1x OCR1x TCNT1 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = ----------------------------------N ( 1 + TOP )
N (1 8 64 256 1024) OCR1x PWM OCR1x BOTTOM(0x0000) TOP+1OCR1xTOP COM1x1:0 OC1A (COM1A1:0 = 1) 50% OCR1A TOP (WGM13:0 = 15) OCR1A 0(0x0000) fOC1A = fclk_I/O/2 CTC OC1A PWM PWM PWM (WGM13:0 = 1 2 3 11) 10 PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1x BOTTOM TCNT1 OCR1x OC1x PWM PWM 8 9 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 12 3) ICR1 (WGM13:0 = 10) OCR1A (WGM13:0 = 11) TCNT1 TOP Figure 47 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x
93
2503F-AVR-12/03
Figure 47. PWM
OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
BOTTOM T/C TOV1 TOP OCR1A ICR1 OCR1x OC1A ICF1 TOPTOP TCNT1OCR1x TOP OCR1x "0" Figure 47 T/C TOP OCR1x OCR1x / TOP PWM TOP TOP T/C TOP TOP PWM OC1x PWM COM1x1:0 2 PWM COM1x1:0 3 PWM ( P99 Table 44 ) OC1x DDR_OC1x OCR1x TCNT1 OC1x PWM PWM f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 11) COM1A1:0 = 1 OC1A 50% PWM PWM (WGM13:0 = 8 9) - PWM - PWM PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x
94
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
OC1xBOTTOMTCNT1OCR1x OC1x PWM PWM OCR1x Figure 47 Figure 48 PWM PWM ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) PWM ICR1 (WGM13:0 = 8) OCR1A (WGM13:0 = 9) TCNT1 TOP Figure 48 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 48. PWM
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
OCR1x T/C TOV1 TOP OCR1A ICR1 TCNT1 TOP OC1A CF1 TOP BOTTOM TOPTOP TCNT1OCR1x Figure 48 PWM OCR1x BOTTOM TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A
95
2503F-AVR-12/03
PWM OC1x PWM COM1x1:0 2 PWM 3 PWM P100 ( Table ) OC1x PWM OC1x OCR1x TCNT1 ( ) TCNT1 ( ) PWM f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 9) COM1A1:0 = 1 OC1A 50%
/
/ clkT1 OCR1x OCR1x ( ) Figure 49 OCF1x Figure 49. T/C OCF1x
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 50
96
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 50. T/C OCF1x fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 51 TOP PWM OCR1x BOTTOM TOP BOTTOM BOTTOM+1 TOP-1 BOTTOM TOV1 Figure 51. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 52
97
2503F-AVR-12/03
Figure 52. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
98
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
16 /
T/C1 A TCCR1A
Bit / 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
FOC1A
2
FOC1B
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
W 0
W 0
R/W 0
R/W 0
* Bit 7:6 - COM1A1:0: A * Bit 5:4 - COM1B1:0: B COM1A1:0 COM1B1:0 OC1A OC1B COM1A1:0(COM1B1:0) "1"OC1A(OC1B) I/O OC1A(OC1B) OC1A(OC1B) COM1x1:0 WGM13:0 Table 44 WGM13:0 CTC ( PWM) COM1x1:0 Table 44. PWM
COM1A1/COM1B1 0 0 1 1 COM1A0/COM1B0 0 1 0 1 OC1A/OC1B OC1A/OC1B OC1A/OC1B( ) OC1A/OC1B ( )
Table 45 WGM13:0 PWM COM1x1:0
99
2503F-AVR-12/03
Table 45. PWM(1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13:0 = 15: OC1A OC1B WGM13:0 OC1A/OC1B OC1A/OC1BOC1A/OC1B TOP OC1A/OC1B OC1A/OC1B TOP
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 OC1A/OC1B / P93 " PWM "
Table 46WGM13:0PWMPWMCOM1x1:0 Table 46. PWM (1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13:0 = 9 14: OC1A OC1B WGM13:0 OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 P94 " PWM "
* Bit 3 - FOC1A: A * Bit 2 - FOC1B: B FOC1A/FOC1BWGM13:0PWM PWM TCCR1A FOC1A/FOC1B 1 COM1x1:0 OC1A/OC1B FOC1A/FOC1B COM1x1:0 CTC OCR1A TOP FOC1A/FOC1B FOC1A/FOC1B 0 * Bit 1:0 - WGM11:0: TCCR1B WGM13:2 ---- Table 47 T/C
100
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
( ) (CTC) (PWM) P91 " " Table 47. (1)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 (PWM10) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 / 8 PWM 9 PWM 10 PWM CTC 8 PWM 9 PWM 10 PWM PWM PWM PWM PWM CTC PWM PWM TOP
0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A
OCR1x
TOP TOP TOP
TOV1
MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
TOP TOP TOP BOTTOM BOTTOM TOP TOP
- TOP TOP
1. CTC1 PWM11:0 WGM12:0
101
2503F-AVR-12/03
T/C1 B TCCR1B
Bit / 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 WGM13 R/W 0 3 WGM12 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B
* Bit 7 - ICNC1: ICNC1 ICP1 ICP1 4 4 4 * Bit 6 - ICES1: ICP1 ICES "0" ICES1 "1" ICES1 ICR1 ICF1 ICR1 TOP ( TCCR1A TCCR1B WGM13:0 ) ICP1 * Bit 5 - TCCR1B "0" * Bit 4:3 - WGM13:2: TCCR1A * Bit 2:0 - CS12:0: 3 T/C Figure 49 Figure 50 Table 48.
CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 (T/C ) clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T1 T1
T1 T/C1 T/C1 TCNT1H TCNT1L
Bit 7 6 5 4 3 2 1 0 TCNT1H TCNT1L TCNT1[15:8] TCNT1[7:0]
102
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
/ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNT1HTCNT1LT/C1TCNT1 / 16 CPU 8 TEMPTEMP 16 P84 " 16 " TCNT1TCNT1OCR1x TCNT1 1A OCR1AH OCR1AL
Bit
7
6
5
4
3
2
1
0 OCR1AH OCR1AL
OCR1A[15:8] OCR1A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
1B OCR1BH OCR1BL
Bit
7
6
5
4
3
2
1
0 OCR1BH OCR1BL
OCR1B[15:8] OCR1B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
16 TCNT1 OC1x 16 CPU 8 TEMP TEMP 16 P84 " 16 " 1 ICR1H ICR1L
Bit
7
6
5
4 ICR1[7:0]
3
2
1
0 ICR1H ICR1L
ICR1[15:8] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
ICP1(T/C1) TCNT1 ICR1 ICR1 TOP 16 CPU 8 TEMP TEMP 16 P84 " 16 " T/C1 TIMSK(1)
Bit /
7 OCIE2 R/W 0
6 TOIE2 R/W 0
5 TICIE1 R/W 0
4 OCIE1A R/W 0
3 OCIE1B R/W 0
2 TOIE1 R/W 0
1 OCIE0 R/W 0
0 TOIE0 R/W 0 TIMSK
Note:
1. T/C T1
103
2503F-AVR-12/03
* Bit 5 - TICIE1: T/C1 "1" I "1" T/C1 TIFR ICF1 CPU T/C1 ( P42 " " ) * Bit 4 - OCIE1A: T/C1 A "1" I "1" T/C1 A TIFR OCF1A CPU T/C1 A ( P42 " " ) * Bit 3 - OCIE1B: T/C1 B "1" I "1" T/C1 B TIFR OCF1B CPU T/C1 B ( P42 " " ) * Bit 2 - TOIE1: T/C1 "1" I "1" T/C1 TIFR TOV1 CPU T/C1 ( P42 " " ) T/C TIFR
Bit / 7 OCF2 R/W 0 6 TOV2 R/W 0 5 ICF1 R/W 0 4 OCF1A R/W 0 3 OCF1B R/W 0 2 TOV1 R/W 0 1 OCF0 R/W 0 0 TOV0 R/W 0 TIFR
Note:
T/C T1
* Bit 5 - ICF1: T/C1 ICP1 ICF1 ICR1 TOP TOP ICF1 ICF1 "1" * Bit 4 - OCF1A: T/C1 A TCNT1 OCR1A "1" (FOC1A) OCF1A A OCF1A "1" * Bit 3 - OCF1B: T/C1 B TCNT1 OCR1B "1" (FOC1B) OCF1B B OCF1B "1" * Bit 2 - TOV1: T/C1 T/C1 CTC T/C1 TOV1 TOV1 P101 Table 47
104
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
TOV1 "1"
105
2503F-AVR-12/03
8 PWM / 2
T/C2 8 / * * ( ) * , (PWM) * * 10 * (TOV2 OCF2) * 32 kHz I/O Figure 53 8 T/C P2 "ATmega32 " CPU I/O I/O I/O I/O P116 "8 T/C " Figure 53. 8 T/C
TCCRn
count clear direction Control Logic
TOVn (Int.Req.) clkTn TOSC1
BOTTOM
TOP Prescaler
T/C Oscillator TOSC2
Timer/Counter TCNTn
=0
= 0xFF
OCn (Int.Req.) clkI/O
DATABUS
=
Waveform Generation
OCn
OCRn Synchronized Status flags clkI/O Synchronization Unit clkASY Status flags ASSRn asynchronous mode select (ASn)
/ TCNT2 OCR2 8 ( Int.Req.) TIFR TIMSK TIFR TIMSK T/C TOSC1/2 ASSR T/C()T/C clkT2 OCR2 TCNT2 PWM OC2 P109 " " OCF2
106
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
"n" / 2 ( TCNT2 T/C2 ) Table 49 Table 49. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR2
T/C
T/C clkT2 MCU clkI/O ASSR AS2 TOSC1 TOSC2 P119 " -ASSR" P121 " / " 8T/CFigure 54 Figure 54.
DATA BUS
TOVn (Int.Req.)
TOSC1 count TCNTn clear direction Control Logic clk Tn Prescaler T/C Oscillator TOSC2
bottom
top
clkI/O
( ) count direction clear clkT2 top bottom TCNT2 1 1 TCNT2 ( ) T/C TCNT2 TCNT2 (0)
clkT2 clkT2 CS22:0 (CS22:0 = 0) clkT2 CPU TCNT2 CPU ( ) T/C (TCCR2) WGM21 WGM20 OC2 P110 " " T/CTOV2WGM21:0 TOV2CPU
107
2503F-AVR-12/03
8 TCNT2 OCR2 TCNT2 OCR2 OCF2 OCIE2 = 1 OCF2 "1" WGM21:0 COM21:0 max bottom ( P110 " " ) Figure 55 Figure 55.
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top bottom FOCn
Waveform Generator
OCxy
WGMn1:0
COMn1:0
PWM OCR2 OCR2 top bottom PWM OCR2 CPU OCR2 CPU OCR2 PWM FOC2 "1" OCF2 / OC2 (COM21:0 OC2 ) CPU TCNT2 OCR2 TCNT2 TCNT2 TCNT2 T/C TCNT2 OCR2 TCNT2 BOTTOM OC2 OC2 FOC2 OC2
TCNT2
108
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
COM21:0 COM21:0
COM21:0 COM21:0 (OC2) COM21:0 OC2 Figure 56 COM21:0 I/O I/O I/O COM21:0 I/O (DDR PORT) OC2 OC2 OC2 Figure 56.
COMn1 COMn0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCn D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM21:0 OC2 I/O OC2 (DDR) OC2 DDR_OC2 OC2 COM21:0 P116 "8 T/C " COM21:0 CTC PWM COM21:0 = 0 OC2 PWM P115 Table 51 PWM P116 Table 52 PWM P116 Table 53 COM21:0 PWM FOC2
- T/C - (WGM21:0) (COM21:0) COM21:0 PWM PWM COM21:0 (P110 " " ) P113 "T/C "
109
2503F-AVR-12/03
(WGM21:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV2 TOV2 9 TOV2 CPU
CTC( )
CTC (WGM21:0 = 2) OCR2 TCNT2 OCR2 OCR2 TOP CTCFigure 57 TCNT2TCNT2OCR2 TCNT2 Figure 57. CTC
OCn Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMn1:0 = 1)
OCF2 TOP TOP CTC TOP BOTTOM OCR2 TCNT2 0xFF 0x00 OCR2 CTC OC2 COM21:0 = 1 OC2 fOC2 = fclk_I/O/2 (OCR2 = 0x00) f clk_I/O f OCn = -----------------------------------------------2 N ( 1 + OCRn ) N (1 8 32 64 128 256 1024) TOV2 MAX 0x00 PWM PWM (WGM21:0 = 3) PWM PWM PWM BOTTOMMAX BOTTOM OC2 TCNT2 OCR2 BOTTOM OC2 PWM PWM
110
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
PWM DAC ( ) PWM MAX Figure 58 TCNT0 PWM PWM TCNT2 OCR2 TCNT2 Figure 58. PWM
OCRn Interrupt Flag Set
OCRn Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
4
5
6
7
MAX T/C TOV2 PWM OC2 PWM COM21:0 2 PWM 3 PWM ( P116 Table 52 ) OC2 PWM OC2 OCR2 TCNT2 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnPWM = -----------------N 256 N (1 8 32 64 128 256 1024) OCR2 PWM OCR2 BOTTOM MAX+1 OCR2 MAX COM21:0 OC2 (COM21:0 = 1) 50% OCR2 0 foc2 = fclk_I/O/2 CTC OC2 PWM PWM PWM (WGM21:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT2 OCR2 OC2 BOTTOM TCNT2 OCR2 OC2 111
2503F-AVR-12/03
PWM PWM 8 MAX TCNT2 MAX Figure 59 TCNT2 PWM PWM TCNT2 OCR2 TCNT2 Figure 59. PWM
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV2 PWM OC2 PWM COM21:0 2 PWM COM21:0 3 PWM ( P116 Table 53 ) OC2 OCR2 TCNT2 OC2 PWM PWM f clk_I/O f OCnPCPWM = -----------------N 510 N (1 8 32 64 128 256 1024) OCR2 PWM PWM OCR2 BOTTOM OCR2 MAX PWM Figure 59 2 OCn BOTTOM * Figure 59 OCR2A MAX OCR2A MAX OCn BOTTOM T/C MAX OCn OCn OCR2A OCn
*
T/C
T/C clkT2 clkI/O T/C Figure 60 T/C PWM MAX
112
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 60. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 61 Figure 61. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 62 ( CTC )OCF2 Figure 62. T/C OCF2 fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
113
2503F-AVR-12/03
Figure 63 CTC OCF2 TCNT2 Figure 63. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
114
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
8 T/C
T/C TCCR2
Bit / 7 FOC2 W 0 6 WGM20 R/W 0 5 COM21 R/W 0 4 COM20 R/W 0 3 WGM21 R/W 0 2 CS22 R/W 0 1 CS21 R/W 0 0 CS20 R/W 0 TCCR2
* Bit 7 - FOC2: FOC2 WGM PWM PWM TCCR2 1 OC2 COM21:0 FOC2 COM21:0 FOC2 OCR2 TOP CTC FOC2 0 * Bit 6, 3 - WGM21:0: TOP T/C (CTC) PWM Table 50 P110 " " Table 50. (1)
0 1 2 3 Note: WGM21 (CTC2) 0 0 1 1 WGM20 (PWM2) 0 1 0 1 T/C PWM CTC PWM TOP 0xFF 0xFF OCR2 0xFF OCR2 TOP TOP TOV2 MAX BOTTOM MAX MAX
1. CTC2 PWM2 WGM21:0
* Bit 5:4 - COM21:0: OC0 COM01:0 OC0 1 OC0 COM01:0 WGM01:0 Table 51 WGM01:0 CTC COM01:0 Table 51. PWM
COM21 0 0 1 1 COM20 0 1 0 1 OC2 OC2 OC2 OC2
115
2503F-AVR-12/03
Table 52 WGM21:0 PWM COM21:0 Table 52. PWM (1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 OC2 OC2 TOP OC0 OC2 TOP OC0
1. OCR2 TOP COM21 TOP P111 " PWM "
Table 53 WGM21:0 PWM COM21:0
.
Table 53. PWM (1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 OC2 OC2 OC2 OC2 OC2
1. OCR2 TOP COM21 TOP P112 " PWM "
* Bit 2:0 - CS22:0: T/C Table 54 Table 54.
CS22 0 0 0 0 1 1 1 1 CS21 0 0 1 1 0 0 1 1 CS20 0 1 0 1 0 1 0 1 T/C
clkT2S/( ) clkT2S/8 ( ) clkT2S/32 ( ) clkT2S/64 ( ) clkT2S/128 ( )
clkT2S/256 ( ) clkT2S/1024 ( )
/ TCNT2
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT2 R/W 0 TCNT2[7:0]
116
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
T/C 8 TCNT2 TCNT2 TCNT2 OCR2 OCR2
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR2 R/W 0 OCR2[7:0]
8 TCNT2 OC2
117
2503F-AVR-12/03
/
ASSR
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 AS2 R/W 0 2 TCN2UB R 0 1 OCR2UB R 0 0 TCR2UB R 0 ASSR
* Bit 3 - AS2: T/C2 AS2"0"T/C2I/OclkI/OAS2"1"T/C2TOSC1 AS2 TCNT2 OCR2 TCCR2 * Bit 2 - TCN2UB: T/C2 T/C2 TCNT2TCN2UB TCNT2 TCN2UB TCN2UB 0 TCNT2 * Bit 1 - OCR2UB: 2 T/C2 OCR2OCR2UB OCR2 OCR2UB OCR2UB 0 OCR2 * Bit 0 - TCR2UB: T/C2 T/C2 TCCR2TCR2UB TCCR2 TCR2UB TCR2UB 0 TCCR2 TCNT2 OCR2 TCCR2 TCNT2 OCR2 TCCR2 / 2 T/C2 * TCNT2OCR2 TCCR2 1. OCIE2 TOIE2 T/C2 2. AS2 3. TCNT2 OCR2 TCCR2 4. TCN2UB OCR2UB TCR2UB 5. T/C2 6. * * 32.768 kHz TOSC1 T/C2 4 TCNT2 OCR2 TCCR2 TOSC1 3 TCNT2 OCR2 ASSR T/C2 MCU Standby TCNT2 OCR2ATCCR2A MCUT/C2 T/C2 MCU OCR2 TCNT2 (OCR2UB
*
118
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
0)MCU MCU * T/C2Standby TOSC1 TOSC1 1. TCCR2 TCNT2 OCR2 2. ASSR 3. Standby * T/C2 32.768 kHz Standby 1 /Standby 1 T/C2 T/C2 Standby MCU 4 SLEEP TCNT2 TCNT2 TOSC TCNT2 I/O TOSC1 I/O TCNT2 TOSC1 TOSC1 TCNT2 1. OCR2 TCCR2 2. 3. TCNT2 * 3
*
*
/ TIMSK
Bit /
7 OCIE2 R/W 0
6 TOIE2 R/W 0
5 TICIE1 R/W 0
4 OCIE1A R/W 0
3 OCIE1B R/W 0
2 TOIE1 R/W 0
1 OCIE0 R/W 0
0 TOIE0 R/W 0 TIMSK
* Bit 7 - OCIE2: T/C2 OCIE2 I "1" T/C2 A T/C2 TIFR OCF2 * Bit 6 - TOIE2: T/C2 TOIE2 I "1" T/C2 T/C2 TIFR TOV2 / TIFR
Bit /
7 OCF2 R/W
6 TOV2 R/W
5 ICF1 R/W
4 OCF1A R/W
3 OCF1B R/W
2 TOV1 R/W
1 OCF0 R/W
0 TOV0 R/W TIFR
119
2503F-AVR-12/03
0
0
0
0
0
0
0
0
* Bit 7 - OCF2: 2 T/C2 OCR2( 2) OCF2 1 SREG IOCIE2 OCF2 * Bit 6 - TOV2: T/C2 T/C2 TOV2 TOV2 1 SREG I TOIE2 TOV2 PWM T/C2 0x00 TOV2
/
Figure 64. T/C2
clkI/O TOSC1 clkT2S Clear
10-BIT T/C PRESCALER
clkT2S/32
clkT2S/64
AS2
PSR2
0
CS20 CS21 CS22
TIMER/COUNTER2 CLOCK SOURCE clkT2
T/C2 clkT2S clkT2S clkI/O ASSR AS2 T/C2 TOSC1 T/C2 RTC TOSC1 TOSC2 C ( 32.768 kHz ) TOSC1 T/C2 clkT2S/8 clkT2S/32 clkT2S/64 clkT2S/128 clkT2S/256 clkT2S/1024 clkT2S 0 () SFIORPSR2 IO SFIOR
Bit / 7 ADTS2 R/W 0 6 ADTS1 R/W 0 5 ADTS0 R/W 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 1 - PSR2: T/C2 1 T/C2 0 CPU T/C2 0 T/C2 1 120
ATmega32(L)
2503F-AVR-12/03
clkT2S/1024
clkT2S/8
clkT2S/128
clkT2S/256
ATmega32(L)
SPI
SPI ATmega32 AVR ATmega32 SPI * 3 * * LSB MSB * 7 * * * * (CK/2) Figure 65. SPI (1)
DIVIDER /2/4/8/16/32/64/128
SPI2X
Note:
1. SPI P2 Figure 1 P55 Table 25
SPI Figure 66 SS SCK MOSI MOSI MISO MISO SS SPI SPI SS SPI SPI 8 SPI SPIF SPCR SPI SPIE SPDR SS
SPI2X
121
2503F-AVR-12/03
SS SPI MISO SPI SPDR SCK SPDR SS SPIF SPCRSPISPIE SPDR Figure 66. SPI -
MSB MASTER LSB MISO MOSI MISO MOSI MSB SLAVE LSB 8 BIT SHIFT REGISTER 8 BIT SHIFT REGISTER
SPI CLOCK GENERATOR
SCK SS
SCK SS
SHIFT ENABLE
SPI SPI SPI SPI SCK SPI fosc/4 SPI MOSI MISO SCK SS Table 55 P52 " " Table 55. SPI
MOSI MISO SCK SS Note: SPI SPI
P55 " B " SPI
SPI DDR_SPIDD_MOSI DD_MISODD_SCK
122
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
MOSI PB5 DD_MOSI DDB5 DDR_SPI DDRB (1)
SPI_MasterInit: ; MOSI SCK ldi out ldi out ret SPI_MasterTransmit: ; (r16) out SPDR,r16 Wait_Transmit: ; sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1<; SPI fck/16
C (1)
void SPI_MasterInit(void) { /* MOSI SCK */ DDR_SPI = (1<Note:
1.
123
2503F-AVR-12/03
SPI (1)
SPI_SlaveInit: ; MISO ldi out ldi out ret SPI_SlaveReceive: ; sbis SPSR,SPIF rjmp SPI_SlaveReceive ; in ret r16,SPDR r17,(1<; SPI
C (1)
void SPI_SlaveInit(void) { /* MISO */ DDR_SPI = (1<Note:
1.
124
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
SS
SPI SS SS SPI MISO ( ) SS SPI SS / SS SPI SPI (MSTR SPCR ) SS SS I/O SPI SS SS SPI SS SPI SPI 1. SPCR MSTR SPI MOSI SCK 2. SPSR SPIF SPI SPI SS MSTR "1" SPI SPI SPCR
Bit / 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* Bit 7 - SPIE: SPI SPSR SPIF SREG SPI * Bit 6 - SPE: SPI SPE SPI SPI SPE * Bit 5 - DORD: DORD LSB MSB * Bit 4 - MSTR: / MSTR MSTR "1" SS MSTR SPSR SPIF MSTR
125
2503F-AVR-12/03
* Bit 3 - CPOL: CPOL SCK SCK Figure 67 Figure 68 CPOL Table 56. CPOL
CPOL 0 1
* Bit 2 - CPHA: CPHA SCK SCK Figure 67 Figure 68 Table 57. CPHA
CPHA 0 1
* Bits 1, 0 - SPR1, SPR0: SPI 1 0 SCK SPR1 SPR0 SCK fosc Table 58. SCK
SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK
fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64
126
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
SPI SPSR
Bit / 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* Bit 7 - SPIF: SPI SPIF SPCR SPIE SPI SPI SS SPIF SPIF SPSR SPDRSPIF * Bit 6 - WCOL: SPI SPDR WCOL WCOL SPSR SPDR * Bit 5..1 - Res: * Bit 0 - SPI2X: SPI SPI ( Table 58) SCK CPU fosc /4 ATmega32 SPI EEPROM P253 SPI SPI SPDR
Bit / 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X SPDR
SPI / SPI
127
2503F-AVR-12/03
SCK 4 CPHA CPOL SPI Figure 67 Figure 68 SCK Table 56 Table 57 Table 59. CPOL CPHA
CPOL = 0, CPHA = 0 CPOL = 0, CPHA = 1 CPOL = 1, CPHA = 0 CPOL = 1, CPHA = 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) SPI 0 1 2 3
Figure 67. CPHA = 0 SPI
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 68. CPHA = 1 SPI
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
128
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
USART
(USART) * ( ) * * * * 5, 6, 7, 8, 9 1 2 * * * * * , * * Figure 69 USART CPU I/O I/O Figure 69. USART (1)
Clock Generator
UBRR[H:L] OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN CONTROL
XCK
Transmitter
UDR (Transmit) PARITY GENERATOR TRANSMIT SHIFT REGISTER PIN CONTROL TxD TX CONTROL
DATABUS
Receiver
CLOCK RECOVERY RX CONTROL
RECEIVE SHIFT REGISTER
DATA RECOVERY
PIN CONTROL
RxD
UDR (Receive)
PARITY CHECKER
UCSRA
UCSRB
UCSRC
Note:
1. P2 Figure 1 P61 Table 33 P57 Table 27 USART
USART : XCK ( ) 129
2503F-AVR-12/03
USART UDR AVR USART AVR UART USART AVR UART * * * * * * USART FIFO FE DOR 9 RXB8 UDR ( Figure 69) USART (DOR) CHR9 UCSZ2 OR DOR
*
* *
USART 4 : USART UMSEL C (UCSRC) ( ) UCSRA U2X (UMSEL = 1) XCK (DDR_XCK)()() XCK Figure 70 Figure 70.
UBRR fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 U2X
0 1
OSC DDR_XCK Sync Register Edge Detector
0 1
txclk
xcki XCK Pin xcko
0 1
UMSEL
DDR_XCK
UCPOL
1 0
rxclk
130
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
txclk rxclk xcki xcko fosc ( ) ( ) XCK ( ) XCK ( ) XTAL ( )
Figure 70 USART UBRR UBRRL UBRR fosc/(UBRR+1) 2 8 16 2 816 UMSEL U2X DDR_XCK Table 60(/)UBRR Table 60.
(U2X = 0) (U2X = 1) (1) UBRR
f OSC f OSC BAUD = --------------------------------------- UBRR = ----------------------- - 1 16 ( UBRR + 1 ) 16BAUD f OSC BAUD = -----------------------------------8 ( UBRR + 1 ) f OSC BAUD = -----------------------------------2 ( UBRR + 1 ) f OSC UBRR = -------------------- - 1 8BAUD f OSC UBRR = -------------------- - 1 2BAUD
Note:
1. (bps)
BAUD ( bps) fOSC UBRR UBRRH UBRRL (0-4095) Table 68 UBRR (U2X) UCSRA U2X "0" 16 8 Figure 70 XCK CPU XCK f OSC f XCK < -----------4
131
2503F-AVR-12/03
fosc
(UMSEL = 1)XCK ( ) ( ) TxD XCK RxD Figure 71. XCK .
UCPOL = 1 XCK
RxD / TxD Sample UCPOL = 0 XCK
RxD / TxD Sample
UCRSC UCPOL XCK Figure 71 UCPOL=0 XCK XCK UCPOL=1 XCK XCK
( ) USART 30 * * * * 1 5 6 7 8 9 1 2
9 Figure 72 Figure 72.
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P] Sp1 [Sp2]
(St / IDLE)
St (n) P Sp IDLE
(0 8) (RxD TxD)
132
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
UCSRB UCSRC UCSZ2:0 UPM1:0 USBS USART UCSZ2:0 UPM1:0 USBS (FE) "0" P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn n
133
2503F-AVR-12/03
USART
USART USART ( ) USART TXC RXC ( UDR )TXC USART ( ) r17:r16 UCSRC UBRRH UCSRC I/O URSEL (MSB) (1)
USART_Init: ; out out ldi out ldi out ret UBRRH, r17 UBRRL, r16 r16, (1<;
; : 8 , 2
C (1)
void USART_Init( unsigned int baud ) { /* */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* */ UCSRB = (1<Note:
1.
I/O
134
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
USART UCSRB TXEN USART TxD
I/O USART XCK CPU UDR ( ) UDRE 8 UDR USART R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; out ret UDR,r16
5 8
C (1)
void USART_Transmit( unsigned char data ) { /* */ while ( !( UCSRA & (1<Note:
1.
UDRE
135
2503F-AVR-12/03
9
9 (UCSZ = 7) 9 UCSRB TXB8 8UDR 9 R17:R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; 9 r17 TXB8 cbi sbi out ret UCSRB,TXB8 UCSRB,TXB8 UDR,r16 sbrc r17,0 ; 8
C (1)
void USART_Transmit( unsigned int data ) { /* */ while ( !( UCSRA & (1<Note:
1. UCSRB UCSRB TXB8
9 USART USART UDRE TXC UDRE "1" UCSRA "0" UCSRB UDRIE "1" UDRE ( ) USART UDR UDRE UDR UDRE TXC TXC "1" TXC RS-485
136
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
UCSRB TXCIE "1" TXC USART TXC TXC (UPM1 = 1) TXEN TxD I/O
137
2503F-AVR-12/03
USART UCSRB (RXEN) USART RxD
USART XCK
5 8
XCK UDR RXC 8 UDR 0 USART (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; in ret r16, UDR
C (1)
unsigned char USART_Receive( void ) { /* */ while ( !(UCSRA & (1<Note:
1.
RXC
138
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
9 9 (UCSZ=7) UDR 8 UCSRB RXB8 9 FE DOR UPE UCSRA UDR UDR FIFO FIFO TXB8 FE DOR UPE USART 9 (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; 9 in in in r18, UCSRA r17, UCSRB r16, UDR
; -1 andi r18,(1<USART_ReceiveNoError: ; 9 lsr ret r17 andi r17, 0x01
C (1)
unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* */ while ( !(UCSRA & (1<> 1) & 0x01; return ((resh << 8) | resl); }
Note:
1.
I/O USART 139
2503F-AVR-12/03
(RXC) 1 0( ) (RXEN = 0) RXC UCSRB (RXCIE) RXC ( ) USART UDR RXC USART (FE) (DOR) (UPE) UCSRA UDR UCSRA (UDR) "0" (FE) ( 1) FE 0 FE 1 UCSRC USBS FE UCSRA 0 (DOR) ( ) DOR UDR UDR UCSRA 0 DOR (PE) UPE UCSRA 0 P134 " " P141 " " UPM1 ( ) UPM0 (UPE) (UPM1 = 1) UPE (UDR) (RXEN ) RxD FIFO
140
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
FIFO UDR RXC (1)
USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush
C (1)
void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<Note:
1.
USART RxD Figure 73 16 8 (U2X = 1) RxD ( ) 0 Figure 73.
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
RxD ( ) ( ) 1 0 8 9 10( ) 4 5 6( ) ( ) 16 8 Figure 74
141
2503F-AVR-12/03
Figure 74.
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
2 3 1 2 3 0RxD Figure 75 Figure 75.
RxD STOP 1
(A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
0 FE Figure 75 A B C ( Table 61) ( D + 1 )S R slow = --------------------------------------------S - 1 + D S + SF ( D + 2 )S R fast = ------------------------------------( D + 1 )S + S M D S SF (D = 5 10 ) S = 16 S = 8 SF = 8 SF = 4
142
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
SM SM = 9 SM = 5 Rslow Rfast Table 61 Table 62 Table 61. (U2X = 0)
D # ( + ) 5 6 7 8 9 10 Rslow (%) 93.20 94.12 94.81 95.36 95.81 96.17 Rfast(%) 106.67 105.79 105.11 104.58 104.14 103.78 (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 (%) 3.0 2.5 2.0 2.0 1.5 1.5
Table 62. (U2X = 1)
D # ( + ) 5 6 7 8 9 10 Rslow (%) 94.12 94.92 95.52 96.00 96.39 96.70 Rfast (%) 105.66 104.92 104.35 103.90 103.53 103.23 (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 (%) 2.5 2.0 1.5 1.5 1.5 1.0
(XTAL) 2% UBRR
143
2503F-AVR-12/03
UCSRA (MPCM) USART CPU MPCM 5 8 9 9 (RXB8) ( 9 ) 1
MPCM
9 (UCSZ = 7) (TXB8 = 1) 9 (TXB8) 1 (TXB = 0) 9 1. (UCSRA MPCM ) 2. UCSRA RXC 3. UDR UCSRA MPCM MPCM 1 4. MPCM 1 5. MPCM 2 5 8 n n+1 5 8 (USBS = 1) - - (SBI CBI) MPCM MPCM TXC I/O SBI CBI
144
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
UBRRH/ UCSRC
UBRRH UCSRC I/O
USART (URSEL) URSEL 0 UBRRH URSEL 1 UCSRC (1)
... ; UBRRH 2 ldi r16,0x02 out UBRRH,r16 ... ; USBS UCSZ1 1 0 ldi r16,(1<C (1)
... /* UBRRH 2*/ UBRRH = 0x02; ... /* USBS UCSZ1 1 0*/ UCSRC = (1<Note:
1.
I/O
145
2503F-AVR-12/03
UBRRH UCSRC UBRRH I/O UCSRC UCSRC ( ) UCSRC (1)
USART_ReadUCSRC: ; UCSRC in in ret r16,UBRRH r16,UCSRC
C (1)
unsigned char USART_ReadUCSRC( void ) { unsigned char ucsrc; /* UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; }
Note:
1.
r16 UCSRC UBRRH
USART
USART I/O UDR
Bit 7 6 5 4 RXB[7:0] TXB[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 UDR ( ) UDR ( )
USART USART I/O USART UDR UDR (TXB) UDR (RXB) 567 0 UCSRA UDRE UDRE UDR USART TxD FIFO FIFO - - (SBI CBI) (SBIC SBIS) FIFO
146
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
USART A UCSRA
Bit /
7 RXC R 0
6 TXC R/W 0
5 UDRE R 1
4 FE R 0
3 DOR R 0
2 PE R 0
1 U2X R/W 0
0 MPCM R/W 0 UCSRA
* Bit 7 - RXC: USART RXC RXC RXC ( RXCIE ) * Bit 6 - TXC: USART (UDR) TXC TXC 1 TXC ( TXCIE ) * Bit 5 - UDRE: USART UDRE(UDR) UDRE1 UDRE ( UDRIE ) UDRE * Bit 4 - FE: 0 FE (UDR) 1 FE 0 UCSRA 0 * Bit 3 - DOR: DOR ( ) (UDR) UCSRA 0 * Bit 2 - PE: (UPM1 = 1) UPE (UDR) UCSRA 0 * Bit 1 - U2X: 1 16 8 * Bit 0 - MPCM: MPCM USART MPCM P145 " " USART B UCSRB
Bit /
7 RXCIE R/W
6 TXCIE R/W
5 UDRIE R/W
4 RXEN R/W
3 TXEN R/W
2 UCSZ2 R/W
1 RXB8 R
0 TXB8 R/W UCSRB
147
2503F-AVR-12/03
0
0
0
0
0
0
0
0
* Bit 7 - RXCIE: RXC RXCIE 1 SREG UCSRA RXC 1 USART * Bit 6 - TXCIE: TXC TXCIE 1 SREG UCSRA TXC 1 USART * Bit 5 - UDRIE: USART UDRE UDRIE 1 SREG UCSRA UDRE 1 USART * Bit 4 - RXEN: USART RxD USART FE DOR PE * Bit 3 - TXEN: USART TxD USART TXEN TxD I/O * Bit 2 - UCSZ2: UCSZ2UCSRCUCSZ1:0( ) * Bit 1 - RXB8: 8 9 RXB8 9 UDR RXB8 * Bit 0 - TXB8: 8 9 TXB8 9 UDR USART C UCSRC
Bit /
7 URSEL R/W 1
6 UMSEL R/W 0
5 UPM1 R/W 0
4 UPM0 R/W 0
3 USBS R/W 0
2 UCSZ1 R/W 1
1 UCSZ0 R/W 1
0 UCPOL R/W 0 UCSRC
UBRRH/ UCSRC "
UCSRC UBRRH I/O P146 "
* Bit 7 - URSEL: UCSRC UBRRH UCSRC 1 UCSRC URSEL 1
148
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
* Bit 6 - UMSEL: USART Table 63. UMSEL Bit Settings
UMSEL 0 1
149
2503F-AVR-12/03
* Bit 5:4 - UPM1:0: UPM0 UCSRA PE Table 64. UPM
UPM1 0 0 1 1 UPM0 0 1 0 1
* Bit 3 - USBS: Table 65. USBS
USBS 0 1 1 2
* Bit 2:1 - UCSZ1:0: UCSZ1:0UCSRB UCSZ2( ) Table 66. UCSZ
UCSZ2 0 0 0 0 1 1 1 1 UCSZ1 0 0 1 1 0 0 1 1 UCSZ0 0 1 0 1 0 1 0 1 5 6 7 8 9
* Bit 0 - UCPOL: UCPOL XCK Table 67. UCPOL
UCPOL 0 1 (TxD ) XCK XCK (RxD ) XCK XCK
150
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
USART UBRRL UBRRH
Bit
15 URSEL 7
14 - 6 R R/W 0 0
13 - 5 R R/W 0 0
12 -
11
10
9
8 UBRRH UBRRL 0 R/W R/W 0 0
UBRR[11:8] 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0
UBRR[7:0] 4 R R/W 0 0 / R/W R/W 0 0
UBRRH/ UCSRC "
UCSRC UBRRH I/O P146 "
* Bit 15 - URSEL: UCSRC UBRRH UBRRH 0 UBRRH URSEL 0 * Bit 14:12 - UBRRH * Bit 11:0 - UBRR11:0: USART 12 USART UBRRH USART 4 UBRRL 8 UBRRL
151
2503F-AVR-12/03
Table 68 UBRR 0.5% ( P143 " " )
BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate
Table 68. UBRR
fosc = 1.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 1.
(1)
fosc = 1.8432 MHz U2X = 0 UBRR 47 23 11 7 5 3 2 1 1 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - - U2X = 1 UBRR 95 47 23 15 11 7 5 3 2 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% - 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - UBRR 51 25 12 8 6 3 2 1 1 0 - -
fosc = 2.0000 MHz U2X = 0 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - U2X = 1 UBRR 103 51 25 16 12 8 6 3 2 1 - 0 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0% 250 kbps
U2X = 0 UBRR 25 12 6 3 2 1 1 0 - - - - 0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - -
U2X = 1 UBRR 51 25 12 8 6 3 2 1 1 0 - - 125 kbps
62.5 kbps UBRR = 0, = 0.0%
115.2 kbps
230.4 kbps
125 kbps
152
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 69. UBRR ( )
fosc = 3.6864 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 4.0000 MHz U2X = 0 UBRR 103 51 25 16 12 8 6 3 2 1 0 0 - - 250 kbps 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - - U2X = 1 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
fosc = 7.3728 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - U2X = 1 UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
U2X = 0 UBRR 95 47 23 15 11 7 5 3 2 1 0 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
U2X = 1 UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
230.4 kbps UBRR = 0, = 0.0%
460.8 kbps
0.5 Mbps
460.8 kbps
921.6 kbps
153
2503F-AVR-12/03
Table 70. UBRR ( )
fosc = 8.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 11.0592 MHz U2X = 0 UBRR 287 143 71 47 35 23 17 11 8 5 2 2 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 575 287 143 95 71 47 35 23 17 11 5 5 2 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0
fosc = 14.7456 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 1 UBRR 767 383 191 127 95 63 47 31 23 15 7 6 3 1 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8%
U2X = 0 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
U2X = 1 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0
0.5 Mbps UBRR = 0, = 0.0%
1 Mbps
691.2 kbps
1.3824 Mbps
921.6 kbps
1.8432 Mbps
154
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 71. UBRR ( )
fosc = 16.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 18.4320 MHz U2X = 0 UBRR 479 239 119 79 59 39 29 19 14 9 4 4 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 959 479 239 159 119 79 59 39 29 19 9 8 4 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 2.4% -7.8% - 0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0% UBRR 520 259 129 86 64 42 32 21 15 10 4 4 - -
fosc = 20.0000 MHz U2X = 0 0.0% 0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% 1.7% -1.4% 8.5% 0.0% - - U2X = 1 UBRR 1041 520 259 173 129 86 64 42 32 21 10 9 4 - 0.0% 0.0% 0.2% -0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% -1.4% 0.0% 0.0% -
U2X = 0 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0 -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1 Mbps UBRR = 0, = 0.0%
U2X = 1 UBRR 832 416 207 138 103 68 51 34 25 16 8 7 3 1
2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
2.5 Mbps
155
2503F-AVR-12/03
TWI
* * * * * * * * * *
7 128 400 kHz AVR
TWI TWI 128 SCL SDA TWI Figure 76. TWI
VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
TWI
Table 72. TWI
SCL
156
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 76 TWI TWI "0" TWI TWI TWI AVR 400 pF 7 TWI P272 " " 100 kHz 400 kHz
( ) TWI Figure 77.
SDA
SCL Data Stable Data Stable
Data Change
START/STOP
START STOP START STOP START STOP START REPEATED START REPEATED START STOP START START REPEATED START START START STOP SCL SDA Figure 78. START REPEATED START STOP
SDA
SCL
START
STOP START
REPEATED START
STOP
TWI 9 7 1 READ/WRITE 1 READ/WRITE 1 SCL (ACK) SDA ACK SDA STOP REPEATED START SLA+R SLA+W READ WRITE
157
2503F-AVR-12/03
MSB 0000 000 ACK SDA Write ACK SDA Read 1111 xxx Figure 79.
Addr MSB SDA Addr LSB R/W ACK
SCL 1 START 2 7 8 9
TWI 9 8 1 START STOP 9 SCL SDA SDA NACK NACK MSB Figure 80.
Data MSB Aggregate SDA SDA from Transmitter SDA from receiverR SCL from Master 1 SLA+R/W 2 7 Data Byte 8 9 STOP, REPEATED START or Next Data Byte Data LSB ACK

START SLA+R/W STOP START STOP SCL SCL SCL SCL SCL SCL SCL TWI Figure 81 SLA+R/W STOP
158
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 81.
Addr MSB SDA Addr LSB R/W ACK Data MSB Data LSB ACK
SCL 1 START 2 7 SLA+R/W 8 9 1 2 Data Byte 7 8 9 STOP
TWI
*
*
SCL
SCL / SCL / Figure 82. SCL
TA low TA high
SCL from Master A
SCL from Master B
SCL bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period
SDA SDA SDA SDA
159
2503F-AVR-12/03
Figure 83.
START SDA from Master A Master A Loses Arbitration, SDAA SDA
SDA from Master B
SDA Line
Synchronized SCL Line
* * * REPEATED START STOP REPEATED START STOP
SLA+R/W
160
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
TWI
TWI Figure 84 AVR Figure 84. TWI
SCL
Slew-rate Control Spike Filter
SDA
Slew-rate Control Spike Filter
Bus Interface Unit
START / STOP Control Spike Suppression
Bit Rate Generator
Prescaler
Arbitration detection
Address/Data Shift Register (TWDR)
Ack
Bit Rate Register (TWBR)
Address Match Unit
Address Register (TWAR)
Control Unit
Status Register (TWSR) Control Register (TWCR)
TWI Unit
Address Comparator State Machine and Status control
SCL SDA
SCL SDAMCU TWI TWI 50 ns SCL SDA I/O TWI SCL TWI TWSR TWBR TWI CPU TWI SCL 16 SCL TWI SCL CPU Clock frequency SCL frequency = -----------------------------------------------------------TWPS 16 + 2(TWBR) 4 * * TWBR = TWI TWPS = TWI
TWI TWBR 10 SDA SCL TWI Start + SLA + R/W ( )
Note:
TWDRSTART/STOP TWDR 8 TWDR (N)ACK (N)ACK TWI TWCR (N)ACK TWCR
161
2503F-AVR-12/03
START/STOP TWI START REPEATED START STOP MCU START/STOP TWI START/STOP TWI MCU TWI TWI TWAR 7 TWAR TWI TWGCE "1" TWI TWCR MCU MCU TWI TWI TWCR TWI TWI TWINT TWI TWSR TWSR TWINT "1" SCL TWI TWINT * * * * * * * * TWI START/REPEATED START TWI SLA+R/W TWI TWI TWI ( ) TWI TWI STOP REPEATED START START STOP
162
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
TWI
TWI TWBR
Bit / 7 TWBR7 R/W 0 6 TWBR6 R/W 0 5 TWBR5 R/W 0 4 TWBR4 R/W 0 3 TWBR3 R/W 0 2 TWBR2 R/W 0 1 TWBR1 R/W 0 0 TWBR0 R/W 0 TWBR
* Bits 7..0 - TWI TWBR SCL P162 " " TWI TWCR
Bit / 7 TWINT R/W 0 6 TWEA R/W 0 5 TWSTA R/W 0 4 TWSTO R/W 0 3 TWWC R 0 2 TWEN R/W 0 1 - R 0 0 TWIE R/W 0 TWCR
TWCR TWI TWI START STOP TWDR TWDR TWDR * Bit 7 - TWINT: TWI TWI TWINT SREG I TWCR TWIE MCU TWI TWINT SCL TWINT "1" "0" TWI TWINT TWAR TWSR TWDR * Bit 6 - TWEA: TWI TWEA TWEA ACK 1. 2. TWAR TWGCE 3. / TWEA * Bit 5 - TWSTA: TWI START CPU TWSTA TWI START STOP START START TWSTA * Bit 4 - TWSTO: TWI STOP TWSTOTWI STOP TWSTO TWSTO STOP TWI SCL SDA
163
2503F-AVR-12/03
* Bit 3 - TWWC: TWI TWINT TWDR TWWC TWINT TWDR * Bit 2 - TWEN: TWI TWEN TWITWI TWEN"1" TWII/O SCL SDA TWI TWI * Bit 1 - Res: "0" * Bit 0 - TWIE: TWI SREG I TWIE TWINT "1" TWI TWI TWSR
Bit / 7 TWS7 R 1 6 TWS6 R 1 5 TWS5 R 1 4 TWS4 R 1 3 TWS3 R 1 2 - R 0 1 TWPS1 R/W 0 0 TWPS0 R/W 0 TWSR
* Bits 7..3 - TWS: TWI 5 TWI TWSR 5 2 "0" * Bit 2 - Res: "0" * Bits 1..0 - TWPS: TWI / Table 73. TWI
TWPS1 0 0 1 1 TWPS0 0 1 0 1 1 4 16 64
P162 " " TWPS1..0 TWI TWDR
Bit / 7 TWD7 R/W 1 6 TWD6 R/W 1 5 TWD5 R/W 1 4 TWD4 R/W 1 3 TWD3 R/W 1 2 TWD2 R/W 1 1 TWD1 R/W 1 0 TWD0 R/W 1 TWDR
164
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
TWDR TWDR TWI (TWINT ) TWINT TWDR TWDR MCU TWI TWDR ACK TWI CPU ACK * Bits 7..0 - TWD: TWI TWI( ) TWAR
Bit /
7 TWA6 R/W 1
6 TWA5 R/W 1
5 TWA4 R/W 1
4 TWA3 R/W 1
3 TWA2 R/W 1
2 TWA1 R/W 1
1 TWA0 R/W 1
0 TWGCE R/W 0 TWAR
TWAR 7 TWI TWAR TWAR LSB (0x00) * Bits 7..1 - TWA: TWI * Bit 0 - TWGCE: TWI MCU TWI
TWI
AVR TWI START TWI TWI TWI TWCR TWI TWIESREGTWINT TWIE TWINT TWI TWINT "1" TWI TWI TWSR TWI TWCR TWCR TWDR TWI TWI Figure 85 TWI
165
2503F-AVR-12/03
Figure 85. TWI
1. Application writes to TWCR to initiate transmission of START 3. Check TWSR to see if START was sendt. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero 5. Check TWSR to see if SLA+W was sent and ACK received. Application loads data into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one
Application Action
TWI bus
START
SLA+W
A
Data
A
STOP
TWI Hardware Action
2. TWINT set. Status code indicates START condition sent
4. TWINT set. Status code indicates SLA+W sent, ACK received
6. TWINT set. Status code indicates data sent, ACK received
Indicates TWINT set
1. TWI START TWCR TWI START TWINT TWINT "1" TWCR TWINT TWI TWINT TWI START 2. START TWCR TWINT TWCR START 3. TWSR START TWSR SLA+W TWDR TWDR TWDR SLA+W TWCR TWI SLA+W TWINT TWINT "1" TWCR TWINT TWI TWINT TWI 4. TWCR TWINT TWDR 5. TWSRACK TWSR TWDR TWCR TWI TWDR TWINT TWCR TWINT TWI TWINT TWI 6. TWCR TWINT TWSR 7. TWSR ACK TWSR TWCR TWI STOP TWINT TWINT "1" TWCR TWINT TWI TWINT TWI STOP TWINT STOP TWI * TWI TWINT TWINT SCL
166
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
* * TWINT TWI TWI TWDR TWI TWCR TWCR TWINT TWINT "1" TWI TWCR
C
1
ldi out r16, (1<C
TWCR = (1< START
2
wait1: in sbrs r16,TWINT rjmp wait1
TWINT TWINT START
3
in cpi ldi out ldi out
r16,TWSR r16, START r16, SLA_W TWDR, r16 r16, (1<if ((TWSR & 0xF8) != START) ERROR();
andi r16, 0xF8 brne ERROR
TWI START
TWDR = SLA_W; TWCR = (1< SLA_W TWDR TWINT
4
wait2: in r16,TWCR sbrs r16,TWINT rjmp wait2
while (!(TWCR & (1< TWINT TWINT SLA+W ACK/NACK TWI MT_SLA_ACK
5
in cpi ldi out ldi out
r16,TWSR r16, MT_SLA_ACK r16, DATA TWDR, r16 r16, (1<if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR();
andi r16, 0xF8 brne ERROR
TWDR = DATA; TWCR = (1< TWDR TWINT
6
wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3
while (!(TWCR & (1< TWINT TWINT DATA ACK/NACK
7
in cpi ldi out
r16,TWSR r16, MT_DATA_ACK r16, (1<andi r16, 0xF8 brne ERROR
if ((TWSR & 0xF8) != MT_DATA_ACK) TWI ERROR(); MT_DATA_ACK
TWCR = (1< STOP
167
2503F-AVR-12/03
TWI 4 (MT) (MR) (ST) (SR) TWI MT TWI EEPROM MR EEPROM TWI SR S START RsREPEATED START R (SDA ) W (SDA ) A (SDA ) A (SDA ) Data8 P STOP SLA Figure 87 Figure 93 TWINT TWSR 0 / TWI TWI TWINT TWINT TWSR Table 74 Table 77 0
Figure 86 START MT MR SLA+W MT SLA+R MR "0" Figure 86.
VCC
Device 1
MASTER TRANSMITTER
Device 2
SLAVE RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN TWSTA"1"START TWINT "1" TWINT TWI START TWINT TWSR 0x08 ( Table 74) MT 168
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
SLA+W TWDR SLA+W TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+W TWINT TWSR 0x18 0x20 0x38 Table 74 SLA+W TWDR TWDR TWINT TWCR TWWC TWDR TWINT TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START TWCR
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
REPEATED START ( 0x10) STOP REPEATED START Table 74.
(TWSR) "0"
$08
TWCR 2 2 START START / TWDR SLA+W SLA+W SLA+R STA
0
STO
0
TWIN T
1
TWE A
X
2 SLA+W ACK NOT ACK SLA+W ACK NOT ACK SLA+R
$10
0 0
0 0
1 1
X X
$18
SLA+W ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO
$20
SLA+W NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
169
2503F-AVR-12/03
Table 74.
$28
ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO
$30
NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
$38
SLA+W
TWDR TWDR
0 1
0 0
1 1
X X
2 START
Figure 87.
MT
Successfull transmission to a slave receiver
S
SLA
W
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$18
$28
RS
SLA
W
$10
Not acknowledge received after the slave address
A
P
R
$20
MR
Not acknowledge received after a data byte
A
P
$30
Arbitration lost in slave address or data byte
A or A
Other master continues
A or A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
170
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 88 START MT MR SLA+W MT SLA+R MR "0" Figure 88.
VCC
Device 1
MASTER RECEIVER
Device 2
SLAVE TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN TWSTA"1"START TWINT "1" TWINT TWI START TWINT TWSR 0x08 ( Table 74) MR SLA+R TWDR SLA+R TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+R TWINT TWSR 0x380x40 0x48 Table 75 TWDR TWINT MR NACK STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START TWCR
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
REPEATED START ( 0x10) STOP REPEATED START Table 75.
(TWSR) "0" TWCR 2 2 / TWDR STA STO TWIN T TWE A 2
171
2503F-AVR-12/03
Table 75. (Continued)
$08
START START
SLA+R SLA+R SLA+W
0
0
1
X
SLA+R ACK NOT ACK SLA+R ACK NOT ACK SLA+W
$10
0 0
0 0
1 1
X X
$38
SLA+R NOT ACK SLA+R ACK SLA+R NOT ACK
TWDR TWDR
0 1
0 0 0 0 0 1 1
1 1 1 1 1 1 1
X X 0 1
2 START NOT ACK ACK
$40
TWDR TWDR
0 0
$48
TWDR TWDR TWDR
1 0 1
X X X
START STOP TWSTO STOP START TWSTO
$50
ACK NOT ACK

0 0
0 0 0 1 1
1 1 1 1 1
0 1
NOT ACK ACK
$58

1 0 1
X X X
START STOP TWSTO STOP START TWSTO
172
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 89.
MR
Successfull reception from a slave receiver
S
SLA
R
A
DATA
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$40
$50
$58
RS
SLA
R
$10
Not acknowledge received after the slave address
A
P
W
$48
MT
Arbitration lost in slave address or data byte
A or A
Other master continues
A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
Figure 90 "0" Figure 90.
VCC
Device 1
SLAVE RECEIVER
Device 2
MASTER TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
173
2503F-AVR-12/03
7 TWI LSB TWI 0x00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) 0 ( ) TWINT TWSR Table 76 TWI ( 0x68 0x78) CPU TWEA TWI SDA " " TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVRTWI AVR SCL MCU TWDR
174
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 76.
(TWSR) "0"
$60
TWCR 22 SLA+W ACK SLA+R/W SLA+W ACK ACK SLA+R/W ACK SLA+W ACK SLA+W NOT ACK / TWDR TWDR TWDR STA
X X
STO
0 0 0 0
TWIN T
1 1 1 1
TWE A
0 1
2 NOT ACK ACK
$68
TWDR TWDR TWDR TWDR
X X
0 1
NOT ACK ACK
$70
X X
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 1
NOT ACK ACK
$78
TWDR TWDR TWDR TWDR
X X X X 0 0 1
0 1
NOT ACK ACK
$80
0 1 0 1 0
NOT ACK ACK SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
$88
1 0 1 1
175
2503F-AVR-12/03
Table 76. (Continued)
$90
ACK NOT ACK
r
X X 0 0 1
0 0 0 0 0
1 1 1 1 1
0 1
NOT ACK ACK
$98
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
1 0 1 1
$A0
STOP START
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
1
0
1
1
176
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 91.
Reception of the own slave address and one or more data bytes. All are acknowledged
S
SLA
W
A
DATA
A
DATA
A
P or S
$60
Last data byte received is not acknowledged
$80
$80
$A0
A
P or S
$88
Arbitration lost as master and addressed as slave
A
$68
Reception of the general call address and one or more data bytes
General Call
A
DATA
A
DATA
A
P or S
$70
Last data byte received is not acknowledged
$90
$90
$A0
A
P or S
$98
Arbitration lost as master and addressed as slave by general call
A
$78
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
Figure 92 "0" Figure 92.
VCC
Device 1
SLAVE TRANSMITTER
Device 2
MASTER RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
177
2503F-AVR-12/03
7 TWI LSB TWI 0x00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) "1" ( ) TWI TWSR Table 77 TWI ( 0xB0) CPU TWEA TWI 0xC0 0xC8 "1" ( ACK) 0xC8 TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVR AVR SCL MCU TWDR
178
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 77.
(TWSR) "0"
$A8
TWCR 22 SLA+R ACK / TWDR STA
X X
STO
0 0
TWIN T
1 1
TWE A
0 1
2 NOT ACK ACK
$B0
SLA+R/W SLA+R ACK TWDR ACK

X X
0 0
1 1
0 1
NOT ACK ACK
$B8
X X
0 0
1 1
0 1
NOT ACK ACK
$C0
TWDR NOT ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
TWDR
1 0 1 1
TWDR
$C8
TWDR (TWAE = "0"); ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
TWDR
1 0 1 1
TWDR
179
2503F-AVR-12/03
Figure 93.
Reception of the own slave address and one or more data bytes
S
SLA
R
A
DATA
A
DATA
A
P or S
$A8
Arbitration lost as master and addressed as slave
$B8
$C0
A
$B0
Last data byte transmitted. Switched to not addressed slave (TWEA = '0')
A
All 1's
P or S
$C8
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
TWI Table 78 0xF8 TWINT "0" TWI 0x00 START STOP ACKSTARTSTOP TWINT TWSTO "1" TWINT TWI TWSTO (TWCR ) SDA SCL STOP
Table 78.
(TWSR) "0"
$F8
TWCR 2 2 TWINT = "0" START STOP / TWDR TWDR TWDR
0
STA
STO
TWIN T
TWE A
2
No TWCR action
$00
1
1
X
STOP TWSTO
180
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
TWI TWI EEPROM 1. 2. EEPROM 3. 4. MT MR EEPROM REPEATED START REPEATED START Figure 94. TWI EEPROM
Master Transmitter Master Receiver
S
SLA+W
A
ADDRESS
A
Rs
SLA+R
A
DATA
A
P
S = START Transmitted from Master to Slave
Rs = REPEATED START Transmitted from Slave to Master
P = STOP
TWI Figure 95.
VCC
Device 1
MASTER TRANSMITTER
Device 2
MASTER TRANSMITTER
Device 3
SLAVE RECEIVER
........
Device n
R1
R2
SDA
SCL
* * READ/WRITE SDA "0" START
181
2503F-AVR-12/03
*
SLA SDA "0" SLA SR ST SLA READ/WRITE START
Figure 96 TWI Figure 96.
START SLA Data STOP
Arbitration lost in SLA
Arbitration lost in Data
Own Address / General Call received
No
38
TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free
Yes Write 68/78
Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned
Direction
Read B0
Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received
182
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure 97 Figure 97. (2)
BANDGAP REFERENCE ACBG
ACME ADEN ADC MULTIPLEXER OUTPUT (1)
Notes:
1. P185 Table 80 2. P2 Figure 1 P55 Table 25
IO SFIOR
Bit / 7 ADTS2 R/W 0 6 ADTS1 R/W 0 5 ADTS0 R/W 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 3 - ACME: "1" ADC (ADCSRA ADEN "0") ADC "0" AIN1 P186 " "
183
2503F-AVR-12/03
ACSR
Bit /
7 ACD R/W 0
6 ACBG R/W 0
5 ACO R N/A
4 ACI R/W 0
3 ACIE R/W 0
2 ACIC R/W 0
1 ACIS1 R/W 0
0 ACIS0 R/W 0 ACSR
* Bit 7 - ACD: ACD ACD ACSR ACIE ACD * Bit 6 - ACBG: ACBG AIN0 P39 " " * Bit 5 - ACO: ACO 1-2 * Bit 4 - ACI: ACIS1 ACIS0 ACI ACIE SREG I ACI ACI "1" * Bit 3 - ACIE: ACIE "1" I * Bit 2 - ACIC: ACIC T/C1 T/C1 ACIC "0" T/C1 TIMSK TICIE1
184
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
* Bits 1, 0 - ACIS1, ACIS0: Table 79 Table 79. ACIS1/ACIS0
ACIS1 0 0 1 1 ACIS0 0 1 0 1
ACIS1/ACIS0 ACSR
ADC7..0 ADC ADC (SFIOR ACME) ADC (ADCSRA ADEN 0) ADMUX MUX2..0 Table 80 ACME ADEN AIN1 Table 80.
ACME 0 1 1 1 1 1 1 1 1 1 ADEN x 1 0 0 0 0 0 0 0 0 MUX2..0 xxx xxx 000 001 010 011 100 101 110 111 AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
185
2503F-AVR-12/03
* * * * * * * * * * * * * * *
10 0.5 LSB 2 LSB 65 - 260 s 15 kSPS 8 7 2 10x 200x (1) ADC 0 - VCC ADC 2.56V ADC ADC ADC 1. PDIP TQFP MLF
Note:
ATmega3210ADC ADC8 A 8 0V (GND) 16 (ADC1 ADC0 ADC3 ADC2) A/D 0 dB (1x) 20 dB (10x) 46 dB (200x) (ADC1) ADC 1x 10x 8 200x 7 ADC ADC ADC Figure 98 ADCAVCC AVCCVCC 0.3V P193 "ADC " 2.56V AVCC AREF
186
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 98.
ADC CONVERSION COMPLETE IRQ
INTERRUPT FLAGS ADTS[2:0]
8-BIT DATA BUS
ADIF ADIE
15 ADC DATA REGISTER (ADCH/ADCL)
ADPS0 ADC[9:0]
0
ADC MULTIPLEXER SELECT (ADMUX)
MUX3 MUX1 REFS1 ADLAR REFS0 MUX4 MUX2 MUX0
ADC CTRL. & STATUS REGISTER (ADCSRA)
ADATE ADPS2 ADPS1 ADEN
ADSC
ADIF
TRIGGER SELECT MUX DECODER
CHANNEL SELECTION
PRESCALER
GAIN SELECTION
START
CONVERSION LOGIC
AVCC
INTERNAL 2.56V REFERENCE AREF
10-BIT DAC
SAMPLE & HOLD COMPARATOR +
GND
BANDGAP REFERENCE
ADC7
SINGLE ENDED / DIFFERENTIAL SELECTION
ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 + POS. INPUT MUX
ADC MULTIPLEXER OUTPUT
GAIN AMPLIFIER
NEG. INPUT MUX
ADC 10 GND AREF 1 LSB ADMUX REFSn AVCC 2.56V AREF AREF ADMUX MUX ADC GND ADC ADC ADC ADCSRA ADEN ADC ADEN ADEN ADC ADC
187
2503F-AVR-12/03
ADC10 ADCADCHADCL ADMUX ADLAR 8 ADCH ADCL ADCH ADCL ADC ADCL ADCH ADC ADCH ADC ADCH ADCL ADC ADCHADCLADC
ADC ADSC "1" ADC ADC ADCSRAADCADATE ADCSRB ADC ADTS ( ADTS ) ADC 0 Figure 99. ADC
ADTS[2:0] PRESCALER
START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE
CLKADC
CONVERSION LOGIC EDGE DETECTOR
ADC ADC ADC ADC ADCSRA ADSC 1 ADC ADC ADIF ADCSRA ADSC ADSC ADSC 1
188
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ADC
Figure 100. ADC
ADEN START CK Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
50 kHz 200 kHz 10 200 kHz ADC 100 kHz CPU ADC ADCSRA ADPS ADCSRA ADEN ADC ADEN 1 ADEN ADCSRAADSC ADC P192 " " 13 ADC ADC (ADCSRA ADEN ) 25 ADC ADC 1.5 ADC ADC 13.5 ADC ADC ADC ADIF ADSC ( ) ADSC ADC 2 ADC 3 CPU ADC 25 ADC ADC ADSC 1 Table 81
CK/128
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
189
2503F-AVR-12/03
Figure 101. ADC ( )
First Conversion Next Conversion
Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
MSB of Result LSB of Result
MUX and REFS Update
Sample & Hold
Conversion Complete
MUX and REFS Update
Figure 102. ADC
One Conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 Next Conversion 1 2 3
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
Figure 103. ADC
One Conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 Next Conversion 1 2
Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL
MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset
Prescaler Reset
190
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 104. ADC
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
Table 81. ADC
& ( ) 14.5 1.5 2 1.5/2.5 ( ) 25 13 13.5 13/14
CKADC2 ADC ADC CKADC2 CKADC2 ( ) ( 13 ADC ) CKADC2 14 ADC CKADC2 ( ) 14 ADC 4 kHz ADC ADC 6 s 12 kSPS ADC ADC ADC ( ADCSRA ADEN "0" "1") ADC P190 " ADC "
ADMUXMUXnREFS1:0 CPU ADC (ADCSRA ADIF ) ADSC 191
2503F-AVR-12/03
ADSC ADC ADMUX ADMUX ADATE ADEN ADMUX ADMUX 1. ADATE ADEN 0 2. ADC 3. ADMUX ADC 125 s 125 s ADC ( ADMUX REFS1:0 ) ADC ADSC ADC ADSC ADC ADC ADC(VREF)ADC VREF 0x3FF VREF AVCC 2.56V AREF AVCCADC 2.56V(VBG) AREF ADC AREF VREF AREF VREF AREF AREF AVCC 2.56V ADC P273 Table 122 AVCC
ADC
ADC CPUI/O ADC 1. ADC ADC 2. ADC ( ) CPU ADC
192
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
3. ADC ADCCPU ADC ADC CPU ADC ADC CPU ADC ADC ADEN ADC ADC Figure 105. ADC ADCn ADC ( ) (S/H) ADC10 k S/H S/H k (fADC/2) ADC Figure 105.
IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2
(EMI) 1. 2. Figure 106 AVCC LC VCC 3. ADC CPU 4. ADC
193
2503F-AVR-12/03
Figure 106. ADC
Analog Ground Plane
PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
GND
PA3 (ADC3)
VCC
1LSB n ADC GND VREF 2n (LSBs) 0 2n-1 * (0x000 0x001) (0.5 LSB) 0 LSB
ADC
194
ATmega32(L)
2503F-AVR-12/03
100nF
10H
ATmega32(L)
Figure 107.
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
*
(0x3FE 0x3FF) ( 1.5 LSB) 0 LSB
Figure 108.
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
*
(INL) INL0 LSB
195
2503F-AVR-12/03
Figure 109. (INL)
Output Code
*
(DNL) ( ) (1 LSB) 0 LSB
INL
Ideal ADC Actual ADC
VREF
Input Voltage
Figure 110. (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* *
(1 LSB) 0.5 LSB ( ) 0.5 LSB
196
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ADC
(ADIF ) ADC (ADCL, ADCH) V IN 1024 ADC = -------------------------V REF VIN VREF ( P198 Table 83 P199 Table 84 ) 0x000 0x3FF 1LSB ( V POS - V NEG ) GAIN 512 ADC = --------------------------------------------------------------------------V REF
VPOS VNEG GAIN VREF 2 0x200 (-512d) 0x1FF (+511d) MSB( ADCH ADC9 ) 1 0 Figure 111 Table 82 GAIN VREF (ADCn - ADCm) Figure 111.
Output Code 0x1FF
0x000 - V REF/GAIN 0x3FF 0 VREF/GAIN Differential Input Voltage (Volts)
0x200
197
2503F-AVR-12/03
Table 82.
VADCn VADCm + VREF/GAIN VADCm + 0.999 VREF/GAIN VADCm + 0.998 VREF/GAIN ... VADCm + 0.001 VREF/GAIN VADCm VADCm - 0.001 VREF/GAIN ... VADCm - 0.999 VREF/GAIN VADCm - VREF/GAIN 0x1FF 0x1FF 0x1FE ... 0x001 0x000 0x3FF ... 0x201 0x200 511 511 510 ... 1 0 -1 ... -511 -512
ADMUX = 0xED (ADC3 - ADC2 10x 2.56V ) ADC3 300 mV ADC2 500 mV ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ADCL 0x00 ADCH 0x9C ADLAR 0 ADCL = 0x70ADCH = 0x02 ADC ADMUX
Bit / 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX
* Bit 7:6 - REFS1:0: Table 83 (ADCSRA ADIF ) AREF Table 83. ADC
REFS1 0 0 1 1 REFS0 0 1 0 1 AREF Vref AVCC AREF 2.56V AREF
*
Bit 5 - ADLAR: ADC
ADLARADCADC ADLAR ADLAR ADC P202 "ADC -ADCL ADCH"
198
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
* Bits 4:0 - MUX4:0: ADC Table 84 (ADCSRA ADIF ) Table 84.
MUX4..0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010(1) 01011
(1)
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
N/A
ADC0 ADC1 ADC0 ADC1 ADC2 ADC3 ADC2 ADC3 ADC0 ADC1 N/A ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 1.22 V (VBG) 0 V (GND) N/A
ADC0 ADC0 ADC0 ADC0 ADC2 ADC2 ADC2 ADC2 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2
10x 10x 200x 200x 10x 10x 200x 200x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x
01100 01101 01110(1) 01111
(1)
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
199
2503F-AVR-12/03
Note:
1. PDIP TQFP MLF
ADC A ADCSRA
Bit /
7 ADEN R/W 0
6 ADSC R/W 0
5 ADATE R/W 0
4 ADIF R/W 0
3 ADIE R/W 0
2 ADPS2 R/W 0
1 ADPS1 R/W 0
0 ADPS0 R/W 0 ADCSRA
* Bit 7 - ADEN: ADC ADENADC ADC ADC * Bit 6 - ADSC: ADC ADSC ADC ADSC ( ADC ADSC ADC ADSC) 25 ADC 13 ADC ADSC "1"ADSC * Bit 5 - ADATE: ADC ADATE ADC ADC SFIOR ADC ADTS * Bit 4 - ADIF: ADC ADC ADIF ADIE SREG I ADC ADIF 1 ADIF ADCSRA SBI CBI * Bit 3 - ADIE: ADC ADIE SREG I ADC * Bits 2:0 - ADPS2:0: ADC XTAL ADC Table 85. ADC
ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 2 2 4 8 16 32 64 128
200
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ADC ADCL ADCH ADLAR = 0
Bit 15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
ADLAR = 1
Bit 15 ADC9 ADC1 7 R R 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL
ADC 2 ADCL ADC ADCH 8 ADCH ADCL ADCH ADMUX ADLAR MUXn ADLAR 1 ( ) * ADC9:0: ADC ADC P198 "ADC " IO SFIOR
Bit / 7 ADTS2 R/W 0 6 ADTS1 R/W 0 5 ADTS0 R/W 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 7:5 - ADTS2:0: ADC ADCSRA ADATE ADTS ADC ADTS ADC
201
2503F-AVR-12/03
ADCSRA ADEN 1 ADC (ADTS[2:0]=0) ADC Table 86. ADC
ADTS2 0 0 0 0 1 1 1 1 ADTS1 0 0 1 1 0 0 1 1 ADTS0 0 1 0 1 0 1 0 1 0 / 0 / 0 / B / 1 / 1
* Bit 4 - Res: 0
202
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
JTAG OCD(On-chip Debug)
* IEEE 1149.1 JTAG * IEEE 1149.1 (JTAG) *
- - SRAM - - - EEPROM Flash - OCD - AVR Break - - - - * JTAG Flash EEPROM * AVR Studio(R) OCD
IEEE 1149.1 AVR JTAG * * * JTAG PCB OCD
JTAG JTAG P256 " JTAG " P210 "IEEE 1149.1 (JTAG) " OCD JTAG ATMEL ATMEL JTAGICE Figure 112JTAGOCDTAPTCKTMS TAP JTAG TDI( ) TDO( ) ( ) JTAG ID (Bypass) JTAG ( ) OCD
TAP
JTAG JTAG TAP * * * * TMS TAP TCK JTAG TCK TDI -- ( ) TDO --
ATmega32 IEEE 1149.1 TAP TRST - Test ReSeT JTAGEN TAP TAP JTAGEN MCUCSR JTD TAP JTAG TAP (TDO) JTAG TAP ( TDI ) 203
2503F-AVR-12/03
JTAG RESET ( ) RESET Figure 112.
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI TDO TCK TMS
TAP CONTROLLER
JTAG PROGRAMMING INTERFACE
AVR CPU INSTRUCTION REGISTER ID REGISTER M U X BYPASS REGISTER FLASH MEMORY Address Data INTERNAL SCAN CHAIN PC Instruction
BREAKPOINT UNIT
ANALOG PERIPHERIAL UNITS
DIGITAL PERIPHERAL UNITS
BREAKPOINT SCAN CHAIN ADDRESS DECODER JTAG / AVR CORE COMMUNICATION INTERFACE
OCD STATUS AND CONTROL
I/O PORT n
204
ATmega32(L)
2503F-AVR-12/03
Control & Clock lines
Analog inputs
FLOW CONTROL UNIT
ATmega32(L)
Figure 113. TAP
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
TAP
TAP 16 JTAG Figure 113 TCK TMS( ) Test-Logic-Reset LSB Run-Test/Idle( - / ) JTAG * TCK TMS 1, 1, 0, 0 - ShiftIR TCK TDI 4 JTAG JTAG 3 LSB TMS Shift-IR MSBTMSShift-IRJTAG TDI IR 0x01 TDO JTAG TDI TDO 205
2503F-AVR-12/03
*
TMS 1, 1, 0Run-Test/IdleUpdate-IR Exit-IR, Pause-IR, Exit2-IR TCK TMS 1, 0, 0 - Shift-DR TDI TCK ( JTAG JTAG ) Shift-DR TMS MSB TMS Shift-IR MSB TDI Capture-DR TDO TMS 1, 1, 0 Run-Test/Idle Update-DR Exit-IR, Pause-IR, Exit2-IR
*
*
JTAG Run-Test/Idle JTAG Run-Test/Idle
Note: TMS TCK TAP Test-Logic-Reset TAP
JTAG P209 " "

P210 "IEEE 1149.1 (JTAG) " Figure 112 * * * AVR CPU CPU JTAG
/ AVR CPU AVR CPU I/O CPU JTAG * * * * * ( ) ( )
AVR Studio JTAG P208 " JTAG " JTAGEN JTAG OCDEN AtmelAVR JTAG ICEIEEE 1149.1 JTAGAVR8 JTAG ICE AVR Studio
206
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
JTAG ICE AVR JTEG ICE www.atmel.com AVR Support Tools Software AVR Studio AVR Studio BREAK ( )
JTAG
PRIVATE0; $8 PRIVATE1; $9 PRIVATE2; $A PRIVATE3; $B
JTAG ATMEL ATMEL JTAG JTAG JTAG JTAG
207
2503F-AVR-12/03
I/O
OCDR
Bit / 7 MSB/IDRD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 OCDR
OCDR CPU I/O - IDRD - CPU OCDR 7 LSB OCDR MSB IDRD IDRD AVR I/O OCDEN OCDR MCU OCDR MCU I/O
JTAG
JTAG AVR JTAG --TCK, TMS, TDI TDO() 12V JTAG JTAGEN MCUCR JTD JTAG * * * * Flash EEPROM
LB1 LB2 OCDEN JTAGJTAGP256 "JTAG"
* * IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993 Colin Maunder: The Board Designers Guide to Testable Logic Circuits, AddisonWesley, 1992
208
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
IEEE 1149.1 (JTAG)
* * * * *
JTAG ( IEEE std. 1149.1 ) JTAG IDCODE AVR AVR_RESET
I/O JTAG IC TDI/TDO TAP IEEE 1149.1 JTAG IDCODE BYPASS SAMPLE/PRELOAD EXTEST AVR JTAG AVR_RESET IDCODE JTAG ID AVR HIGHZ BYPASS RESET AVR_RESET EXTEST EXTEST JTAG IR SAMPLE/PRELOAD EXTEST SAMPLE/PRELOAD TAGEN I/O MCUCR JTD JTAG JTAG JTAG TCK
* * * * (Bypass)
TDI TDO Capture-DR 0 Figure 114 Figure 114.
MSB Bit ID 31 4 bits 28 27 16 bits 12 11 ID 11 bits 1 LSB 0 1 1 bit
209
2503F-AVR-12/03
* Table 87 Table 87. JTAG
ATmega32 A 0x0 JTAG (Hex)
* 16 Table 88 ATmega32 JTAG Table 88. AVR JTAG
ATmega32 0x9502 JTAG (Hex)
* ID ID 11 Table 89 ATMEL JTAG ID Table 89. ID
ATMEL 0x01F JTAG ID (Hex)
AVR JTAG HIGHZ ( P23 " " ) Figure 115 Figure 115.
To TDO
From other Internal and External Reset Sources From TDI Internal Reset
D
Q
ClockDR * AVR_RESET
I/O P214 " "
210
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
JTAG
4 16 JTAG AVR HIGHZ AVR_RESET LSB OPCODE hex TDI TDO EXTEST; $0 EXTEST JTAG AVR JTAG IR EXTEST * * * IDCODE; $1 Capture-DR Shift-DR TCK Update-DR
IDCODEJTAG 32ID ID JEDEC IDCODE * * Capture-DR IDCODE Shift-DR TCK IDCODE
SAMPLE_PRELOAD; $2
SAMPLE_PRELOADJTAG / * * * Capture-DR Shift-DR TCK Update-DR
AVR_RESET; $C
AVR_RESETAVRJTAG AVRJTAG TAP 1 * Shift-DR TCK
BYPASS; $F
BYPASS JTAG * * Capture-DR 0 Shift-DRTDI TDO
211
2503F-AVR-12/03
I/O
MCU MCUCSR MCU MCU MCU
Bit / 7 JTD R/W 0 6 ISC2 R/W 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUCSR
* Bit 7 - JTD: JTAG 0 JTAGEN JTAG 1 JTAG JTAG JTD JTD JTAG JTAG JTD JTAG TDO * Bit 4 - JTRF: JTAG JTAG AVR_RESET JTAG 1 JTRF 0 JTRF
212
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
I/O Figure 116 - PUExn - - OCxn - ODxn - IDxn Figure 117 P47 "I/O " Figure 117 Figure 116 - ID - PINxn ( ID ) PORT - DD - PUExn - PUD * DDxn * PORTxn Figure 117 Figure 116. .
ShiftDR To Next Cell EXTEST Vcc
Pullup Enable (PUE) FF2 0 D 1 G Q D Q LD2
0 1
Output Control (OC) FF1 0 D 1 G Q D Q LD1 0 1
Output Data (OD)
0 1 0
FF0 D 1 Q
LD0 D G Q
0 Port Pin (PXn) 1
Input Data (ID)
From Last Cell
ClockDR
UpdateDR
213
2503F-AVR-12/03
Figure 117. (1)
PUExn
PUD
Q
D
DDxn
Q CLR
OCxn
RESET
WDx
RDx
Pxn
Q
D
ODxn IDxn SLEEP
PORTxn
Q CLR
WPx RESET RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn
L
Q
Q
CLK I/O
PUD: PUExn: OCxn: ODxn: IDxn: SLEEP:
PULLUP DISABLE PULLUP ENABLE for pin Pxn OUTPUT CONTROL for pin Pxn OUTPUT DATA to pin Pxn INPUT DATA from pin Pxn SLEEP CONTROL
WDx: RDx: WPx: RRx: RPx: CLK I/O :
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN I/O CLOCK
Note:
1.
TWI
SCL SDA - TWIEN Figure 118 TWIEN Figure 122
Notes: 1. 50ns TWIEN 2. OC TWIEN
214
ATmega32(L)
2503F-AVR-12/03
DATA BUS
ATmega32(L)
Figure 118.
PUExn
OCxn ODxn
Pxn
TWIEN
SRC
Slew-rate Limited IDxn
RESET
RESET5V12V Figure 119 5V RSTT 12V RSTHV Figure 119.
To Next Cell
ShiftDR
From System Pin
To System Logic
FF1
0 D 1 Q
From Previous Cell
ClockDR
AVR RC RC ( ) Figure 120 / RC
215
2503F-AVR-12/03
Figure 120.
XTAL1/TOSC1 XTAL2/TOSC2
From Digital Logic
ShiftDR
To Next Cell
EXTEST
Oscillator
ENABLE OUTPUT
0 1 0 D 1 G Q D Q 0 D 1 Q
FF1
From Previous Cell
ClockDR
UpdateDR From Previous Cell ClockDR
Table 90 XTAL1 XTAL1/XTAL2 32 kHz Table 90. (1)(2)(3)
EXTCLKEN OSCON RCOSCEN OSC32EN TOSKON Notes: EXTCLK (XTAL1) OSCCK RCCK OSC32CK TOSCK RC 32 kHz 0 0 1 0 0
1. 2. JTAG TCK 3. INTCAP XTAL
Figure 121 Figure 122 Table 91
216
ATmega32(L)
2503F-AVR-12/03
To System Logic
ShiftDR
To Next Cell
ATmega32(L)
Figure 121.
BANDGAP REFERENCE ACBG
ACO
AC_IDLE
ACME ADCEN ADC MULTIPLEXER OUTPUT
Figure 122. ADC
To Next Cell
ShiftDR
EXTEST
From Digital Logic/ From Analog Ciruitry 0 D 1 G Q D Q
0 1
To Analog Circuitry/ To Digital Logic
From Previous Cell
ClockDR
UpdateDR
217
2503F-AVR-12/03
Table 91.
AC_IDLE ACO ACME ACBG '1' '1' ADC 1 C 0 0 C 0 C C
ADC Figure 123 ADC Figure 122 ADC Figure 123.
VCCREN
AREF
IREFEN
To Comparator
2.56V ref
MUXEN_7 ADC_7 MUXEN_6 ADC_6 MUXEN_5 ADC_5 MUXEN_4 ADC_4
PASSEN
SCTEST
ADCBGEN
EXTCH MUXEN_3 ADC_3 MUXEN_2 ADC_2 MUXEN_1 ADC_1 MUXEN_0 ADC_0 NEGSEL_2
ADC_2
1.22V ref
PRECH
PRECH AREF
AREF
DACOUT
DAC_9..0
10-bit DAC + COMP
G10
+
G20 ACTEN
+
-
ADCEN
10x
-
20x
-
HOLD GNDEN
NEGSEL_1
ADC_1
NEGSEL_0
ADC_0
ST ACLK AMPEN
Table 92
218
ATmega32(L)
2503F-AVR-12/03
COMP
ATmega32(L)
Table 92. ADC
COMP ACLK ACTEN ADCBGEN ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH G10 G20 GNDEN HOLD ADC ADC DAC 9 DAC 8 DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 ADC 0 - 3 10x 20x '1' & '0' '1' ACLK DAC AREF 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 CPU ADC 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1
IREFEN MUXEN_7 MUXEN_6 MUXEN_5 MUXEN_4 MUXEN_3 MUXEN_2 MUXEN_1

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
219
2503F-AVR-12/03
Table 92. ADC (Continued)
MUXEN_0 NEGSEL_2 NEGSEL_1 NEGSEL_0 PASSEN PRECH SCTEST ST ADC 0 2 1 0 ( ) TEST 10x ADC_4 AMPEN ACLK Vcc ADC 1 0 0 0 1 1 0 0 CPU ADC 1 0 0 0 1 1 0 0
VCCREN Note:
0
0
Figure 123 Figure 123 S&H ADC
ADC Table 92 AVR ADC Figure 123 : DAC[9:0] DAC[9:0] ADC ADC * * * ADC ADC""(10) ADC 200ns " " HOLD ( ) DAC 0x200
5.0V AREF VCC ADC 3 1.5V 5%
The lower limit is: The upper limit is: 1024 1,5V 0,95 5V = 291 = 0x123 1024 1,5V 1,05 5V = 323 = 0x143
Table 93 Table 92 Table 93 DAC " " JTAG
220
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 93. ADC
ADCEN DAC MUXEN HOLD PRECH PA3. PA3. PA3.
1
SAMPLE _PRELO AD EXTEST
1
0x200
0x08
1
1
0
0
0
2 3 4 5 6
1 1 1 1
0x200 0x200 0x123 0x123 0x200
0x08 0x08 0x08 0x08 0x08
0 1 1 1 1
1 1 1 0 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
COMP 0
1
7 8 9 10 11
COMP 1
1 1 1 1 1
0x200 0x200 0x143 0x143 0x200
0x08 0x08 0x08 0x08 0x08
0 1 1 1 1
1 1 1 0 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
HOLD TCK 5 HOLD TCK 5 thold,max
221
2503F-AVR-12/03
ATmega32
TDI TDO Table 94 Bit 0 LSB ( / ) A Figure 116 PXn.Data FF0 PXn.Control FF1 PXn. Pullup_enable FF2 C 2 4 3 5 JTAG TAP Table 94. ATmega32
140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 AC_IDLE ACO ACME ACBG COMP PRIVATE_SIGNAL1 ACLK ACTEN PRIVATE_SIGNAL2(2) ADCBGEN ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH G10 G20 GNDEN HOLD IREFEN
(1)

ADC
222
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 94. ATmega32 (Continued)
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 MUXEN_7 MUXEN_6 MUXEN_5 MUXEN_4 MUXEN_3 MUXEN_2 MUXEN_1 MUXEN_0 NEGSEL_2 NEGSEL_1 NEGSEL_0 PASSEN PRECH SCTEST ST VCCREN PB0.Data PB0.Control PB0.Pullup_Enable PB1.Data PB1.Control PB1.Pullup_Enable PB2.Data PB2.Control PB2.Pullup_Enable PB3.Data PB3.Control PB3.Pullup_Enable PB4.Data PB4.Control PB4.Pullup_Enable B ADC
223
2503F-AVR-12/03
Table 94. ATmega32 (Continued)
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 PB5.Data PB5.Control PB5.Pullup_Enable PB6.Data PB6.Control PB6.Pullup_Enable PB7.Data PB7.Control PB7.Pullup_Enable RSTT RSTHV EXTCLKEN OSCON RCOSCEN OSC32EN EXTCLK (XTAL1) OSCCK RCCK OSC32CK TWIEN PD0.Data PD0.Control PD0.Pullup_Enable PD1.Data PD1.Control PD1.Pullup_Enable PD2.Data PD2.Control PD2.Pullup_Enable PD3.Data PD3.Control PD3.Pullup_Enable PD4.Data PD4.Control PD4.Pullup_Enable TWI D ( ) ( ) / B
224
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 94. ATmega32 (Continued)
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 PD5.Data PD5.Control PD5.Pullup_Enable PD6.Data PD6.Control PD6.Pullup_Enable PD7.Data PD7.Control PD7.Pullup_Enable PC0.Data PC0.Control PC0.Pullup_Enable PC1.Data PC1.Control PC1.Pullup_Enable PC6.Data PC6.Control PC6.Pullup_Enable PC7.Data PC7.Control PC7.Pullup_Enable TOSC TOSCON PA7.Data PA7.Control PA7.Pullup_Enable PA6.Data PA6.Control PA6.Pullup_Enable PA5.Data PA5.Control PA5.Pullup_Enable PA4.Data PA4.Control PA4.Pullup_Enable A 32 kHz C D
225
2503F-AVR-12/03
Table 94. ATmega32 (Continued)
11 10 9 8 7 6 5 4 3 2 1 0 Notes: PA3.Data PA3.Control PA3.Pullup_Enable PA2.Data PA2.Control PA2.Pullup_Enable PA1.Data PA1.Control PA1.Pullup_Enable PA0.Data PA0.Control PA0.Pullup_Enable 1. PRIVATE_SIGNAL1 0 2. PRIVATE_SIGNAL2 0 A
(BSDL) BSDL ATmega32
226
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
(RWW, Read-WhileWrite)
Boot Loader MCU - (ReadWhile-Write RWW) MCU Flash Boot Loader Boot Loader ( ) Flash Boot Loader Flash Boot Loader Boot Loader Boot Loader Boot Loader * * * * * * *
RWW Boot Loader ( Boot ) (1) RWW 1. Flash ( P243 Table 111 )
Note:
Flash Flash Boot Loader ( Figure 125) BOOTSZ P237 Table 100 Figure 125 Flash
Flash Boot (Boot 0) P230 Table 96 SPM Boot Loader Boot Loader BLS BLS SPM SPM Flash BLS Boot Loader Boot Loader (Boot 1) P230 Table 97 CPU RWW CPU Boot Loader BOOTSZ Flash ---- - (RWW) - (NRWW) RWW NRWW P237 Table 101 P229 Figure 125 * RWW NRWW NRWW CPU Boot Loader RWW "RWW " ( ) Boot Loader RWW Boot Loader RWW Flash NRWW Flash RWW RWW ( call/jmp/lpm ) Boot Loader Boot Loader NRWW RWW (SPMCSR) RWW RWWSB RWW RWWSB RWWSB P232 " -SPMCR"
(Boot Loader Section) BLS
RWW Flash RWW Flash
227
2503F-AVR-12/03
RWW NRWW
Boot Loader RWW NRWW Boot Loader NRWW CPU Table 95. RWW
Z ? RWW NRWW ? NRWW CPU ? RWW ?
Figure 124. RWW NRWW
Read-While-Write (RWW) Section
Z-pointer Addresses RWW Section
Z-pointer Addresses NRWW Section
No Read-While-Write (NRWW) Section
CPU is Halted during the Operation Code Located in NRWW Section Can be Read during the Operation
228
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 125. (1)
Program Memory BOOTSZ = '11' $0000
Read-While-Write Section Read-While-Write Section
Program Memory BOOTSZ = '10' $0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00'
Boot Loader Flash Section
End Application Start Boot Loader Flashend
Program Memory BOOTSZ = '01' $0000
Read-While-Write Section Read-While-Write Section
$0000
Application Flash Section
Application flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend
No Read-While-Write Section
End RWW, End Application Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
Note:
1. P237 Table 100
Boot Loader Flash Boot Loader Boot * * * * Flash MCU MCU Boot Loader Flash MCU Flash MCU Flash
Table 96 Table 97Boot ( 2) SPM Flash / ( 1) LPM/SPM Flash /
229
2503F-AVR-12/03
Table 96. Boot 0 ( )(1)
BLB0 Mode 1 2 BLB02 1 1 BLB01 1 0 SPM/LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader
3
0
0
4 Note:
0
1
1. "1" "0"
Table 97. Boot 1 (Boot Loader )(1)
BLB1 mode 1 2 BLB12 1 1 BLB11 1 0 SPM/LPM Boot Loader SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader
3
0
0
4 Note:
0
1
1. "1" "0"
Boot Loader USART SPI Boot Boot Boot Loader MCU Boot Boot
230
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 98. Boot (1)
BOOTRST 1 0 Note: = ( 0x0000) =Boot Loader ( P237 Table 100 )
1. "1" , "0"
SPMCR
SPMCR Boot Loader
Bit / 7
SPMIE
6
RWWSB
5
-
4
RWWSRE
3
BLBSET
2
PGWRT
1
PGERS
0
SPMEN SPMCR
R/W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - SPMIE: SPM SPMIE I SPM SPMCSR SPMEN SPM * Bit 6 - RWWSB: RWW RWW ( ) RWWSB 1 RWWSB RWW RWWSRE 1 RWWSB RWWSB * Bit 5 - Res: ATmega32 "0" * Bit 4 - RWWSRE: RWW RWW() RWW(RWWSB"1") (SPMEN)RWW RWWSRE SPMEN"1" SPMRWW Flash (SPMEN ),RWW Flash RWWSRE Flash * Bit 3 - BLBSET: Boot SPMEN SPM R0 Boot R1 Z SPM BLBSET SPMCSR BLBSET SPMEN LPM ( Z Z0) P236 " " * Bit 2 - PGWRT: SPMEN SPM Flash Z R1 R0 SPM PGWRT NRWW CPU
231
2503F-AVR-12/03
* Bit 1 - PGERS: SPMEN SPM Z R1 R0 SPM PGERS NRWW CPU * Bit 0 - SPMEN: SPM RWWSRE BLBSET PGWRT PGERS SPM SPMEN SPM R1:R0 Z LSB Z SPM SPM SPMEN SPMEN 1 "10001" "01001" "00101" "00011" "00001"
Flash
Z SPM
Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Flash (see P243 Table 111 ) Figure 126 Boot Loader Z Z SPM Boot Loader Z LPM Z Z LSB ( Z0)
232
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 126. SPM (1)
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. Figure 126 P238 Table 102
Flash
SPM 1 * * * * * *
2
( ) Flash 1 Boot Loader - Flash 2 P237 " " SPM Z RAMPZ "X0000011" SPMCSR SPMR1 R0 Z PCPAGE Z * * RWW NRWW NRWW CPU
233
2503F-AVR-12/03
( )
Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE
Note: EEPROM SPM
Z RAMPZ "X0000101" SPMCSR SPMR1 R0 Z PCPAGE Z * * RWW NRWW NRWW CPU
SPM
SPM SPMCSR SPMEN SPMCSR SPM BLS RWW P42 " " Boot 11 Boot Loader Boot Loader Boot Loader Boot Loader Boot 11 Boot Loader ( ) RWW RWW SPMCSR RWWSB P42 " " BLS RWW RWWSRE 1 RWWSB P237 " " Boot Loader R0 "X0001001"SPMCSR SPM Boot Loader MCU Boot Loader
BLS
RWW
SPM
234
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Bit R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1
Boot Loader Flash Table 96 Table 97 R0 5..2 0 SPMCSR BLBSET SPMEN SPM Boot Z Z 0x0001( lOck ) R0 7 6 1 0 "1" Flash EEPROM SPMCR EEPROM Flash SPMCR EECR EEWE 0x0001 Z SPMCSRBLBSET SPMEN SPMCSRCPU LPM CPU LPM CPU SPM BLBSET SPMEN BLBSET SPMEN LPM
Bit Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1
0x0000ZSPMCRBLBSET SPMEN SPMCSR CPU LPM (FLB) P240 Table 106
Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
0x0003 Z SPMCR BLBSET SPMEN SPMCSR CPU LPM (FHB) P240 Table 105
Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
"0" "1" Flash VCC CPU Flash Flash Flash Flash Flash CPU Flash ( ) 1. Boot Loader Boot Loader Boot Loader 2. AVR RESET BOD 3. AVR CPU SPMCR Flash 235
2503F-AVR-12/03
SPM Flash
RC Flash Table 99 CPU Flash Table 99. SPM
Flash ( SPM ) 3.7 ms 4.5 ms
;- RAM Flash ; Y RAM ;Z Flash ;- ;- Boot ( Do_spm ) ; ( ) NRWW ;- r0 r1 temp1 (r16) temp2 (r17) looplo (r24) ; loophi (r25) spmcrval (r20) ; ; ;- Boot loader , .equ PAGESIZEB = PAGESIZE*2 ; PAGESIZEB .org SMALLBOOTSTART Write_page: ; ldi spmcrval, (1<; ;PAGESIZEB<=256
;PAGESIZEB<=256 subi
; subi ZL, low(PAGESIZEB) ; sbci ZH, high(PAGESIZEB) ;PAGESIZEB<=256 ldi spmcrval, (1<; ;PAGESIZEB<=256 ;
236
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
jmp Error sbiw loophi:looplo, 1 brne Rdloop ;PAGESIZEB<=256 subi
; RWW ; RWW Return: in temp1, SPMCR sbrs temp1, RWWSB ; RWWSB "1" RWW ret ; RWW ldi spmcrval, (1<ATmega32
Table 100 Table 102 Table 100. Boot (1)
Boot 256 512 1024 2048 Boot Loader Flash $3F00 $3FFF $3E00 $3FFF $3C00 $3FFF $3800 $3FFF Boot ( Boot Loader ) $3F00 $3E00 $3C00 $3800
BOOTSZ1 1 1 0 0
BOOTSZ0 1 0 1 0
4 8 16 32
Flash $0000 $3EFF $0000 $3DFF $0000 $3BFF $0000 $37FF
$3EFF $3DFF $3BFF $37FF
Note:
1. BOOTSZ Figure 125
Table 101. RWW (1)
Flash - (RWW) - (NRWW) 224 32 $0000 - $37FF $3800 - $3FFF
237
2503F-AVR-12/03
Note:
1. P229 " RWW -NRWW" P228 "RWW "
Table 102. Figure 126 Z
PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD Note: PC[13:6] PC[5:0] 13 5 Z14 Z6 Z14:Z7 Z6:Z1 Z (1) ( 14 PC[13:0]) ( 64 6 PC [5:0]) Z PCMSB Z0 ZPCMSB PCMSB + 1 Z PAGEMSB Z0 ZPAGEMSB PAGEMSB + 1 ( 0)
1. Z15: Z0 SPM "0" LPM Z P233 " Flash"
238
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ATmega32 6 ("0") ("1") Table 104 "1" Table 103. (1)
7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 Note: 5 4 3 2 1 0 - - Boot Boot Boot Boot 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
1. "1" "0"
Table 104.
(2) LB 1 2 3 BLB0 1 2 LB2 1 1 0 BLB02 1 1 LB1 1 0 0 BLB01 1 0 SPM LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader SPM/LPM Boot Loader SPI/JTAGFlashEEPROM (1) SPI/JTAGFlashEEPROM (1)
3
0
0
4 BLB1 1
0 BLB12 1
1 BLB11 1
239
2503F-AVR-12/03
Table 104. (Continued)
(2) 2 1 0 SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader
3
0
0
4 Notes:
0
1
1. 2. "1" , "0"
ATmega32 Table 105 - Table 106 "0" Table 105.
OCDEN
(4) (5)
7 6 5 4 3 2 1 0
OCD JTAG EEPROM Boot ( Table 100 ) Boot ( Table 100 )
1 ( OCD ) 0 ( JTAG ) 0 ( SPI ) 1 ( ) 1 ( )EEPROM 0 ( )(3) 0 ( )(3) 1 ( )
JTAGEN SPIEN(1) CKOPT
(2)
EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes: 1. 2. 3. 4.
SPI SPIEN CKOPT CKSEL P23 " " BOOTSZ1..0 Boot P237 Table 100 JTAGEN OCDEN OCDEN 5. JTAG JTAGEN JTAG TDO
Table 106.
BODLEVEL BODEN SUT1 SUT0 CKSEL3 7 6 5 4 3 BOD BOD 1 ( ) 1 ( BOD ) 1 ( )(1) 0 ( )(1) 0 ( )(2)
240
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 106.
CKSEL2 CKSEL1 CKSEL0 Notes: 2 1 0 0 ( )(2) 0 ( )(2) 1 ( )(2)
1. SUT1..0 P28 Table 10 2. CKSEL3..0RC1 MHz P23 Table 2
1(LB1) EESAVE Atmel ATmega32 1. 0x000: 0x1E ( Atmel ) 2. 0x001: 0x95 ( 32 KB Flash ) 3. 0x002: 0x02 ( 0x001 0x95 ATmega32)
ATmega32 RC 0x000 0x0001 0x0002 0x0003 1 2 4 8 MHz 1 MHz OSCCAL P28 " -OSCCAL"
241
2503F-AVR-12/03
ATmega32 Flash EEPROM 250 ns
ATmega32 Figure 127 Table 107 XA1/XA0 XTAL1 Table 109 WR OE Table 110 Figure 127.
+5V RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RESET PA0 XTAL1 GND AVCC
PB7 - PB0
VCC +5V
DATA
Table 107.
RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA PAGEL XA1 XA0 BS1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PA0 PB7-0 I/O O I I I I I I I I/O 0: , 1: ( ). ( ). 1("0" , "1" ). XTAL 0 XTAL 1 EEPROM 2("0" , "1" ) (OE ) Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0
Table 108.
242
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 109. XA1 XA0
XA1 0 0 1 1 XA0 0 1 0 1 XTAL1 Flash EEPROM ( BS1 ) ( BS1 )
Table 110.
1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Flash EEPROM Flash EEPROM
Table 111. Flash
Flash 16K (32K ) 64 PCWORD PC[5:0] 256 PCPAGE PC[13:6] PCMSB 13
Table 112. EEPROM
EEPROM 1024 4 PCWORD EEA[1:0] 256 PCPAGE EEA[9:2] EEAMSB 9
243
2503F-AVR-12/03
1. VCC GND 4.5 - 5.5V 2. RESET XTAL1 6 3. P242 Table 108 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable RC XTAL1 1. P242 Table 108 Prog_enable "0000" 2. VCC GND 4.5 - 5.5V RESET 11.5 - 12.5V 3. 100 ns 4. (CKSEL3:0 = 0b0000) 5. RESET 0b0 6. * * * 0xFF Flash EEPROM( EESAVE ) Flash EEPROM 256
Flash EEPROM(1) Flash / EEPROM
Note: 1. EESAVE EEPRPOM
" " 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY Flash Flash P243 Table 111 Flash Flash A. " Flash" 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "0001 0000" Flash 4. XTAL1 B. 244
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
1. XA1 XA0 "00" 2. BS1 "0" 3. DATA (0x00 - 0xFF) 4. XTAL1 C. 1. XA1 XA0 "01" 2. DATA (0x00 - 0xFF) 3. XTAL1 D. 1. BS1 "1" 2. XA1 XA0 "01" 3. DATA (0x00 - 0xFF) 4. XTAL1 E. 1. BS1 "1" 2. PAGEL ( Figure 129 ) F. B E FLASH P246 Figure 128 8 ( < 256) G. 1. XA1 XA0 "00" 2. BS1 "1" 3. DATA (0x00 - 0xFF) 4. XTAL1 H. 1. BS1 = "0" 2. WR RDY/BSY 3. RDY/BSY ( Figure 129 ) I. B H Flash J. 1. 1. XA1 XA0 "10" 2. DATA "0000 0000" 3. XTAL1
245
2503F-AVR-12/03
Figure 128. Flash
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE PCWORD P243 Table 111
Figure 129. Flash (1)
F
A
DATA
$10
B
C
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
ADDR. LOW DATA LOW
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1. "XX" Flash
246
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
EEPROM P243 Table 112 EEPROM EEPROM EEPROM ( P245 " Flash " ) 1. A "0001 0001" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. C (0x00 - 0xFF) 5. E ( PAGEL ) K 3 5 L EEPROM 1. BS1 "0" 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure 130 ) Figure 130. EEPROM
K
A
DATA
0x11
G
B
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
ADDR. HIGH ADDR. LOW
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Flash
Flash ( P245 " Flash " ) 1. A "0000 0010" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA Flash 5. BS1 "1" DATA Flash 6. OE "1"
EEPROM
( P245 " Flash " )
247
2503F-AVR-12/03
1. A "0000 0011" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA EEPROM 5. OE "1" ( P245 " Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "0" BS2 "0" 4. WR RDY/BSY ( P245 " Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "1" BS2 "0" 4. WR RDY/BSY 5. BS1 "0" Figure 131.
Write Fuse Low byte A
DATA
$40
Write Fuse high byte A C
DATA XX
C
DATA XX
$40
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
( P245 " Flash " ) 1. A "0010 0000" 2. C n "0" 3. WR RDY/BSY
248
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
( P245 " Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 "0" DATA ("0" ) 3. OE"0" BS2BS1"1" DATA("0") 4. OE "0" BS2 "0" BS1 "1" DATA ("0" ) 5. OE "1" Figure 132. BS1 BS2
Fuse Low Byte
0 DATA
Lock Bits
0 1
BS1 Fuse High Byte BS2
( P245 " Flash " ) 1. A "0000 1000" 2. B 0x00 - 0x02 3. OE BS1 "0" DATA 4. OE "1" ( P245 " Flash " ) 1. A "0000 1000" 2. B 3. OE "0" BS1 "1" DATA 4. OE "1" Figure 133.
t XLWL XTAL1 t DVXH Data & Contol (DATA, XA0/1, BS1, BS2) t BVPH PAGEL WR RDY/BSY t WLRH t PHPL t WL t PLWL
WLRL WH
1
t XHXL t XLDX
t PLBX
t BVWL
t WLBX
249
2503F-AVR-12/03
Figure 134. (1)
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA LOAD DATA (HIGH BYTE)
tXLPH tPLXH
LOAD ADDRESS (LOW BYTE)
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 133 (tDVXH tXHXL tXLDX)
Figure 135. ( )(1)
LOAD ADDRESS (LOW BYTE)
tXLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 133 ( tDVXH tXHXL tXLDX)
Table 113. VCC = 5 V 10%
VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH tPLXH XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR XTAL1 PAGEL XTAL1 PAGEL 67 200 150 67 0 0 150 11.5 12.5 250 V A ns ns ns ns ns ns ns
250
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 113. VCC = 5 V 10% (Continued)
tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: PAGEL XTAL1 PAGEL BS1 PAGEL PAGEL BS1 WR BS2/1 PAGEL WR BS1 WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY (2) XTAL1 OE BS1 DATA OE DATA OE DATA 1. Flash EEPROM tWLRH 2. tWLRH_CE 67 150 67 67 67 67 150 0 3.7 7.5 0 0 250 250 250 1 4.5 9 ns ns ns ns ns ns ns s ms ms ns ns ns ns
SPI
RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P251 Table 114 SPI SPI SPI
SPI
Table 114.
MOSI MISO SCK PB5 PB6 PB7 I/O I O I
251
2503F-AVR-12/03
Figure 136. SPI (1)
+2.7 - 5.5V VCC +2.7 - 5.5V(2) MOSI MISO SCK PB5 PB6 PB7 XTAL1 AVCC
RESET
GND
Notes:
1. XTAL1 2. VCC -0.3V < AVCC < VCC +0.3V AVCC 2.7 - 5.5V
EEPROM MCU EEPROM 0xFF CKSEL (SCK) fck < 12 MHz 2 CPU fck 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck 12 MHz 3 CPU > SPI ATmega32 SCK ATmega32 SCK Figure 137 ATmega32 ( Table 116 4 ) 1. RESET SCK "0" VCC GND SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. (0x53) 4 0x53 RESET 4. Flash 6 LSB 7 tWD_FLASH ( Table 115) Flash
252
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
5. EEPROM EEPROM tWD_EEPROM ( Table 115) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC Flash Flash 0xFF Flash 0xFF 0xFF tWD_FLASH 0xFF 0xFF tWD_FLASH Table 115 EEPROM 0xFF 0xFF 0xFF 0xFF EEPROM 0xFF tWD_EEPROM tWD_EEPROM Table 115 Table 115. Flash EEPROM
tWD_FLASH tWD_EEPROM tWD_ERASE 4.5 ms 9.0 ms 9.0 ms
EEPROM
Figure 137. SPI
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
253
2503F-AVR-12/03
Table 116. SPI
1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx 00aa aaaa 00xx xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxbb bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM a:b o EEPROM a:b i "0" "1" P239 Table 103 "0" P239 Table 103 b o. "0" "1" P240 Table 106 "0" "1" P240 Table 105 "0" "1" P240 Table 106 "0" "1" P240 Table 105
EEPROM EEPROM Note:
0100 1100 1010 0000 1100 0000 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 0101 0000 0101 1000 0011 1000
00aa aaaa 00xx xxaa 00xx xxaa 0000 0000 111x xxxx 00xx xxxx 1010 0000 1010 1000 0000 0000 0000 1000 00xx xxxx
bbxx xxxx bbbb bbbb bbbb bbbb xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000
xxxx xxxx oooo oooo iiii iiii xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii oooo oooo oooo oooo oooo oooo
a = b = H =0 - 1 - o = i = x =
SPI
SPI P273 "SPI " JTAG 4 JTAG :TCKTMSTDI TDOreset JTAG JTAGEN MCUCSR JTD JTD 1 reset JTD JTAG JTAG I/O ISP JTAG JTAG LSB /
JTAG
JTAG
4 16 JTAG OPCODE 16 TDI TDO
254
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
TAPRun-Test/Idle JTAG Figure 138 Figure 138.
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
AVR_RESET ($C)
AVR_RESETAVRJTAG AVR TAP 1 1 * Shift-DR TCK
PROG_ENABLE ($4)
PROG_ENABLEAVRJTAG JTAG 16 * * Shift-DR Update-DR
255
2503F-AVR-12/03
PROG_COMMANDS ($5)
AVR JTAG JTAG 15 * * * * Capture-DR Shift-DR TCK Update-DR Flash Run-Test/Idle ( Table 117 )
PROG_PAGELOAD ($6)
AVRJTAG JTAGFlash1024 Flash 8 JTAG Update-DR Shift-DR Flash * Shift-DR Flash TCK TDI , 1
JTAG PROG_PAGELOAD AVR JTAG
Note:
PROG_PAGEREAD ($7)
AVRJTAG JTAGFlash 1032 Flash Flash 8 8 JTAG Capture-DR Shift-DR Flash * Shift-DR Flash 1 TCK TDO TDI
JTAG PROG_PAGEREAD AVRJTAG
Note:
JTAG P256 " JTAG " * * * * * Flash Flash
256
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
0 0 ( P23 " " ) P210 Figure 115 16 ( 1010_0011_0111_0000) JTAG Figure 139.
TDI
D A T A
$A370
=
D
Q
Programming Enable
ClockDR & PROG_ENABLE
TDO
15 JTAG Table 117 Figure 141
257
2503F-AVR-12/03
Figure 140.
TDI
S T R O B E S
A D D R E S S / D A T A
Flash EEPROM Fuses Lock Bits
TDO
258
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 117. JTAG
1a.
a = , b = , H = 0 - , 1 - , o = , i = , x = TDI 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 0110011_10000000 0100011_00010000 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0010111_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0100011_00000010 0000111_aaaaaaaa 0000011_bbbbbbbb 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00010001 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000011 0000111_aaaaaaaa TDO xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (9) (1) (9) (9) (1) (9) (2)
1b. 2a. Flash 2b. 2c. 2d. 2e. 2f.
2g. Flash
(1)
2h. 3a. Flash 3b. 3c. 3d.
(2)
4a. EEPROM 4b. 4c. 4d. 4e.
4f. EEPROM
(1)
4g. 5a. EEPROM 5b.
(2)
259
2503F-AVR-12/03
Table 117. JTAG (Continued)
5c. 5d.
a = , b = , H = 0 - , 1 - , o = , i = , x = TDI 0000011_bbbbbbbb 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 0100011_01000000 0010011_iiiiiiii 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0010011_iiiiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00100000 0010011_11iiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000100 0111110_00000000 0111111_00000000 0110010_00000000 0110011_00000000 0110110_00000000 0110111_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00001000 0000011_bbbbbbbb 0110010_00000000 0110011_00000000 TDO xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo (5) (5) (4) (1) (3) (1)
6a. 6b.
(6)
6c.
6d. 6e. (7) 6f.
(2) (3) (1)
6g. 7a. 7b. 7c.
(9)
(2)
7d. 8a. / 8b.
(6)
(2)
8c. (7) 8d. (8) 8e.
9a. 9b. 9c.
260
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 117. JTAG (Continued)
10a. 10b. 10c. 11a. Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. a = , b = , H = 0 - , 1 - , o = , i = , x = TDI 0100011_00001000 0000011_bbbbbbbb 0110110_00000000 0110111_00000000 0100011_00000000 0110011_00000000 TDO xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx
( ) 7 MSB o = "1". "0" = "1" = "0" = "1" = "0" = "1" = P240 Table 105 P240 Table 106 P239 Table 103 PCMSB EEAMSB(Table 111 Table 112)
261
2503F-AVR-12/03
Figure 141. /
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
Flash
Flash Flash 8 Flash LSB MSB Flash
262
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 142. Flash
STROBES
TDI
State Machine
ADDRESS
Flash EEPROM Fuses Lock Bits
D A T A
TDO
Flash
Flash Flash 8 8 Flash 8 LSB MSB Flash Figure 143. Flash
STROBES
TDI
State Machine
ADDRESS
Flash EEPROM Fuses Lock Bits
D A T A
TDO
263
2503F-AVR-12/03

"1a" "1b" Table 117 1. JTAG AVR_RESET 1 Reset 2. PROG_ENABLE 1010_0011_0111_0000
1. JTAG PROG_COMMANDS 2. 11a 3. PROG_ENABLE 0000_0000_0000_0000 4. JTAG AVR_RESET 0 Reset
1. JTAG PROG_COMMANDS 2. 1a 3. 1b tWLRH_CE( P250 Table 113 )
Flash
Flash P266 " " 1. JTAG PROG_COMMANDS 2. 2a Flash 3. 2b 4. 2c 5. 2d 2e 2f 6. 4 5 7. 2g 8. 2h Flash tWLRH( P250 Table 113 ) 9. 3 7 PROG_PAGELOAD 1. JTAG PROG_COMMANDS 2. 2a Flash 3. 2b 2c PCWORD( P243 Table 111 ) 0 4. JTAG PROG_PAGELOAD 5. LSB MSB 6. JTAG PROG_COMMANDS 7. 2g 8. 2h Flash tWLRH ( P250 Table 113 ). 9. 3 8
264
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Flash 1. JTAG PROG_COMMANDS 2. 3a Flash 3. 3b 3c 4. 3d 5. 3 4 PROG_PAGEREAD 1. JTAG PROG_COMMANDS 2. 3a Flash 3. 3b3cPCWORD ( P243 Table 111 ) 0 4. JTAG PROG_PAGEREAD 5. LSB MSB 6. JTAG PROG_COMMANDS 7. 3 6 EEPROM EEPROM P266 " " 1. JTAG PROG_COMMANDS 2. 4a EEPROM 3. 4b 4. 4c 5. 4d 4e 6. 4 5 7. 4f 8. 4gEEPROM tWLRH(P250 Table 113 ) 9. 3 8 EEPROM PROG_PAGELOAD EEPROM 1. JTAG PROG_COMMANDS 2. 5a EEPROM 3. 5b 5c 4. 5d 5. 3 4 EEPROM PROG_PAGEREAD
265
2503F-AVR-12/03
1. JTAG PROG_COMMANDS 2. 6a 3. 6b 0 4. 6c 5. 6d tWLRH( P250 Table 113 ) 6. 6e 0 1 7. 6f 8. 6g tWLRH( P250 Table 113 )
1. JTAG PROG_COMMANDS 2. 7a 3. 7b 0 4. 7c 5. 7d tWLRH( P250 Table 113 )
1. JTAG PROG_COMMANDS 2. 8a / 3. 8e 8b 8c 8d
1. JTAG PROG_COMMANDS 2. 9a 3. 9b 0x00 4. 9c 5. 0x01 0x02 3 4
1. JTAG PROG_COMMANDS 2. 10a 3. 10b 0x00 4. 10c
266
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
*
........................................................ -55C +125C ........................................................ -65C +150C RESET............ -0.5V VCC+0.5V RESET .................................. -0.5V +13.0V .................................................................... 6.0V I/O ......................................... 40.0 mA *NOTICE: " "
VCC GND ................................ 200.0 mA
TA = -40C 85C, VCC = 2.7V 5.5V ( )
VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST Rpu ( A,B,C,D)
(3)
XTAL1 XTAL1 XTAL1 RESET XTAL1 RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V VCC = 5.5V, ( ) VCC = 5.5V, ( )
-0.5 -0.5 0.6 VCC(2) 0.7 VCC(2) 0.9 VCC
(2)
0.2 VCC 0.1 VCC
(1) (1)
V V V V V V V V V
VCC + 0.5 VCC + 0.5 VCC + 0.5 0.7 0.5
(4) ( A,B,C,D) I/O I/O Reset I/O
4.0 2.2 1 1 30 20 60 50
A A k k
267
2503F-AVR-12/03
TA = -40C 85C, VCC = 2.7V 5.5V ( )
1 MHz, VCC = 3V (ATmega32L) 4 MHz, VCC = 3V (ATmega32L) 8 MHz, VCC = 5V (ATmega32) 1 MHz, VCC = 3V (ATmega32L) 4 MHz, VCC = 3V (ATmega32L) 8 MHz, VCC = 5V (ATmega32) (5) VACIO IACLK tACID Notes: 1. 2. 3. WDT , VCC = 3V WDT , VCC = 3V VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 -50 1.1 3.8 12 0.35 1.2 5.5 < 25 <1 2.5 8 20 10 40 50 5 15 mA mA mA mA mA mA A A mV nA
ICC
4.
750 VCC = 2.7V ns 500 VCC = 4.0V " " " " ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V PDIP 1] IOL 400 mA 2] A0 - A7 IOL 200 mA 3] B0 - B7,C0 - C7, D0 - D7 XTAL2 IOL 300 mA TQFP MLF 1] IOL 400 mA 2] A0 - A7 IOL 200 mA 3] B0 - B4 IOL 200 mA 4] B3 - B7, XTAL2, D0 - D2 IOL 200 mA 5] D3 - D7 IOL 200 mA 6] C0 - C7 IOL 200 mA IOL VOL ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V PDIP 1] IOH 400 mA 2] A0 - A7 IOH 200 mA 3] B0 - B7,C0 - C7, D0 - D7 XTAL2 IOH 300 mA TQFP MLF 1] IOH 400 mA 2] A0 - A7 IOH 200 mA 3] B0 - B4 IOH 200 mA 4] B3 - B7, XTAL2, D0 - D2 IOH 200 mA 5] D3 - D7 IOH 200 mA
268
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
6] C0 - C7 IOH 200 mA IOH VOH 5. VCC 2.5V
Figure 144.
V IH1 V IL1
Table 118.
VCC = 2.7V - 5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 125 50 50 1.6 1.6 2 8 VCC = 4.5V - 5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s %
tCLCL
Table 119. RC (VCC = 5V)
R [k](1) 100 33 10 Notes: C [pF] 47 22 22 f(2) 87 kHz 650 kHz 2.0 MHz
1. R 3 k - 100 k 20 pF C C C 2.
269
2503F-AVR-12/03
Table 120 ATmega32 Figure 145 Table 120.
VIL VIH Vhys(1) VOL tr(1) tof(1) tSP(1) Ii Ci(1) fSCL
(1)
SDA SCL VIHmin VILmax I/O I/O SCL
-0.5 0.7 VCC 0.05 VCC(2) 3 mA sink current 0 20 + 0.1Cb
(3)(2) (3)(2)
0.3 VCC VCC + 0.5 - 0.4 300 250 50(2) 10 10 400 1000ns -----------------Cb 300ns --------------Cb - - - - - - - - 3.45 0.9 - - - - - -
V V V V ns ns ns A pF kHz s s s s s s s s s s ns ns s s s s
10 pF < Cb < 400 pF
(3)
20 + 0.1Cb 0 -10 -
0.1VCC < Vi < 0.9VCC fCK(4) > max(16fSCL, 250kHz) fSCL 100 kHz
(5)
0 V CC - 0,4V ----------------------------3mA V CC - 0,4V ----------------------------3mA 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7 1.3
Rp
fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz
(6) (7)
tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Notes: 1. 2. 3. 4.
START ( ) SCL SCL STARTS STOP
fSCL > 100 kHz
fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz
STOP START
ATmega32 100% fSCL > 100 kHz Cb = fCK = CPU
270
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
5. ATmega32 fSCL 6. ATmega32 (1/fSCL - 2/fCK) fSCL = 100 kHz fCK 6 MHz 7. ATmega32 (1/fSCL - 2/fCK) fCK = 8 MHz fSCL > 308 kHz ATmega32 ATmega32 (400 kHz) tLOW
Figure 145.
tof tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tHIGH tLOW tr
tBUF
SPI
Figure 146 Figure 147 Table 121. SPI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SCK SCK / / SCK SCK SCK SS SCK SCK / / SCK SCK SS SS SS SCK 2 * tck 20 10 10 tck 15 ns 4 * tck 2 * tck 1.6 s Table 58 50% 3.6 10 10 0.5 * tSCK 10 10 15 ns
271
2503F-AVR-12/03
Figure 146. SPI ( )
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
Figure 147. SPI ( )
18
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
272
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 122. ADC TA = -40C 85C
VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 1 MHz ( INL, DNL, , Gain, ) VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 1 MHz VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 200 kHz 50 13 VCC - 0.3 2.0 GND 0 38.5 2.3 2.56 32 100 2.7
(1)
10 1.5
Bits LSB
3
LSB
1.5
LSB
3
LSB
0.75
LSB

0.25
LSB
0.75
LSB
AVCC VREF VIN ADC VINT RREF RAIN Notes: 1. AVCC 2.7V. 2. AVCC 5.5V.
0.75 1000 260 VCC + 0.3 AVCC VREF 1023
(2)
LSB kHz s V V V LSB kHz V k M
273
2503F-AVR-12/03
Table 123. ADC TA = -40C 85C
Gain = 1x Gain = 10x Gain = 200x Gain = 1x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 10x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 1x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz INL( ) Gain = 10x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 1x Gain = 10x Gain = 200x Gain = 1x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 10x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz Gain = 200x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz AVCC VREF VIN VDIFF ADC 50 65 VCC - 0.3(1) 2.0 GND -VREF/Gain -511 4 17 10 10 10 Bits Bits Bits LSB
16
LSB
7
LSB
0.75
LSB
0.75
LSB
2 1.6 1.5 0.2 1
LSB % % % LSB
1.5
LSB
4.5 200 260 VCC + 0.3(2) AVCC - 0.5 VCC VREF/Gain/ 511
LSB kHz s V V V V LSB kHz
274
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Table 123. ADC TA = -40C 85C (Continued)
VINT RREF RAIN Notes: 1. AVCC 2.7V. 2. AVCC 5.5V. 2.3 2.56 32 100 2.7 V k M
5.
275
2503F-AVR-12/03
ATmega32
I/O I/O CL*VCC*f CL VCC f Figure 148. RC (Vcc = 5V T=25c 1 MHz)
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
1.03 1.02 1.01 1 0.99
FRc (MHz) Vcc = 5.5V Vcc = 5.0V Vcc = 4.5V Vcc = 4.0V Vcc = 3.6V Vcc = 3.3V Vcc = 3.0V Vcc = 2.7V
0.98 0.97 0.96 0.95 0.94 0.93 0.92 -40 -20 0 20
Ta(C)
40
60
80
276
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 149. RC (Vcc = 5V T=25c 1 MHz )
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
1.03 1.02 1.01 1 0.99
FRc (MHz) TA = 85C TA = -40C TA = -10C TA = 25C TA = 45C TA = 70C
0.98 0.97 0.96 0.95 0.94 0.93 0.92 2.5 3 3.5 4
Vcc(V)
4.5
5
5.5
Figure 150. RC (Vcc = 5V T=25c 2 MHz)
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
2.1
2.05
2
Vcc = 5.5V FRc (MHz) Vcc = 5.0V Vcc = 4.5V
1.95
1.9
Vcc = 4.0V Vcc = 3.6V Vcc = 3.3V Vcc = 3.0V Vcc = 2.7V
1.85
1.8 -40 -20 0 20
Ta(C)
40
60
80
277
2503F-AVR-12/03
Figure 151. RC (Vcc = 5V T=25c 2 MHz )
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
2.1
2.05
TA = -40C TA = -10C TA = 25C TA = 45C TA = 70C TA = 85C
2
FRc (MHz)
1.95
1.9
1.85
1.8 2.5 3 3.5 4
Vcc(V)
4.5
5
5.5
Figure 152. RC (Vcc = 5V T=25c 4 MHz)
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
4.1 4.05 4 3.95 3.9
FRc (MHz) Vcc = 5.5V Vcc = 5.0V Vcc = 4.5V Vcc = 4.0V Vcc = 3.6V Vcc = 3.3V Vcc = 3.0V Vcc = 2.7V
3.85 3.8 3.75 3.7 3.65 3.6 -40 -20 0 20
Ta(C)
40
60
80
278
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
Figure 153. RC (Vcc = 5V T=25c 4 MHz)
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
4.1 4.05 4 3.95 3.9
FRc (MHz) TA = 85C TA = -40C TA = -10C TA = 25C TA = 45C TA = 70C
3.85 3.8 3.75 3.7 3.65 3.6 2.5 3 3.5 4
Vcc(V)
4.5
5
5.5
Figure 154. RC (Vcc = 5V T=25c 8 MHz)
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.5 8.3 8.1 7.9
FRc (MHz) Vcc = 5.5V Vcc = 5.0V Vcc = 4.5V Vcc = 4.0V Vcc = 3.6V Vcc = 3.3V Vcc = 3.0V Vcc = 2.7V
7.7 7.5 7.3 7.1 6.9 6.7 -40 -20 0 20
Ta(C)
40
60
80
279
2503F-AVR-12/03
Figure 155. RC (Vcc = 5V T=25c 8 MHz )
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
8.5 8.3 8.1 7.9
FRc (MHz) TA = -40C TA = -10C TA = 25C TA = 45C TA = 70C TA = 85C
7.7 7.5 7.3 7.1 6.9 6.7 2.5 3 3.5 4
Vcc(V)
4.5
5
5.5
280
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
$3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31(1) ($51)(1) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20(2) ($40)(2) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22)
SREG SPH SPL OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL OCDR SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR
Bit 7
I -
Bit 6
T -
Bit 5
H - SP5 INT2 INTF2 TICIE1 ICF1 - TWSTA SM1 - COM01
Bit 4
S - SP4 - - OCIE1A OCF1A RWWSRE TWSTO SM0 JTRF COM00
Bit 3
V SP11 SP3 - - OCIE1B OCF1B BLBSET TWWC ISC11 WDRF WGM01
Bit 2
N SP10 SP2 - - TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02
Bit 1
Z SP9 SP1 IVSEL - OCIE0 OCF0 PGERS - ISC01 EXTRF CS01
Bit 0
C SP8 SP0 IVCE - TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00
8 10 10 78 45, 65 66 78, 104, 120 78, 105, 120 232 164 30, 64 38, 65, 213 76 77 28 209
SP7 SP6 T/C0 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SE JTD FOC0 T/C0 (8 ) ADTS2 COM1A1 ICNC1 ADTS1 COM1A0 ICES1 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SM2 ISC2 WGM00
ADTS0 COM1B1 -
- COM1B0 WGM13
ACME FOC1A WGM12
PUD FOC1B CS12
PSR2 WGM11 CS11
PSR10 WGM10 CS10
54,80,121,184,202 100 103 103 103 104 104 104 104 104 104
T/C1 - T/C1 - T/C1 - A T/C1 - A T/C1 - B T/C1 - B T/C1 - T/C1 - FOC2 T/C2 (8 ) T/C2 - - URSEL URSEL - EEPROM - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPI SPIF SPIE RXC RXCIE ACD REFS1 ADEN WCOL SPE TXC TXCIE ACBG REFS0 ADSC - DORD UDRE UDRIE ACO ADLAR ADATE - MSTR FE RXEN ACI MUX4 ADIF - CPOL DOR TXEN ACIE MUX3 ADIE - CPHA PE UCSZ2 ACIC MUX2 ADPS2 - SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 - PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 - - - UMSEL - - - - UPM1 - - WDTOE - UPM0 - USBS - - AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 EEAR9 UCPOL EEAR8 TCR2UB WDP0 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20
116 117 118 119 39 152 149 17 17 17 17 61 61 62 62 62 62 62 62 62 62 62 63 128 128 126 147 148 148 152 185 199 201 202 202 165
EEPROM
USART I/O
USART
ADC ADC TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
166
281
2503F-AVR-12/03
$01 ($21) $00 ($20)
TWSR TWBR
Bit 7
TWS7
Bit 6
TWS6
Bit 5
TWS5
Bit 4
TWS4
Bit 3
TWS3
Bit 2
-
Bit 1
TWPS1
Bit 0
TWPS0
165 164
r
Notes:
1. 2. 3. 4.
OCDEN OSCCAL OCDR UBRRH UCSRC USART 0 I/O 1 AVR CBI SBI CBI SBI 0x00 - 0x1F
282
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k k k k 1 2 (Z) (Z) Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k "0" "1" I/O "0" I/O "1" "1" "0" "1" "0" "1" "0" T "1" T "0" "1" "0" Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2

#
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1
PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC Stack PC Stack if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC
283
2503F-AVR-12/03
BRIE BRID
k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
SRAM SRAM I/O I/O I/O T T 2 2 SREG T SREG T
if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr Stack Rr Rd Stack I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V
#
1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP
SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV
CLV SET CLT SEH
SREG
V0 T1 T0 H1
V T T H
1 1 1 1
284
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
CLH MCU NOP SLEEP WDR BREAK
SREG

H0 H
#
1 1 1 1 N/A
( specific descr.) ( WDR/timer specific descr.)
None None None None
285
2503F-AVR-12/03
Speed (MHz) 8 Power Supply 2.7 - 5.5V Ordering Code ATmega32L-8AC ATmega32L-8PC ATmega32L-8MC ATmega32L-8AI ATmega32L-8PI ATmega32L-8MI 16 4.5 - 5.5V ATmega32-16AC ATmega32-16PC ATmega32-16MI ATmega32-16AI ATmega32-16PI ATmega32-16MC Package 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 Operation Range (0oC 70oC) (-40oC 85oC) (0oC 70oC) (-40oC 85oC)
44A 40P6 44M1 44- (1.0 mm)TQFP 40- 0.600" PDIP 44- 7 x 7 x 1.0 mm 0.50 mm MLF
286
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
44A
44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch. Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB
PIN 1 ID
12.25(0.482) SQ 11.75(0.462)
PIN 1
0.80(0.0315) BSC
0.45(0.018) 0.30(0.012)
10.10(0.394) SQ 9.90(0.386) 1.20(0.047) MAX 0.20(0.008) 0.09(0.004) 0~7
0.75(0.030) 0.45(0.018)
0.15(0.006) 0.05(0.002)
*Controlling dimension: millimeter
REV. A
04/11/2001
287
2503F-AVR-12/03
40P6
40-lead, Plastic Dual Inline Package (PDIP), 0.600" wide Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 52.71(2.075) 51.94(2.045)
PIN 1
13.97(0.550) 13.46(0.530)
48.26(1.900) REF 4.83(0.190)MAX SEATING PLANE 3.56(0.140) 3.05(0.120) 2.54(0.100)BSC 1.65(0.065) 1.27(0.050) 15.88(0.625) 15.24(0.600) 0.38(0.015) 0.20(0.008) 17.78(0.700)MAX 0.38(0.015)MIN 0.56(0.022) 0.38(0.015)
0 ~ 15 REF
*Controlling dimension: Inches
REV. A 04/11/2001
288
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
44M1
D
Marked pin#1 identifier SEATING PLANE A1 TOP VIEW A3 A L D2 PIN #1 CORNER SIDE VIEW COMMON DIMENSIONS (*Unit of Measure = mm) SYMBOL A A1 A3 E2 b D D2 E
E2 5.00
E
MIN 0.80 0.00 0.18
NOM 0.90 0.02 0.25 REF 0.23 7.00 BSC
MAX 1.00 0.05 0.30
NOTE
5.00
5.20 7.00 BSC
5.20
5.40
5.40
e b e L 0.35
0.50 BSC 0.55 0.75
BOTTOM VIEW NOTE 1. JEDEC STANDARD MO-220, Fig 1 (Saw Singulation), VKKD-1
08/29/01
R
2325 Orchard Parkway San Jose, CA 95131
TITLE
44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mm Micro lead frame package (MLF)
DRAWING NO. REV
44M1
B
289
2503F-AVR-12/03
ATmega32 Rev. A
ATmega32 JTAG IDCODEH IDCODE TDI IEEE1149.1 JTAG IDCODE ID TDI "1" "1" Update-DR "1" ATmega32 IDCODE TAP Test-Logic-Reset ID ATmega32 ID ATmega32 BYPASS ID ATmega32 TAP Test-LogicReset IDCODE ID ATmega32 IDCODE JTAG Update-DR ID
290
ATmega32(L)
2503F-AVR-12/03
ATmega32(L)
ATmega32
Rev. 2503E-09/03 Rev. 2503F-12/03 Rev. 2503D-02/03 Rev. 2503E-09/03
1. P27 " RC "
1. P33 "JTAG " " " 2. P35 Table 15 3. P204 " -TAP" JTAGEN 4. Bit 7 - JTD: JTAG 5. P240 Table 105 JTAGEN 6. P269 " " * , 7. P292 " " JTAG IDCODE
Rev. 2503C-10/02 Rev. 2503D-02/03
1.
P283 " " EEARH EEAR9
2. P266 "Flash" P267 "EEPROM" 3. " " "32 kHz " 4. Timer 0 Timer 2 PWM 5. P235 " ( )" SPM EEPROM 6. P1 " " 7. P20 " EEPROM " 8. P190 " ADC " 9. P216 Table 90 10. P289 " "
Rev. 2503B-10/02 Rev. 2503C-10/02 Rev. 2503A-03/02 Rev. 2503B-10/02
1. P269 " "
1. Flash 10,000 / 2. SFIOR Bit nr.4 - ADHSM 3. P23 " "
291
2503F-AVR-12/03
4. P29 " " P269 Table 118 5. P32 " " OCD 6. (WGM ):
- - - - P71 " PWM " (T/C0) P72 " PWM " (T/C0) P111 " PWM " (T/C2) P112 " PWM " (T/C2)
7. P150 Table 67 (USART) 8. P269 " " VIL, IIL IIH 9. OSCCAL 2 4 8 MHz P28 " -OSCCAL" P242 " " 10. Table 42 11. Table 45 Table 46 12. Table 119, Table 121 Table 122 13. P292 " "
292
ATmega32(L)
2503F-AVR-12/03

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