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CLC030 SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
PRELIMINARY
December 2000
CLC030 SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
General Description
The CLC030 SMPTE 292M/259M Digital Video Serializer with Ancilliary Data FIFO and Integrated Cable Driver is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital video data conforming to SMPTE 125M and 267M standard definition, 10-bit wide component video and SMPTE 260M, 274M, 295M and 296M highdefinition, 20-bit wide component video standards. The CLC030 operates at SMPTE 259M serial data rates of 270 Mbps, 360 Mbps, the SMPTE 344M (proposed) serial data rate of 540 Mbps; and the SMPTE 292M serial data rate of 1.485 Gbps. The serial data clock frequency is internally generated and requires no external frequency setting, trimming or filtering components*. Functions performed by the CLC030 include: parallel-toserial data conversion, SMPTE standard data encoding, NRZ to NRZI data format conversion, serial data clock generation and encoding with the serial data, automatic video rate and format detection, ancilliary data packet storage manipulation and insertion, and serial data output driving. The CLC030 has circuitry for automatic EDH/CRC character and flag generation and insertion per SMPTE RP-165 (standard definition) or SMPTE 292M (high definition). LSB dithering is implemented according to the proposed SMPTE recommended practice. Unique to the CLC030 are its video and ancilliary data FIFOs. The video FIFO allows from 0 to 7 parallel data clock delays to be inserted in the data path for video timing purposes. The ancilliary data port and on-chip FIFO and control circuitry offer elegant handling and insertion of ancilliary data packets and checksums in the ancilliary data space. The CLC030 also has an exclusive built-in selftest (BIST) and video test pattern generator (TPG) with SD and HD component video test patterns: reference black, PLL and EQ pathologicals and colour bars in 4:3 and 16:9 raster formats for NTSC and PAL standards*. The colour bar patterns feature optional bandwidth limiting coding between the chroma and luma transitions. The CLC030 has a unique multi-function I/O port which provides access to control and configuration signals and data. This port may be programmed to provide external access to control functions and data for use as inputs and outputs. This allows the designer greater flexibility in tailoring the CLC030 to the desired application. At power-up or after a reset command, the CLC030 is auto-configured to a default operating condition. Separate power pins for the output driver, PLL and the serializer improve power supply rejection, output jitter and noise performance. The CLC030's internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power dissipation is typically 575 mW at 1.485Gbps including two 75 ACcoupled and back-matched output loads. The device is packaged in a 64-pin TQFP.
Features
n SDTV/HDTV serial digital video standard compliant n Supports 270 Mbps, 360 Mbps, 540 Mbps and 1.485 Gbps serial video data rates with auto-detection* n LSB dithering option n No external serial data rate setting or VCO filtering components required* n Fast VCO lock time: < TBD s at 1.485 Gbps n Built-in self-test (BIST) and video test pattern generator (TPG)* n Automatic EDH/CRC word and flag generation and insertion n On-chip ancilliary data FIFO and insertion control circuitry n Flexible control and configuration I/O port n LVCMOS compatible data and control inputs and outputs n 75 ECL-compatible, differential, serial cable-driver outputs n 3.3V I/O power supply, 2.5V logic power supply operation n Low power: typically 575mW n 64-pin TQFP package n Commercial temperature range 0C to +70C
* Patent applications made or pending.
Applications
n SDTV/HDTV parallel-to-serial digital video interfaces for: -- Video cameras -- VTRs -- Telecines -- Digital video routers and switchers -- Digital video processing and editing equipment -- Video test pattern generators and digital video test equipment -- Video signal generators
(c) 2001 National Semiconductor Corporation
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Typical Application
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Block Diagram
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Connection Diagram
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64-Pin TQFP Order Number CLC030VEC See NS Package Number VEC-64A
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Absolute Maximum Ratings (Note 1)
It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. CMOS I/O Supply Voltage (VDDIO-VSSIO): SDO Supply Voltage (VDDSD-VSSSD): Digital Logic Supply Voltage (VDDD-VSSD): PLL Supply Voltage (VDDPLL-VSSPLL): CMOS Input Voltage (Vi): CMOS Output Voltage (Vo): CMOS Input Current (single input): Vi = VSSIO -0.15V: Vi = VDDIO +0.15V: CMOS Output Source/Sink Current: SDO Output Sink Current: 4.0V 4.0V 3.0V 3.0V VSSIO -0.15V to VDDIO +0.15V VSSIO -0.15V to VDDIO +0.15V -5 mA +5 mA 10 mA 40 mA
Package Thermal Resistance JA @ 0 LFM Airflow JA @ 500 LFM Airflow JC Storage Temp. Range: Junction Temperature: Lead Temperature (Soldering 4 Sec): ESD Rating (HBM): ESD Rating (MM): Transistor Count:
TBDC/W TBDC/W TBDC/W -65C to +150C +150C +260C 2 kV 300V TBD
Recommended Operating Conditions
CMOS I/O Supply Voltage (VDDIO-VSSIO): SDO Supply Voltage (VDDSD-VSSSD): Digital Logic Supply Voltage (VDDD-VSSD): PLL Supply Voltage (VDDPLL-VSSPLL): CMOS Input Voltage: Operating Free Air Temperature (TA): 3.3V 150 mV 3.3V 150 mV 2.5V 125 mV 2.5V 125 mV VSSIO to VDDIO 0C to +70C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol VIH VIL IIH IIL VOH VOL VSDO IDD (3.3V) Parameter Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Low Level CMOS Output Voltage High Level CMOS Output Voltage Low Level Serial Driver Output Voltage Power Supply Current, 3.3V Supply, Total VIH = VDDIO VIL = VSSIO IOH = -10 mA IOL = +10 mA Test Circuit, Test Loads Shall Apply VCLK = 27 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply VCLK = 74.25 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply VCLK = 27 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply VCLK = 74.25 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply SDO, SDO VDDIO, VDDSD 30 TBD mA All LVCMOS Outputs 2.4 VSSIO 720 Conditions Reference All LVCMOS Inputs Min 2.0 VSSIO +40 -1 2.7 VSSIO +0.3 800 Typ Max VDDIO 0.8 +60 -20 VDDIO VSSIO +0.5V 880 Units V V A A V V mVP-P
IDD (3.3V)
Power Supply Current, 3.3V Supply, Total
VDDIO, VDDSD 80 TBD mA
IDD (2.5V)
Power Supply Current, 2.5V Supply, Total
VDDD, VDDZ, VDDPLL
50
TBD
mA
IDD (2.5V)
Power Supply Current, 2.5V Supply, Total
VDDD, VDDZ, VDDPLL
125
TBD
mA
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CLC030
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol fVCLK DCV tJIT fACLK DCA tr, tf BRSDO tr, tf tj tj tLOCK tLOCK tS tH tS tH Parameter Parallel Video Clock Frequency Video Clock Duty Cycle Video Clock Jitter Ancilliary Clock Frequency Ancilliary Clock Duty Cycle Input Clock and Data Rise Time, Fall Time Serial Data Rate Rise Time, Fall Time Output Overshoot Serial Output Jitter, Intrinsic Serial Output Jitter, Intrinsic Lock Time Lock Time Setup Time, Video Data Hold Time, Video Data Setup Time, Anc. Data Port Hold Time, Anc. Data Port (Note 11) (Note 11) (Notes 8, 11) (Note 11) (Note 11) 10%-90%, (Note 11) (Notes 5, 6) 20%-80%, (Note 6) (Note 4) 270 MBPS, (Notes 5, 9, 10) 1,485 MBPS, (Notes 6, 9, 10) (Notes 5, 7) (SD Rates) (Notes 6, 7) (HD Rates) Timing Diagram, (Note 11) Timing Diagram, (Note 11) Timing Diagram, (Note 11) Timing Diagram, (Note 11) DVN to VCLK VCLK to DVN ADN to ACLK ACLK to ADN 1.5 1.5 1.5 1.5 Conditions Reference VCLK VCLK VCLK ACLK ACLK VCLK, ACLK, DVN, ADN SDO, SDO SDO, SDO SDO, SDO SDO, SDO SDO, SDO 5 0.1 0.1 500 500 2.0 2.0 2.0 2.0 1x 10-3 45 1.0 270 50 1.5 Min 27 45 50 100 VCLK 55 3.0 1,485 270 Typ Max 74.25 55 Units MHz % psP-P MHz % ns MBPS ps % UIP-P UIP-P s s ns ns ns ns
Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics" specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VSS = 0V. Note 3: Typical values are stated for VDDIO = VDDSD = +3.3V, VDDD = VDDPLL = +2.5V and TA = +25C. Note 4: Spec. is guaranteed by design. Note 5: RL = 75, AC-coupled @ 270 MBPS, RREFLVL = RREFPRE = 4.75 k 1%, See Test Loads and Test Circuit. Note 6: RL = 75, AC-coupled @ 1,485 MBPS, RREFLVL = RREFPRE = 4.75 k 1%, See Test Loads and Test Circuit. Note 7: Measured from rising-edge of first DVCLK cycle until Lock Detect output goes high (true). Note 8: Average value measured between rising edges computed over at least one video field. Note 9: Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission standard, SMPTE 259M-1997 or SMPTE 292M (proposed). A colour bar test pattern is used. The value of fSCLK is 270 MHz or 360 MHz for SMPTE 259M, 540MHz for SMPTE 344M or 1,485 MHz for SMPTE 292M serial data rates. See Timing Jitter Bandpass section. Note 10: Intrinsic jitter is defined in accordance with SMPTE RP 184-1996 as: jitter at an equipment output in the absence of input jitter. As applied to this device, the input port is VCLK and the output port is SDO or SDO. Note 11: The signal applied to the appropriate input of this device shall conform to the stated specification.
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Test Loads
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Timing Jitter Bandpass
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Test Circuit
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Timing Diagram
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Device Operation
The CLC030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts parallel SDTV or HDTV component digital video signals into serial format. Logic levels within this equipment are normally produced by LVCMOS logic devices. The encoder produces ECL-compatible serial digital video (SDV) signals conforming to SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M. The CLC030 operates at parallel data rates of 27.0 MHz, 36.0 MHz, 54.0 MHz and 74.25 MHz. Corresponding serial data rates are 270 Mbps, 360 Mbps, 540 Mbps and 1.485 Gbps. VIDEO DATA PATH The input data register accepts 10-bit standard definition or 20-bit high definition parallel data and associated clock signals having LVCMOS-compatible signal levels. All parallel data inputs, DV[19:0] and AD[9:0], have internal pull-down devices. VCLK and ACLK do not have internal pull-down devices. Parallel video data may conform to any of several SMPTE standards: 125M, 267M, 260M, 274M, 295M or 296M. For HDTV data, the upper 10 bits of the DV input are luminance (luma) information and the lower 10 bits are colour difference (chrominance or chroma) information. For SDTV data, the lower order 10-bits contain both luma and chroma information. Output from this register feeds the video FIFO, video format detection circuit, TRS character detector, SMPTE scrambler, EDH/CRC generators, serializer/NRZI converter and the device control system. Data from the input data register passes into an 8-register deep video FIFO prior to encoding and other processing. The depth of this FIFO is set by a word written into the VIDEO FIFO Depth[2:0] bits in the ANC 0 control register. The video format detector automatically determines the raster characteristics (video data format) of the parallel input data and configures the CLC030 to properly handle the data. This assures that the data will be properly formatted, that the correct data rate is selected and that ancilliary data and CRC/EDH data are correctly inserted. Indication of the standard being processed is stored in the FORMAT[4:0] bits in the FORMAT 1 control data register. This format data can be programmed for output on the multi-function I/O port. The CLC030 may be configured to operate at a single video format by writing the appropriate FORMAT SET[4:0] control data into the FORMAT 0 control register. Also, the CLC030 may be configured to handle only the standard-definition data formats by setting the SD ONLY bit or only the highdefinition data formats by setting the HD ONLY bit in the FORMAT 0 control register. When both of these bits are reset the part automatically detects the data rate and range. The TRS character detector processes the timing reference signals which control raster framing. The TRS detector supplies control signals to the system controller to identify the presence of the valid video data. The system controller supplies necessary control signals to the EDH/CRC control block. TRS character LSB-clipping as prescribed in ITU-R BT.601 is used. LSB-clipping causes all TRS characters with a value between 000h and 003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh. Clipping is done prior to scrambling and EDH/CRC character generation. The CLC030 incorporates circuitry that implements the proposed SMPTE recommended practice and method for LSB dithering. Control of this circuitry is via the Dither Enable bit in the VIDEO INFO 0 control register. Dithering can be selectively enabled during the vertical blanking interval by use of the V Dither Enable bit in the VIDEO INFO 0 control register. The initial condition of Dither Enable and V Dither Enable is OFF. The SMPTE scramblers accept 10-bit standard definition or 20-bit high definition parallel video data and encode it using the polynomial X9 + X4 + 1 as specified in the respective standard in SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M. The data is then serialized and sent to the NRZ-to-NRZI converter before being output. The transmission bit order is LSB-first. The NRZ-to-NRZI converter accepts NRZ serial data from the SMPTE scrambler. The data is converted to NRZI format using the polynomial (X + 1). The converter's output goes to the output cable driver amplifier. ANCILLIARY/CONTROL DATA PATH The Ancilliary and Control Data Port is used to load ancilliary data into the Ancilliary Data FIFO for insertion into the video data stream. This port also provides read/write access to contents of the configuration and control registers. It is also used to configure the Multi-function I/O Port. Ancilliary and control data are input via the 10-bit Ancilliary/Control Data Port, AD[9:0]. The signals RD/WR, ANC/CTRL and ACLK control data flow through the port. The utilization and flow of ancilliary data within the device is managed by a system of control bits, masks and IDs in the control data registers. Control data are input to and output from the CLC030 using the lower-order 8 bits AD[7:0] of the Ancilliary/Control Data Port. This control data initializes, monitors and controls operation of the CLC030. The upper two bits AD[9:8] of the
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Device Operation
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port function as handshaking signals with the device accessing the port. When either a control register read or write address is being written to the port, AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]). When control data is being written to the port, AD[9:8] must be driven as 11b (3XXh, where XX are AD[7:0]). When control data is being read from the port, the CLC030 will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system.
Example: Read the Full-field Flags via the AD port. 1) Take ANC/CTRL to a logic-low. 2) Take RD/WR to a logic-high. 3) Present 001h to AD[9:0] as the register address. 4) Transition ACLK L-H. 5) Release the bus driving the AD port. 6) Read the data present on the AD port. The Full-field Flags are bits AD[4:0]. 7) To release the AD port, transition ACLK L-H.
Figure 1 shows the sequence of clock and control signals for reading control data from the ancilliary/control data port. Control data read mode is invoked by making the ANC/ CTRL input low and the RD/WR input high. The 8-bit address of the control register set to be accessed is input to the port on bits AD[7:0]. The address is captured on the rising edge of ACLK. When a control register read address is being written to the port, AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]). When control data is being read from the port, the CLC030 will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system. Data being output from the selected register is driven by the port immediately following the rising edge of ACLK or when the address signal is removed. For optimum system timing, the signals driving the address to the port should be removed before or at the falling edge of ACLK at the end of that address cycle. Output data remains stable until the next rising edge of ACLK and may be written into external devices at any time after the removal of the address signal.
Figure 2 shows the sequence of clock and control signals for writing control data to the ancilliary/control data port. The control data write mode is similar to the read mode. Control data write mode is invoked by making the ANC/CTRL input low and the RD/WR input low. The 8-bit address of the control register set to be accessed is input to the port on bits AD[7:0]. The address is captured on the rising edge of ACLK. The address data is removed on the falling edge of ACLK. Next, the control data is presented to the port bits AD[7:0] and written into the selected register on the next rising edge of ACLK. When a control register write address is being written to the port, AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]). When control data is being written to the port, AD[9:8] must be driven as 11b (3XXh, where XX are AD[7:0]). Control data written into the registers may be read out non-destructively in most cases. Example: Enable the TPG Mode and the SMPTE 260M colour bars as test pattern via the AD port. 1) Take ANC/ CTRL to a logic-low. 2) Take RD/WR to a logic-low. 3) Present 00Dh to AD[9:0] as the Test 0 register address. 4) Toggle ACLK. 5) Present 063h to AD[9:0] as the register data. 6) Toggle ACLK.
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FIGURE 1. Control Data Read Timing (2 read and 1 write cycle shown)
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FIGURE 2. Control Data Write Timing
Figure 3 shows the sequence of clock, data and control signals for writing ancilliary data to the port. In ancilliary data write mode, 10-bit Ancilliary Data is written into the port using bits AD[9:0] and routed to the ancilliary data FIFO. From the FIFO, the ancilliary data can be written into the ancilliary data spaces in the serial video data stream. Ancilliary data write mode is invoked by making the ANC/CTRL input high and the RD/WR input low. Data presented to the port on a falling edge of ACLK is written into the FIFO on the
next rising edge of ACLK. Data may only be written to the port when in the ancilliary data mode. Ancilliary data cannot be read from the port. Admission of ancilliary data to and from the FIFO is controlled by a system of masking and control bits in the control registers. The details and functions of these control registers and bits is explained later in this datasheet.
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FIGURE 3. Ancilliary Data Write Timing MULTI-FUNCTION I/O PORT The multi-function I/O port can be configured to provide immediate access to many control and indicator functions within the CLC030 configuration and control registers. The individual pins comprising this port are assigned as input or output for selected bits in the control data registers. The multi-function I/O port is configured by way of an 8x6-bit register bank, configuration and control registers I/O pin 0 CONFIG through I/O pin 7 CONFIG. The contents of these registers determine whether the port bits function as inputs or outputs and to which register element each port bit is assigned. Port bits may be assigned to access different register elements or any or all port bits may be assigned to access the same register element (an unlikely or unusual situation). Controls and indicators that are accessible by the port and their corresponding selection addresses are given in the I/O Pin Configuration Register Addresses, Table 6. Table 2 gives the control register bit assignments.
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Example: Program multi-function I/O port bit-0 as the CRC Luma Error bit output. 1) Take ANC/CTRL to a logic-low. 2) Take RD/WR to a logic-low. 3) Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address. 4) Toggle ACLK. 5) Present 310h to AD[9:0] as the register data. 6) Toggle ACLK. EDH/CRC SYSTEM The CLC030 has EDH and CRC character generation and insertion circuitry. The EDH system functions as described in SMPTE Recommended Practice RP-165. The CRC system functions as specified in SMPTE 292M. The EDH/CRC polynomial generators accept parallel data from the input register and generate the EDH and CRC check words for insertion in the serial data. Incoming parallel data is checked for errors and the EDH flags are updated automatically. EDH check words and status flags for SDTV data are generated using the polynomial X16 + X12 + X6 + 1 per SMPTE RP165.
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Device Operation
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EDH check words are inserted in the serial data stream at the correct positions in the ancilliary data space and formatted per SMPTE 291M. Generation and automatic insertion of the EDH check words is controlled by EDH Force and EDH Enable bits in the control registers. After a reset, the initial state of all EDH and CRC check characters is 00h. The SMPTE 292M high definition video standard employs CRC (cyclic redundancy check codes) error checking instead of EDH. The CRC consists of two 18-bit words generated using the polynomial X18 + X5 + X4 + 1 per SMPTE 292M. One CRC is used for luminance and one for chrominance data. CRC data is inserted at the required place in the video data according to SMPTE 292M. The CRCs appear in the data stream following the EAV and line number characters. EDH and CRC errors are reported in the EDH0, EDH1, and EDH2 register sets of the configuration and control registers. PHASE-LOCKED LOOP SYSTEM The phase-locked loop (PLL) system generates the output serial data clock at 10x (standard definition) or 20x (high definition) the parallel data clock frequency. This system consists of a VCO, divider chain, phase-frequency detector and internal loop filter. The VCO free-running frequency is internally set. The PLL automatically generates the appropriate frequency for the serial clock rate using the parallel data clock (VCLK) frequency as its reference. Loop filtering is internal to the CLC030. The VCO has separate analog and digital power supply feeds: VDDPLLA pin 62, VSSPLLA pin 61, VDDPLLD pin 1, and VSSPLLD pin 2. These may be separately supplied power via external low-pass filters, if desired. PLL acquisition (lock) time is less than 500s @ 1,485 Mbps. The VCO halts when VCLK signal is not present or is inactive. A LOCK DETECT indicator is available as a bit in the VIDEO INFO 0 control registers. This function also includes logic to check the stability of the device after the digital logic reset is released following PLL lock. If the system is not fully stable, the logic is automatically reset. LOCK DETECT is a logic-1 when the loop is locked and can be assigned as an output on the multifunction I/O port. The power-on default assigns LOCK DETECT as I/O Port bit 4. SERIAL DATA OUTPUT DRIVER The serial data outputs provide low-skew complimentary or differential signals. The output buffer design is intended to drive AC-coupled and terminated, 75 coaxial cables. Output levels are 800 mVP-P 10% into 75 AC-coupled loads. The 75 resistors connected to the SDO outputs function both as drain-load and back-matching resistors. No series back-matching resistors should be used. The serial output level is controlled by the value of RREFLVL and RREFPRE connected to pin 53 and pin 52, respectively. The RREFLVL resistor sets the nominal peak-to-peak level of the output signal to the SMPTE nominal level. The RREFPRE resistor sets the value of a pre-emphasis current which is active during the rise and fall times of the HD-rate output signal. The value of RREFLVL is normally 4.75 K, 1%. The value of RREFPRE is normally 4.75 K, 1%. The rise and fall times of this output buffer design automatically adjust and are different for the HD and SD data rate conditions. The output buffer is quiescent when the device is in an out-oflock condition. The output will become active after the VCO
is locked and a valid format has been detected. Separate power feeds are provided for the serial output driver: VSSSD, pins 54, 55, and 59; VDDSD, pin 51; and VDDLS, pin 57. NOTE: This output buffer is not designed or specified for driving 50 or other impedance loads. POWER-ON-RESET AND RESET INPUT The CLC030 has an automatic, power-on-reset circuit. Reset initializes the device and clears TRS detection circuitry, all latches, registers, counters and polynomial generators, sets the EDH/CRC characters to 00h and disables the serial output. An active-HIGH-true, manual reset input is available at pin 64. The reset input has an internal pull-down device and is inactive when unconnected. TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST) The CLC030 includes an on-board test pattern generator (TPG). Four test pattern types are available in both HD and SD formats, NTSC and PAL standards, and 4x3 and 16x9 raster sizes. The test patterns are: flat-field black, PLL pathological, equalizer (EQ) pathological and a 75%, 8-colour vertical bar pattern. The pathologicals follow recommendations contained in SMPTE RP 178-1996 regarding the test data used. The colour bar pattern has optional bandwidth limiting coding in the chroma and luma data transitions between bars. The VPG FILTER ENABLE bit in the VIDEO INFO 0 control register enables the colour bar filter function. The default condition of VPG FILTER ENABLE is OFF. The TPG also functions as a built-in self-test (BIST) which can verify device functionality. The BIST function performs a comprehensive go/no-go test of the device. The test may be run using any of the HD colour bar test patterns or one of two SD test patterns, either a 270 Mb/s NTSC full-field colour bar or a PLL pathological, as the test data pattern. Data is input internally in the input data register, processed through the device and tested for errors using either the EDH system for SD or the CRC system for HD. A go/no-go indication is logged in the Pass/Fail bit of the TEST 0 control register set. This bit may be assigned as an output on the multifunction I/O port. TPG and BIST operation is initiated by loading the code for the desired test pattern into the Test Pattern Select[5:0] bits and by setting the TPG Enable bit of the TEST 0 register. In the default power-on state, TPG Enable appears as bit 7 on the multi-function I/O port. The TPG is run by making TPG Enable true and applying the appropriate frequency clock at the VCLK input. Note that when attempting to use the TPG or BIST immediately after the device has been reset or powered on, the TPG defaults to the 270Mbps SD rate and expects a VCLK clock frequency of 27MHz as input. The device must also be configured for the desired test pattern. If HD operation is desired, the device must be further configured for an HD rate and test pattern. (Note also the requirement to initialize the ancilliary data port control logic by clocking ACLK at least three (3) complete cycles before attempting to load the first register address).Table 5 gives the available test patterns and codes. The Pass/Fail bit in the control register gives device test status indication. If no errors have been detected, this bit will be set to logic-1 approximately 2 field intervals after TPG Enable is set. If errors have been detected in the internal circuitry of the CLC030, Pass/Fail will remain reset to a logic-0. The TPG or BIST is stopped by resetting TPG Enable. The serial output data is present at the SDO outputs during TPG or BIST operation.
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Example: Enable the TPG Mode to use the NTSC 270Mbps SD colour bars as the BIST and TPG pattern. 1) Take ANC/CTRL to a logic-low. 2) Take RD/WR to a logic-low. 3) Present 00Bh to AD[9:0] as the FORMAT 0 register address. 4) Toggle ACLK. 5) Present 343h to AD[9:0] as the register data (SD, SMPTE 125M, 27MHz). 6) Toggle ACLK. 7) Present 00Dh to AD[9:0] as the TEST 0 register address. 8) Toggle ACLK. 9) Present 343h to AD[9:0] as the register data (SD-ONLY, NTSC 525/30/4x3 Colour bars). 10) Toggle ACLK. 11) Take TPG ENABLE (I/O Port, bit 7) high. The PASS/FAIL indicator (I/O Port, bit 6) is monitored for the result of the test. CONFIGURATION AND CONTROL REGISTERS The configuration and control registers store data to configures the operational modes of the CLC030 or which result from its operation. Many of these registers may be assigned as external I/O functions which are then available on the multi-function I/O bus. These functions are summarized in Table 1 and detailed in Table 2. The power-on default condition for the multi-function I/O port is indicated in Table 1 and detailed in Table 6.
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Device Operation
(Continued) TABLE 1. Configuration and Control Data Register Summary
Register Function CRC Error (SD/HD) CRC Error Luma CRC Error Chroma Full-Field Flags Active Picture Flags ANC Flags EDH Force EDH Enable F/F Flag Error A/P Flag Error ANC Flag Error ANC Checksum Force ANC Checksum Error FIFO Empty FIFO Full FIFO Overrun Video FIFO Depth ANC ID ANC Mask MSG Track MSG Flush Static MSG Flush Dynamic FIFO Flush Static FIFO Flush Dynamic MSG Flush Static Full MSG Required Chksum Attach In FIFO Insert Enable VANC Switch Point 0 Switch Point 1 Switch Point 2 Switch Point 3 Format Set SD Only HD Only Format H V F Test Pattern Select TPG Enable Pass/Fail New Sync Position (NSP) SAV EAV
Bits 1 1 1 5 5 5 1 1 1 1 1 1 1 1 1 1 3 16 16 1 1 1 1 1 1 1 1 1 1 8 8 8 8 5 1 1 5 1 1 1 6 1 1 1 1 1
Read or Write R R R R R R R/W R/W R R R R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R R R R
Initial Condition
Available on I/O Bus Output Output Output No No No
Notes (Note 12)
OFF OFF
Input Input Output Output Output
OFF
Input Output Output Output
OFF 0000h FFFFh OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 00h 00h 00h 00h OFF OFF OFF
Input/Output No No No No No No No No No No Input Input No No No No No No No No Output Output Output Output Format [4] (Note 12) (Note 12) (Note 12) (Note 12) (Note 12) (Note 12)
525/27 MHz/Black OFF
Input Input Output Output Output Output
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14
CLC030
Device Operation
Register Function Lock Detect VPG Filter Enable Dither_Enable Vert. Dither Enable I/O Bus Pin Config.
(Continued)
TABLE 1. Configuration and Control Data Register Summary (Continued) Bits 1 1 1 1 48 Read or Write R R/W R/W R/W R/W OFF See Table 6 OFF Initial Condition Available on I/O Bus Output Input Input Input No Notes (Note 12)
Note 12: Connected to multifunction I/O port at power-on. Note 13: ON = logic-1, OFF = logic-0 (positive logic).
TABLE 2. Control Register Bit Assignments
Bit 7 CRC ERROR reserved Bit 6 EDH FORCE Bit 5 EDH ENABLE Bit 4 F/F FLAGS(4) Bit 3 F/F FLAGS(3) A/P FLAGS(3) ANC FLAGS(3) FIFO EMPTY ANC ID(3) ANC ID(11) ANC MASK(3) Bit 2 F/F FLAGS(2) A/P FLAGS(2) ANC FLAGS(2) FIFO FULL ANC ID(2) ANC ID(10) ANC MASK(2) Bit 1 F/F FLAGS(1) A/P FLAGS(1) ANC FLAGS(1) ANC CHECKSUM ERROR ANC ID(1) ANC ID(9) ANC MASK(1) ANC MASK(9) MSG FLUSH STATIC
*FRAME
Bit 0 F/F FLAGS(0) A/P FLAGS(0) ANC FLAGS(0) ANC CHECKSUM FORCE ANC ID(0) ANC ID(8) ANC MASK(0) ANC MASK(8)
EDH 0 (register address 01h) EDH 1 (register address 02h) CRC ERROR LUMA CRC ERROR CHROMA A/P FLAGS(4) ANC FLAG ERROR VIDEO FIFO-DEPTH(0) ANC ID(5) ANC ID(13) ANC MASK(5) ANC MASK(13) FULL MSG REQUIRED ANC PARITY MASK LINE(5) PROTECT(2) LINE(5) PROTECT(2) HD ONLY H TEST PATTERN SELECT(5) VPG FILTER ENABLE ANC FLAGS(4) FIFO OVERRUN ANC ID(4) ANC ID(12) ANC MASK(4) EDH 2 (register address 03h) F/F FLAG ERROR A/P FLAG ERROR ANC 0 (register address 04h) VIDEO FIFO-DEPTH(2) ANC ID(7) ANC ID(15) ANC MASK(7) ANC MASK(15) FIFO INSERT ENABLE VIDEO FIFO-DEPTH(1) ANC ID(6) ANC ID(14) ANC MASK(6) ANC MASK(14) CHKSUM ATTACH IN
ANC 1 (register address 05h) ANC 2 (register address 06h) ANC 3 (register address 07h) ANC 4 (register address 08h) ANC MASK(12) ANC MASK(11) ANC MASK(10) FIFO FLUSH DYNAMIC
*BUFFER
ANC 5 (register address 17h) FIFO FLUSH STATIC
*BUFFER
MSG FLUSH DYNAMIC
*FRAME
MSG TRACK
ANC 6 (register address 18h) reserved reserved READY IN LINE(4) PROTECT(1) LINE(4) PROTECT(1) READY OUT LINE(3) PROTECT(0) LINE(3) PROTECT(0) LOCK IN LINE(2) LINE(10) LINE(2) LINE(10) LOCK OUT LINE(1) LINE(9) LINE(1) LINE(9) VANC
SWITCH POINT 0 (register address 09h) LINE(7) PROTECT(4) LINE(7) PROTECT(4) reserved F LINE(6) PROTECT(3) LINE(6) PROTECT(3) SD ONLY V LINE(0) LINE(8) LINE(0) LINE(8) SWITCH POINT 1 (register address 0Ah) SWITCH POINT 2 (register address 19h) SWITCH POINT 3 (register address 1Ah) FORMAT 0 (register address 0Bh) FORMAT SET(4) FORMAT SET(3) FORMAT SET(2) FORMAT SET(1) FORMAT SET(0) FORMAT(4) FORMAT(3) FORMAT(2) FORMAT(1) FORMAT(0) FORMAT 1 (register address 0Ch) TEST 0 (register address 0Dh) PASS/FAIL TPG ENABLE TEST PATTERN TEST PATTERN TEST PATTERN TEST PATTERN TEST PATTERN SELECT(4) SELECT(3) SELECT(2) SELECT(1) SELECT(0) LOCK DETECT
VIDEO INFO 0 (register address 0Eh) DITHER ENABLE VERT. DITHER ENABLE EAV SAV NSP reserved
15
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CLC030
Device Operation
Bit 7 Bit 6
(Continued) TABLE 2. Control Register Bit Assignments (Continued)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MULTI-FUNCTION I/O BUS PIN CONFIGURATION I/O PIN 0 CONFIG (register address 0Fh) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved PIN 0 SEL[5] PIN 1 SEL[5] PIN 2 SEL[5] PIN 3 SEL[5] PIN 4 SEL[5] PIN 5 SEL[5] PIN 6 SEL[5] PIN 7 SEL[5] PIN 0 SEL[4] PIN 1 SEL[4] PIN 2 SEL[4] PIN 3 SEL[4] PIN 4 SEL[4] PIN 5 SEL[4] PIN 6 SEL[4] PIN 7 SEL[4] PIN 0 SEL[3] PIN 1 SEL[3] PIN 2 SEL[3] PIN 3 SEL[3] PIN 4 SEL[3] PIN 5 SEL[3] PIN 6 SEL[3] PIN 7 SEL[3] PIN 0 SEL[2] PIN 1 SEL[2] PIN 2 SEL[2] PIN 3 SEL[2] PIN 4 SEL[2] PIN 5 SEL[2] PIN 6 SEL[2] PIN 7 SEL[2] PIN 0 SEL[1] PIN 1 SEL[1] PIN 2 SEL[1] PIN 3 SEL[1] PIN 4 SEL[1] PIN 5 SEL[1] PIN 6 SEL[1] PIN 7 SEL[1] PIN 0 SEL[0] PIN 1 SEL[0] PIN 2 SEL[0] PIN 3 SEL[0] PIN 4 SEL[0] PIN 5 SEL[0] PIN 6 SEL[0] PIN 7 SEL[0] I/O PIN 1 CONFIG (register address 10h) I/O PIN 2 CONFIG (register address 11h) I/O PIN 3 CONFIG (register address 12h) I/O PIN 4 CONFIG (register address 13h) I/P PIN 5 CONFIG (register address 14h) I/O PIN 6 CONFIG (register address 15h) I/O PIN 7 CONFIG (register address 16h)
TABLE 3. Control Register Addresses Register Name EDH 0 EDH 1 EDH 2 ANC 0 ANC 1 ANC 2 ANC 3 ANC 4 ANC 5 ANC 6 SWITCH POINT 0 SWITCH POINT 1 SWITCH POINT 2 SWITCH POINT 3 FORMAT 0 FORMAT 1 TEST 0 VIDEO INFO 0 I/O PIN 0 CONFIG I/O PIN 1 CONFIG I/O PIN 2 CONFIG I/O PIN 3 CONFIG I/O PIN 4 CONFIG I/O PIN 5 CONFIG I/O PIN 6 CONFIG I/O PIN 7 CONFIG Address Decimal 1 2 3 4 5 6 7 8 23 24 9 10 25 26 11 12 13 14 15 16 17 18 19 20 21 22 Address Hexadecimal 01 02 03 04 05 06 07 08 17 18 09 0A 19 1A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16
EDH REGISTERS 0, 1 AND 2 (Addresses 01h through 03h) The CRC Error flag indicates that parallel data has been input that contains detected errors in either the EDH checksums (SD) or CRC checkwords (HD). Updated EDH packets may be inserted by setting the EDH Force bit in the control registers. The EDH Force control bit causes the insertion of new EDH checkwords and flags into the serial output regardless of the previous condition of EDH checkwords and flags in the input parallel data. This function may be used in situations where video content has been editted thus making the previous EDH information invalid. In the case of SMPTE 292M data, the CRC check characters are recalculated and inserted automatically regardless of the presence of CRC characters in the parallel data. After the CLC030 is reset, the initial state of the CRC check characters is 00h. The EDH Enable bit enables operation of the EDH generator function. The EDH flags F/F FLAGS[4:0], A/P FLAGS[4:0] and ANC FLAGS[4:0] are defined in SMPTE RP 165. The EDH flags are stored in the control registers. The flags are updated automatically when the EDH function is enabled and data is being received. The status of EDH flag errors in incoming SD parallel data are reported in the ffFlagError, apFlagError and ancFlagError bits. The ffFlagError, apFlagError and ancFlagError bits are the logical-OR of the corresponding EDH and EDA flags of the EDH checkwords. CRC errors in incoming HD parallel data are reported in the CRC ERROR, CRC ERROR LUMA and CRC ERROR CHROMA bits in the control registers. ANC REGISTERS 1 THROUGH 6 (Addresses 04h through 08h, 17h and 18h) The V FIFO Depth[2:0] bits control the depth of the video FIFO which follows the input data latches. The depth can be set from 0 to 7 stages deep by writing the corresponding binary code into these bits. For example: to set the Video FIFO depth at two registers, load 11010XXXXXb into the
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16
CLC030
Device Operation
(Continued)
ANC 0 control register (where X represents the other functional bits of this register). To retain other data previously stored in a register, read the register's contents and logically-OR this with the new data. Then write the composite data back into the register. Flags for FIFO EMPTY, FIFO FULL and FIFO OVERRUN are available in the configuration and control register set. These flags can also be assigned as inputs and outputs on the multi-function I/O port. The FIFO OVERRUN flag indicates that an attempt to write data into a full FIFO has occurred. When FIFO FLUSH DYNAMIC or MSG FLUSH DYNAMIC are enabled, the FIFO OVERRUN function is superceded. When FIFO OVERRUN is active and not superceded, it can be reset by reading the bit's status via the Ancilliary/Command port. To be used properly, FIFO OVERRUN should be assigned as an output on the multi-function I/O port and monitored by the host system. Otherwise, inadvertent loss of ancilliary packet data could occur. The ANC Checksum Force bit, under certain conditions, enables the overwriting of ancilliary data checksums received in the parallel ancilliary data. Calculation and insertion of new ancilliary data checksums is controlled by the ANC Checksum Force bit. If a checksum error is detected (calculated and received checksums do not match) and the ANC Checksum Force bit is set, a new checksum will be inserted in the ancilliary data replacing the previous one. If a checksum error is detected and the ANC Checksum Force bit is not set, the checksum mismatch is reported via the ANC Checksum Error bit. Ancilliary data checksums may be received in the incoming parallel ancilliary data. Alternatively they may be calculated and inserted automatically by the CLC030. The CHKSUM ATTACH IN bit in the control registers when set to a logic-1 indicates that the checksum is to be supplied in the incoming data. When the CHKSUM ATTACH IN bit is set, checksums for incoming data are calculated and checked against received checksums. Calculation and insertion of new ancilliary data checksum is controlled by the ANC Checksum Force bit in the configuration and control registers. If a checksum error is detected (calculated and received checksums do not match) and the ANC Checksum Force bit is set, a new checksum will be inserted in the ancilliary data replacing the previous one. If a checksum error is detected and the ANC Checksum Force bit is not set, the checksum mismatch is reported via the ANC CHECKSUM ERROR bit in the control registers. The ANC Checksum Error bit indicates that the received ancilliary data checksum did not agree with the CLC030's internally generated checksum. This bit is available as an output on the multifunction I/O port. Admission of ancilliary data packets into the FIFO is controlled by the ANC MASK[15:0] and ANC ID[15:0] bits in the control registers. The ANC ID[15:0] normally is set to a valid 16-bit code used for component ancilliary data packet identification as specified in SMPTE 291M-1998. The ANC MASK[15:0] is a 16-bit word that can be used to selectively control loading of packets with specific IDs (or ID ranges) into the FIFO. When the ANC MASK[15:0] is set to FFFFh, packets with any ID can be loaded into the FIFO. When any bit or bits of the ANC MASK[15:0] are set to a logic-1, the corresponding bit or bits of the ANC ID[15:0] are a don'tcare when matching IDs of incoming packets. When the ANC MASK[15:0] is set to 0000h, the ANC ID of incoming packets must match exactly, bit-for-bit the ANC ID[15:0] set
17
in the control register for the packets to be loaded into the FIFO. The initial value of the ANC MASK[15:0] is FFFFh and the ANC ID[15:0] is 0000h. The ANC PARITY MASK bit when set disables parity checking for the DATA ID (DID) and SECONDARY DATA ID (SDID) in the ANC data packet. When reset, parity checking is enabled, and, if a parity error occurs, the packet will not be loaded. The FIFO INSERT ENABLE bit in the control registers enables insertion of ancilliary data stored in the FIFO into the serial data stream. Data insertion is enabled when this bit is set to a logic-1. This bit can be used to delay automatic insertion of data into the serial data stream. The CLC030 can keep track of up to 8 ancilliary packets in the FIFO. Incoming packet length versus available space in the FIFO is also tracked. The MSG TRACK bit in the control registers, when set, enables tracking of packets in the FIFO. MSG TRACK also enables several other functions for control of packet traffic in the FIFO: FIFO FLUSH DYN, FIFO FLUSH STAT, MSG FLUSH DYN, and MSG FLUSH STAT. With message tracking enabled and FIFO FLUSH DYN set to a logic-1, if a FIFO full condition is encountered, all existing message packets in the FIFO will be flushed. The current message packet will be left intact. When FIFO FLUSH DYN is not set and a FIFO full condition is encountered, the FIFO will overrun and the FIFO OVERRUN flag will be set. FIFO FLUSH DYN remains set until cleared. With message tracking enabled, setting the FIFO FLUSH STAT bit to a logic-1 flushes the FIFO. Data may not be loaded into the FIFO during FIFO FLUSH STAT execution. FIFO FLUSH STAT is automatically reset after this operation is complete. With message tracking enabled and MSG FLUSH DYN set to a logic-1, the oldest message packet in the FIFO will be flushed when the next message is written to the FIFO. MSG FLUSH DYN remains set until cleared. With message tracking enabled and MSG FLUSH STAT set to a logic-1, the oldest message packet in the FIFO is flushed when data is not being written to the FIFO. MSG FLUSH STAT is automatically reset after this operation is complete. The FULL MSG REQ (full message required) bit in the control registers, when set, instructs the CLC030 to insert only complete packets residing in the FIFO into the serial data stream. When this bit is not set, messages of any length, incomplete or partial, will be inserted into the serial data stream. This function is not affected by MSG TRACK. This function can be used to prevent overrunning available space in the FIFO. The VANC bit in the control registers, when set to a logic-1, enables insertion of ancilliary data during the vertical blanking interval (both active video and horizontal blanking portions of the line). SWITCH POINT REGISTERS 0 THROUGH 3 (Addresses 09h, 0Ah, 19h and 1Ah) The Line[10:0] and Protect[4:0] bits define the vertical switching point. The vertical switching point for component digital standard definition formats is defined in SMPTE RP 168-1993. The vertical switching point for high-definition formats has the same basic definition. However, since the vertical switching point has not been standardized among the various high-definition rasters, these registers provide a convenient means whereby the vertical switching point may be programmed by the user.
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CLC030
Device Operation
(Continued)
FORMAT REGISTERS 0 AND 1 (Addresses 0Bh and 0Ch) The CLC030 may be set to process a single video format by writing the appropriate data into the FORMAT 0 register. The Format Set[4:0] bits configure the raster format parameters to recognize and process only the specified type of standard or high definition format. These formats and codes are detailed in Table 4. Bit Format Set[4] when set indicates that HD data is to be processed. When reset, SD data is indicated. Format Set[3] when set indicates that PAL data is to be processed. When reset NTSC data is to be processed. Format Set[2:0] correspond to one of the sub-standards given in the table.
The CLC030 can automatically determine the format of the incoming parallel data. The result of this operation is stored in the FORMAT 1 register. The Format[4:0] bits identify which of the many possible video data standards that the CLC030 can process is being received. These format codes follow the same arrangement as for the Format Set[4:0] bits. These formats and codes are given in Table 4. Bit Format[4] when set indicates that HD data is being processed. When reset, SD data is indicated. Format[3] when set indicates that PAL data is being processed. When reset NTSC data is being processed. Format[2:0] correspond with one of the sub-standards given in the table.
TABLE 4. Video Raster Format Parameters Format Code [4,3,2,1,0] 00001 00010 00011 01001 01010 01011 10001 10010 10011 11001 11010 11100 11101 10100 Frame Rate 60I 60I 60I 50I 50I 50I 30I 30I 30P 25I 25P 25I 24P 60P Active Samples 2880 1920 1440 2880 1920 1440 1920 1920 1920 1920 1920 1920 1920 1280
Format SDTV, 54 SDTV, 36 SDTV, 27 SDTV, 54 SDTV, 36 SDTV, 27 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25
Spec. RP 174 SMPTE 267 SMPTE 125 ITU-R BT 601.5 ITU-R BT 601.5 ITU-R BT 601.5 SMPTE 260 SMPTE 274 SMPTE 274 SMPTE 274 SMPTE 274 SMPTE 295 SMPTE 274 SMPTE 296
Lines 525 525 525 625 625 625 1125 1125 1125 1125 1125 1250 1125 750
Active Lines 507/487* 507/487* 507/487* 577 577 577 1035 1080 1080 1080 1080 1080 1080 720
Samples 3432 2288 1716 3456 2304 1728 2200 2200 2200 2640 2640 2376 2750 1650
The HD Only bit when set to a logic-1 locks the CLC030 into the high definition data range and frequency. In systems designed to handle only high definition signals, enabling HD Only reduces the time required for the CLC030 to establish frequency lock and determine the HD format being processed. The SD Only bit when set to a logic-1 locks the CLC030 into the standard definition data ranges and frequencies. In systems designed to handle only standard definition signals, enabling SD Only reduces the time required for the CLC030 to establish frequency lock and determine the format being processed. When SD Only and HD Only are set to logic-0, the device operates in SD/HD mode. The H, V, and F bits correspond to input TRS data bits 6, 7 and 8, respectively. The meaning and function of this data is the same for both standard definition (SMPTE 125M) and high definition (SMPTE 292M luminance and colour difference) video data. Polarity is logic-1 equals HIGH-true. These bits are registered for the duration of the applicable field. TEST 0 REGISTER (Address 0Dh) The Test Pattern Select bits determine which test pattern is output when the Test Pattern Generator (TPG) mode or the Built-in Self-Test (BIST) mode is enabled. Table 5 gives the codes corresponding to the various test patterns. All HD
colour bars test patterns are BIST data. SD BIST test patterns are: NTSC, 27MHz, 4x3 Colour Bars and PAL, 27MHz, 4x3 PLL Pathological. The TPG Enable bit when set to a logic-1 enables the Test Pattern Generator function and built-in self-test (BIST). This bit is mapped to I/O port bit 7 in the default condition. The Pass/Fail bit indicates the result of the built-in self-test. This bit is a logic-1 for a pass condition. This bit is mapped to I/O port bit 6 in the default condition.
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CLC030
Device Operation
(Continued) TABLE 5. Test Pattern Selection Codes
Test Pattern Select Word Bits >
Bit 5 1=HD
Bit 4 1=Progressive 0=Interlaced 1=PAL 0=NTSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 3
Bit 2
Bit 1 00=Black 01=PLL Path. 10=EQ Path. 11=Colour Bars
Bit 0
Video Raster Standard
0=SD
1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 274M)
1125 Line, 74.25 MHz, 25 Frame Interlaced Component (SMPTE 274M)
1125 Line, 74.25 MHz, 25 Frame Interlaced Component (SMPTE 295M)
1125 Line, 74.25 MHz, 30 Frame Progressive Component (SMPTE 274M)
1125 Line, 74.25 MHz, 25 Frame Progressive Component (SMPTE 274M)
1125 Line, 74.25 MHz, 24 Frame Progressive Component (SMPTE 274M)
750 Line, 74.25 MHz, 60 Frame Progressive Component (SMPTE 296M)
19
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CLC030
Device Operation
(Continued) TABLE 5. Test Pattern Selection Codes (Continued)
Test Pattern Select Word Bits > Ref. Black PLL Path. EQ Path. Colour Bars (SD BIST) Ref. Black PLL Path. (SD BIST) EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars 525 Line, 30 Frame, 54 MHz (NTSC) Ref. Black PLL Path. EQ Path. Colour Bars 625 Line, 25 Frame, 54 MHz (PAL) Ref. Black PLL Path. EQ Path. Colour Bars
Bit 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)
625 Line, 25 Frame, 27 MHz, PAL 4x3 (ITU-T BT.601)
525 Line, 30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)
625 Line, 25 Frame, 36 MHz, PAL 16x9 (ITU-T BT.601)
Note:SD BIST patterns are NTSC 4x3 Colour Bars and PAL 4x3 PLL Pathological. HD BIST patterns are colour bars for each format.
VIDEO INFO 0 REGISTER (Address 0Eh) The NSP (New Sync Position) bit indicates that a new or out-of-place TRS character has been detected in the input data. This bit is set to a logic-1 and remains set for at least one horizontal line period or unless re-activated by a subsequent new or out-of-place TRS. It is reset by an EAV TRS character. {Activation of this function flushes the existing state of the machine reseting the EDH/CRC generator, SMPTE polynomial generator, serializer and NRZ-NRZI converter.} The EAV (end of active video) and SAV (start of active video) bits track the occurrence of the corresponding TRS characters. The lock detect indicator is registered as a control signal and is a logic-1 when the loop is locked. This bit may be programmed as an output on the multi-function I/O bus. This bit is mapped to I/O port bit 4 in the default condition. The VPG Filter Enable bit when set enables operation of the Video Pattern Generator filter. Operation of this filter causes the insertion of transition codes in the chroma and luma data of colour bar test patterns where these patterns change from
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one bar to the next. This filter reduces the magnitude of out-of-band frequency products which can be produced by abrupt transitions in the chroma and luma data when fed to D-to-A converters and picture monitors. I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h) The I/O Pin Configuration Registers are used to map the bits of the multi-function I/O port to selected bits of the Configuration and Control Registers. Table 6 gives the addresses of the Configuration and Control register functions that may be mapped to the port and their corresponding addresses. Pin[n] Config bit 5 controls whether the port pin is input or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not be configured as outputs and vice versa. Example: Program, via the AD port, I/O port bit 0 as output for the CRC Luma Error bit in the control registers. 1) Take ANC/CTRL to a logic-low. 2) Take RD/WR to a logic-low. 3) Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register
CLC030
Device Operation
(Continued)
address. 4) Toggle ACLK. 5) Present 010h to AD[9:0] as the register data, the bit address of the CRC Luma Error bit in the control registers. 6) Toggle ACLK. TABLE 6. I/O Configuration Register Addresses for Control Register Functions Bit Address Pin # SEL [n] [5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 [4]] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 [3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 [2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
21
Register Bit reserved FF Flag Error AP Flag Error ANC Flag Error CRC Error (SD/HD) reserved reserved reserved reserved reserved reserved reserved reserved SAV EAV NSP CRC Luma Error CRC Chroma Error F V H Format[0] Format[1] Format[2] Format[3] Format[4] FIFO Full FIFO Empty Lock Detect Pass/Fail FIFO Overrun ANC Chksum Error EDH Force Test Pattern Select[0] Test Pattern Select[1] Test Pattern Select[2] Test Pattern Select[3] Test Pattern Select[4] Test Pattern Select[5] EDH Enable TPG Enable reserved Chksum Attach In reserved
[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
I/P or O/P Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input
Power-On Status
I/O Port Bit 5
I/O Port Bit 0 I/O Port Bit 1 I/O Port Bit 2
I/O Port Bit 3 (SD/HD) I/O Port Bit 6 I/O Port Bit 4
I/O Port Bit 7
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CLC030
Device Operation
Register Bit VPG Filter Enable Dither Enable Framing Enable FIFO Insert Enable
(Continued)
TABLE 6. I/O Configuration Register Addresses for Control Register Functions (Continued) Bit Address Pin # SEL [n] [5] 1 1 1 1 [4]] 0 0 0 0 [3] 1 1 1 1 [2] 1 1 1 1 [1] 0 0 1 1 [0] 0 1 0 1 I/P or O/P Input Input Input Input Power-On Status
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Name VDDPLLD VSSPLLD IO0 IO1 DV0 DV1 DV2 DV3 DV4 VSSD DV5 DV6 DV7 DV8 DV9 VDDD VSSD DV10 DV11 DV12 DV13 DV14 VDDIO DV15 DV16 DV17 DV18 DV19 VSSIO IO2 IO3 IO4 IO5 IO6 IO7 ACLK VDDD AD0 AD1 AD2
Description Positive Power Supply Input (2.5V supply, PLL Logic) Negative Power Supply Input (2.5V supply, PLL Logic) Multi-Function I/O Port Multi-Function I/O Port Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Negative Power Supply Input (2.5V supply, Digital Logic) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Parallel Video Input (HD=Chroma, SD=Luma & Chroma) Positive Power Supply Input (2.5V supply, Digital Logic) Negative Power Supply Input (2.5V supply, Digital Logic) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Positive Power Supply Input (3.3V supply, I/O) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Parallel Video Input (HD=Luma) Negative Power Supply Input (3.3V supply, I/O) Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Ancilliary/Control Clock Input Positive Power Supply Input (2.5V supply, Digital Logic) Ancilliary/Control Data Input Ancilliary/Control Data Input Ancilliary/Control Data Input
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CLC030
Pin Descriptions
Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AD3 AD4 VSSD AD5 AD6 AD7 AD8 AD9 RD/WR ANC/CTRL VDDSD RREFPRE RREFLVL VSSSD VSSSD SDO VDDLS SDO VSSLS VDDZ VSSPLLA VDDPLLA VCLK Reset
(Continued) Description Ancilliary/Control Data Input Ancilliary/Control Data Input Negative Power Supply Input (2.5V supply, Digital Logic) Ancilliary/Control Data Input Ancilliary/Control Data Input Ancilliary/Control Data Input Ancilliary/Control Data Input Ancilliary/Control Data Input Ancilliary/Control Data Port Read/Write Control Input Ancilliary/Control Data Port Function Control Input Positive Power Supply Input (3.3V supply, Output Driver) Output Preemphasis Reference Resistor (4.75 K, 1% Nom.) Output Level Reference Resistor (4.75 K, 1% Nom.) Negative Power Supply Input (3.3V supply, Output Driver) Negative Power Supply Input (3.3V supply, Output Driver) Serial Data True Output Positive Power Supply Input (3.3V supply, Level Shift) Serial Data Complement Output Negative Power Supply Input (3.3V supply, Level Shift) Positive Power Supply Input (2.5V supply, Serializer) Negative Power Supply Input (2.5V supply, PLL Analog) Positive Power Supply Input (2.5V supply, PLL Analog) Video Data Clock Input Manual Reset Input (High True)
Name
Note: All LVCMOS inputs have internal pull-down devices.
Application Circuit
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CLC030
Application Information
A typical application circuit for the CLC030 is shown in the Application Circuit diagram. This circuit demonstrates the capabilities of the CLC030 and allows its evaluation in a native configuration. An assembled demonstration board is available, part number SD030EVK. The board may be ordered through any of National's sales offices. Complete circuit board layouts and schematics, including Gerber photoplot files, for the SD030EVK are available on National's WEB site in the application information for this device. For latest availability information, please see: www.national.com/ appinfo/interface. PCB Layout and Power System Bypass Recommendations Circuit board layout and stack-up for the CLC030 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 F to 0.1 F. Tantalum capacitors may be in the range 2.2 F to 10 F. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the CLC030 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional VSS (ground) plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the VSS power supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. The CLC030 uses two power supply voltages, 2.5 and 3.3 volts. These supplies connect to the device through seven sets of independent power input pins. The function and system supplied through these is given in the Pin Description Table. The power supply voltages normally share a common 0 volt or ground return system. Either a split plane or separate power planes can be used to supply the positive voltages to the device. In especially noisy power supply environments, such as is often the case when using switching power supplies, separate filtering may be used at the CLC030's PLL analog, PLL digital and serial output driver power pins. The CLC030 was designed for this situation. The digital section, PLL and output driver power supply feeds are independent. See the Pin Description Table and the Connection Diagram for details. Supply filtering may take the form of L-section or pisection, L-C filters in series with these VDD inputs. Such filters are available in a single package from several manufacturers. Despite being independent feeds, all device power supplies should be applied simultaneously as from a common source. The CLC030 is free from power supply latch-up caused by circuit-induced delays between the device's separate power feed systems.
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CLC030 SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
Physical Dimensions
inches (millimeters) unless otherwise noted
64-Pin TQPF Order Number CLC030VEC NS Package Number VEC-64A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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