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BQ4802Y/LY
Y2K-Compliant Parallel RTC with CPU Supervisor
Features
(R) Real-Time Clock counts seconds through centuries in BCD format (R) BQ4802Y--5V operation, bq4802LY--3.3V operation (R) Century register (R) On-chip battery-backup switchover circuit with nonvolatile control for external SRAM (R) Less than 500nA of clock operation current in backup mode (R) Microprocessor r e s e t push-button override with the status of its voltage supply. When the BQ4802Y/LY detects an out-oftolerance condition, it generates an interrupt warning and subsequently a microprocessor reset. The reset stays active for 200ms after VCC rises within tolerance, to allow for power supply and processor stabilization. The reset function also allows for an external push-button override The BQ4802Y/LY also has a built-in watchdog timer to monitor processor operation. If the microprocessor does not toggle the watchdog input (WDI) within the programmed time-out period, the BQ4802Y/LY asserts WDO and RST. WDI unconnected disables the watchdog timer. The BQ4802Y/LY can generate other interrupts based on a clock alarm condition, periodic setting, or watchdog timer. The alarm interrupt can be set to occur from once per second to once per month. The alarm can be made active in the battery-backup mode to serve as a system wake-up call. For interrupts at a rate beyond once per second, the periodic interrupt can be programmed with periods of 30.5s to 500ms.
General Description
The BQ4802Y/LY Real-Time Clock is a low-power microprocessor peripheral that integrates a time-of-day clock, a century based calendar, and a CPU supervisor in a 28-pin SOIC, TSSOP IC, or SNAPHAT module. The BQ4802Y/LY is ideal for fax machines, copiers, industrial control systems, point-of-sale terminals, data loggers, and computers. The BQ4802Y/LY provides direct connections for a 32.768KHz quartz crystal and a 3V backup battery. Through the use of the conditional chip enable output (CEOUT) and battery voltage output (VOUT) pins, the BQ4802Y/LY can write-protect and make nonvolatile external SRAMs. The backup cell powers the real-time clock and maintains SRAM information in the absence of system voltage. The crystal and battery are contained within the modules for a more integrated solution The BQ4802Y/LY contains a temperature-compensated reference and comparator circuit that monitors
(R) I n d e p e n d e n t watchdog t i m e r with a programmable t ime-out period (R) Power-fail interrupt warning (R) Programmable clock alarm interr u p t active in battery-backup mode (R) Programmable periodic interrupt (R) Battery-low warning (R) 28-pin SOIC, TSSOP, SNAPHAT package options and
Pin Connections
VOUT (NC) X1 (NC) X2 WDO INT RST A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CEIN CEOUT BC (NC) WDI OE CS VSS (NC) DQ7 DQ6 DQ5 DQ4 DQ3
Pin Names
A0-A3 DQ0-DQ7 WE OE CS CEIN CEOUT X1-X2 BC Clock/control address inputs Data inputs/outputs RST Write enable input Output enable input Chip select input External RAM chip enable input Conditional RAM chip enable output Crystal inputs Backup battery input WDI WDO VCC VSS NC Microprocessor reset output Watchdog input Watchdog output Input supply voltage Ground No connect VOUT INT Back-up battery output Interrupt output
28-pin, SOIC, TSSOP or SNAPHAT
PN4802.eps
SLUS464A--August 2000--Revised October 2000
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BQ4802Y/LY
Pin Descriptions
X1-X2 Crystal inputs X1-X2 are a direct connection for a 32.768kHZ, 6pF crystal. Not accessible in module packages. VSS RST Reset output RST goes low whenever VCC falls below the power fail threshold. RST will remain low for 200ms (typical) after VCC crosses the threshold on power-up. The BQ4802Y/LY will also enter the reset cycle when RST is released from being pulled low for more than 1s. INT Interrupt output INT goes low when a power fail, periodic, or alarm condition occurs. INT is an open-drain output. WDI Watchdog input WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-out period (1.5 seconds default), WDO goes low. WDO remains low until the next transition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between VOUT and VSS, which sets it to mid-supply when left unconnected. WDO Watchdog output WDO goes low if WDI remains either high or low longer than the watchdog time-out period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. A0-A3 Clock address inputs A0-A3 allow access to the 16 bytes of realtime clock and control registers. VCC CEIN CS OE DQ0-DQ7 Data input and output DQ0-DQ7 provide x8 data for real-time clock information. These pins connect to the memory data bus. Ground Chip select Output enable OE provides the read control for the RTC memory locations. CEOUT Chip enable output CEOUT goes low only when CEIN is low and VCC is above the power fail threshold. If CEIN is low, and power fail occurs, CEOUT stays low for 100s or until CEIN goes high, whichever occurs first. Chip enable input CEIN is the input to the chip-enable gating circuit. BC Backup battery input BC should be connected to a 3V backup cell. A voltage within the VBC range on the BC pin should be present upon power up to provide proper oscillator start-up. Not accessible in module packages. VOUT Output supply voltage VOUT provides the higher of VCC or VBC, switched internally, to supply external RAM. WE Write enable WE provides the write control for the RTC memory locations. Input supply voltage 5V input or 3.3V input
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BQ4802Y/LY
Functional Description
Figure 1 is a block diagram of the BQ4802Y/LY The . following sections describe the BQ4802Y/LY functional operation including clock interface, data-retention modes, power-on reset timing, watchdog timer activation, and interrupt generation.
Figure 1. Block Diagram
Truth Table
VCC < VCC (max.) CS VIH VIL > VCC (min.) < VPFD (min.) > VSO VSO VIL VIL X X OE X X VIL VIH X X WE X VIL VIH VIH X X CEOUT CE IN CEIN CEIN CEIN VOH VOHB VOUT VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT2 Mode Deselect Write Read Read Deselect Deselect DQ High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery-backup mode
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BQ4802Y/LY
Address Map
The BQ4802Y/LY provides 16 bytes of clock and control status registers. Table 1 is a map of the BQ4802Y/LY registers, and Table 2 describes the register bits.
Read Mode
The BQ4802Y/LY is in read mode whenever OE (Output enable) is low and CS (chip select) is low. The unique address, specified by the 4 address inputs, defines which one of the 16 clock/calendar bytes is to be accessed. The BQ4802Y/LY makes valid data available at the data I/O pins within t AA (address access time). This occurs after the last address input signal is stable, and providing the CS and OE (output enable) access times are met. If the CS and OE access times are not met, valid data is available after the latter of chip select access time (tACS) or output enable access time (tOE). CS and OE control the state of the eight three-state data I/O signals. If the outputs are activated before t AA,
Clock Memory Interface
The BQ4802Y/LY has the same interface for clock/calendar and control information as standard SRAM. To read and write to these locations, the user must put the BQ4802Y/LY in the proper mode and meet the timing requirements.
Table 1. BQ4802Y/LY Clock and Control Register Map
Address (h) 0 1 2 3 4 5 6 7 8 9 A B C D E F Notes: * * * * D7 0 ALM1 0 ALM1 PM/AM ALM1 PM/AM 0 ALM1 0 0 0 D6 ALM0 10-second digit 10-minute digit ALM0 10-minute digit 0 ALM0 0 ALM0 10-hour digit 10-hour digit 10-day digit 10-day digit 0 0 10 mo. 10-year digit WD2 WD1 * * * 10-century digit WD0 RS3 AIE AF UTI 0 D5 D4 D3 D2 D1 D0 12-Hour Range (h) 00-59 00-59 00-59 00-59 Register Seconds Seconds alarm Minutes Minutes alarm
10-second digit
1-second digit 1-second digit 1-minute digit 1-minute digit 1-hour digit 1-hour digit 1-day digit 1-day digit Day-of-week digit 1-month digit 1-year digit RS2 PIE PF STOP RS1 RS0
01-12 AM/ 81- 92 PM Hours 01-12 AM/ 81-92 PM Hours alarm 01-31 01-31 01-07 01-12 00-99 Day Day alarm Day-of-week Month Y ear Programmable rates Interrupt enables Flags Control Century
PWRIE ABE PWRF BVF 24/12 DSE
1-century digit
* = Unused bits; unwritable and read as 0. 0 = should be set to 0 for valid time/calendar range. Clock calendar data in BCD. Automatic leap year adjustment up to year 2100. PM/AM = 1 for PM; PM/AM = 0 for AM. DSE = 1 enables daylight savings adjustment. 24/12 = 1 enables 24-hour data representation; 24/12 = 0 enables 12-hour data representation. Day-of-Week coded as Sunday = 1 through Saturday = 7. BVF = 1 for valid battery. STOP = 1 turns the RTC on; STOP = 0 stops the RTC in back-up mode.
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BQ4802Y/LY
Reading the Clock Table 2. Clock and Control Register Bits
Bits 24/12 ABE AF AIE ALM0-ALM1 BVF DSE PF PIE PM/AM PWRF PWRIE RS0-RS3 STOP UTI WD0 - WD2 Description 24- or 12-hour representation Alarm interrupt enable in battery-backup mode Alarm interrupt flag Alarm interrupt enable Alarm mask bits Battery-valid flag Daylight savings time enable Periodic interrupt flag Periodic interrupt enable PM or AM indication Power-fail interrupt flag Power-fail interrupt enable Periodic interrupt rate Oscillator stop and start Update transfer inhibit Watchdog time-out rate The UTI bit must also be used to set the BQ4802Y/LY clock. Once set, the locations can be written with the desired information in BCD format. Resetting the UTI bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible registers to resume within one second. Once every second, the user-accessible clock/calendar locations are updated simultaneously from the internal real time counters. To prevent reading data in transition, updates to the BQ4802Y/LY clock registers should be halted. Updating is halted by setting the update transfer inhibit (UTI) bit D3 of the control register E. As long as the UTI bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory locations, the UTI bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the UTI bit, reading the clock locations has no effect on clock accuracy. Once the UTI bit is reset to 0, the internal registers update within one second t h e useraccessible registers with the correct time. A halt command issued during a clock update allows the update to occur before freezing the data.
Setting the Clock
Stopping and Starting the Clock Oscillator
The BQ4802Y/LY clock can be programmed to turn off when the part goes into battery back-up mode by setting STOP to 0 prior to power down. If the board using the BQ4802Y/LY is to spend a significant period of time in storage, the STOP bit can be used to preserve some battery capacity. STOP set to 1 keeps the clock running when VCC drops below VSO. With VCC greater than VSO, the BQ4802Y/LY clock runs regardless of the state of STOP.
the data lines are driven to an indeterminate state until t AA. If the address inputs are changed while CS and OE remain low, output data remains valid for t OH (output data hold time), but goes indeterminate until the next address access.
Write Mode
The BQ4802Y/LY is in write mode whenever WE and CS are active. The start of a write is referenced from the latter-occurring falling edge of WE or CS. A write is terminated by the earlier rising edge of WE or CS. The addresses must be held valid throughout the cycle. CS or WE must return high for a minimum of t WR2 from CS or t WR1 from WE prior to the initiation of another read or write cycle. Data-in must be valid t DW prior to the end of write and remain valid for t DH1 or t DH2 afterward. OE should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on CS and OE, a low on WE disables the outputs t WZ after WE falls.
Power-Down/Power-Up Cycle
The BQ4802Y/LY continuously monitors VCC for out-of-tolerance. During a power failure, when VCC falls below VPFD, the BQ4802Y/LY write-protects the clock and storage registers. The power source is switched to BC when VCC is less than VPFD and BC is greater than VPFD, or when VCC is less than VBC and VBC is less than VPFD. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VPFD, the power source is VCC. Write-protection continues for t CSR time after VCC rises above VPFD. An external CMOS static RAM is battery-backed using t h e VOUT a n d chip enable o u t p u t pins from t h e BQ4802Y/LY As the voltage input VCC slews down dur. ing a power failure, the chip enable output, CEOUT, is
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BQ4802Y/LY
forced inactive independent of the chip enable input CEIN. This activity unconditionally write-protects the external SRAM as VCC falls below VPFD. If a memory access is in progress to the external SRAM during power-fail detection, that memory cycle continues to completion before the memory is write-protected. If the memory cycle is not terminated within time t WPT, the chip enable output is unconditionally driven high, write-protecting the controlled SRAM. As the supply continues to fall past VPFD, an internal switching device forces VOUT to the external backup energy source. CEOUT is held high by the VOUT energy source. During power-up, VOUT is switched back to the main supply as VCC rises above the backup cell input voltage sourcing VOUT. If VPFD < VBC on the BQ4802Y/LY the switch to the main supply occurs at VPFD. CE OUT is held inactive for time t CER (200ms maximum) after the power supply has reached VPFD, independent of the CEIN input, to allow for processor stabilization. During power-valid operation, the CEIN input is passed through to the CEOUT output with a propagation delay of less than 12ns. Figure 2 shows the hardware hookup for the external RAM, battery, and crystal. A primary backup energy source input is provided on the BQ4802Y/LY The BC input accepts a 3V primary . battery, typically some type of lithium chemistry. Since the BQ4802Y/LY provides for reverse battery charging protection, no diode or current limiting resistor is needed in series with the cell. To prevent battery drain when there is no valid data to retain, VOUT and CEOUT are internally isolated from BC by the initial connection of a battery. Following the first application of VCC above VPFD, this isolation is broken, and the backup cell provides power to VOUT and CEOUT for the external SRAM. The crystal should be located as close to X1 and X2 as possible and meet the specifications in t he Crystal Specification Table. With the specified crystal, the BQ4802Y/LY RTC will be accurate to within one minute per month at room temperature. In the absence of a crystal, a 32.768 kHz waveform can be fed into X1 with X2 grounded. The power source and crystal are integrated into the SNAPHAT modules.
VCC
bq4802
Address Bus Data Bus
From
WDI
3V
bq4802.eps
Figure 2. BQ4802Y/LY Application Circuit
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BQ4802Y/LY
Power-On Reset
The BQ4802Y/LY provides a power-on reset, which pulls the RST pin low on power-down and remains low on power-up for t RST after VCC passes VPFD. With valid battery voltage on BC, RST remains valid for VCC= VSS. WD2 in register B. The BQ4802Y/LY maintains the watchdog time-out programming through power cycles. The default state (no valid battery power) of WD0-WD2 is 000 or 1.5s on power-up. Table 3 shows the programmable watchdog time-out rates. The watchdog time-out period immediately after a reset is equal to the programmed watchdog time-out. To disable the watchdog function, leave WDI floating. An internal resistor network (100k equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When VCC is below the power-fail threshold, the BQ4802Y/LY disables the watchdog function and disconnects WDI from its internal resistor network, thus making it high impedance.
Push-Button Reset
The BQ4802Y/LY also provides a push-button override to the Reset when the device is not already in a reset cycle. When the RST pin is released after being pulled low for 1s then the RST will stay low for 200ms (typical).
Watchdog Timer
The watchdog monitors microprocessor activity through the Watchdog input (WDI). To use the watchdog function, connect WDI to a bus line or a microprocessor I/O line. If WDI remains high or low for longer than the watchdog time-out period (1.5 seconds default), the BQ4802Y/LY asserts WDO and RST.
Watchdog Output
The Watchdog output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout period. The BQ4802Y/LY disables the watchdog function and WDO is a logic high when VCC is below the power fail threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog time-out period, the BQ4802Y/LY asserts RST for the reset time-out period t 1. WDO goes low and remains low until the next transition at WDI. If WDI is held high or low indefi-
Watchdog Input
The BQ4802Y/LY resets the watchdog timer if a change of state (high to low, low to high, or a minimum 100ns pulse) occurs at the Watchdog input (WDI) during the watchdog period. The watchdog time-out is set by WD0-
Figure 3. Watchdog Time-out Period and Reset Active Time
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BQ4802Y/LY
nitely, RST will generate pulses (t1 seconds wide) every t 3 seconds. Figure 3 shows the watchdog timing.
Alarm Interrupt
Registers 1, 3, 5, and 7 program the real-time clock alarm. During each update cycle, the BQ4802Y/LY compares the date, hours, minutes, and seconds in the clock registers with the corresponding alarm registers. If a match between all the corresponding bytes is found, the alarm flag AF in the flags register is set. If the alarm interrupt is enabled with AIE, an interrupt request is generated on INT. The alarm condition is cleared by a read to the flags register. ALM1 - ALM0 in the alarm registers, mask each alarm compare byte. An alarm byte is masked by setting ALM1 (D7) and ALM0 (D6) to 1. Alarm byte masking can be used to select the frequency of the alarm interrupt, according to Table 5. The alarm interrupt can be made active while the BQ4802Y/LY is in the battery-backup mode by setting ABE in the interrupts register. Normally, the INT pin goes high-impedance during battery backup. With ABE set, however, INT is driven low if an alarm condition occurs and the AIE bit is set.
Interrupts
The BQ4802Y/LY allows three individually selected interrupt events to generate an interrupt request on the INT pin. These three interrupt events are: The periodic interrupt, programmable to occur once every 30.5s to 500ms The alarm interrupt, programmable to occur once per second to once per month The power-fail interrupt, which can be enabled to be asserted when the BQ4802Y/LY detects a power failure The periodic, alarm, and power-fail interrupts are enabled by an individual interrupt-enable bit in register C, the interrupts register. When an event occurs, its event flag bit in the flags register, register D, is set. If the corresponding event enable bit is also set, then an interrupt request is generated. Reading the flags register clears all flag bits and makes INT high impedance. To reset the flag register, the BQ4802Y/LY addresses must be held stable at register D for at least 50ns to avoid inadvertent resets.
Power-Fail Interrupt
When VCC falls to the power-fail-detect point, the power-fail flag PWRF is set. If the power-fail interrupt enable bit (PWRIE) is also set, then INT is asserted low. The power-fail i n t e r r u p t occurs t WPT before t h e BQ4802Y/LY generates a reset and deselects.
Periodic Interrupt
Bits RS3-RS0 in the interrupts register program the rate for the periodic interrupt. The user can interpret the interrupt in two ways: either by polling the flags register for PF assertion or by setting PIE so that INT goes active when the BQ4802Y/LY sets the periodic flag. Reading the flags register resets the PF bit and returns INT to the high-impedance state. Table 4 shows the periodic rates.
Battery-Low Warning
The BQ4802Y/LY checks the battery on power-up. When the battery voltage is approximately 2.1V, the batteryvalid flag BVF in the flags register is set to a 0 indicating that clock and RAM data may be invalid.
Table 3. Watchdog Time-out Rates
WD2 0 0 0 0 1 1 1 1 WD1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 Normal Watchdog Time-out Period (t2, t3) 1.5s 23.4375ms 46.875ms 93.75ms 187.5ms 375ms 750ms 3s Reset Time-out Period (t1) 0.25s 3.9063ms 7.8125ms 15.625ms 31.25ms 62.5ms 125ms 0.5s
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BQ4802Y/LY
Table 4. Periodic Interrupt Rates
Register B Bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Periodic Interrupt Period None 30.5175 61.035 122.070 244.141 488.281 976.5625 1.95315 3.90625 7.8125 15.625 31.25 62.5 125 250 500 s s s s s s ms ms ms ms ms ms ms ms ms Units
Table 5. Alarm Frequency (Alarm Bits D6 and D7 of Alarm Registers)
1h ALM1 ALM0 1 0 0 0 0 3h ALM1 ALM0 1 1 0 0 0 5h ALM1 ALM0 1 1 1 0 0 7h ALM1 ALM0 1 1 1 1 0 Alarm Frequency Once per second Once per minute when seconds match Once per hour when minutes, and seconds match Once per day when hours, minutes, and seconds match When date, hours, minutes, and seconds match
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BQ4802Y/LY
Absolute Maximum Ratings
Symbol VCC VT TOPR TSTG TBIAS TSOLDER Note: Parameter DC voltage applied on VCC relative to VSS DC voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature Temperature under bias Soldering temperature Value -0.3 to 6.0 -0.3 to 6.0 0 to +70 -55 to +125 -40 to +85 +260 Unit V V C C C C For 10 seconds VT VCC + 0.3 Commercial Conditions
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (TA = TOPR)
Symbol VCC VIL VIH VBC VPBRL VPBRH Note: Parameter Supply voltage 2.7 Input low voltage Input high voltage Backup cell voltage Push button reset input low Push button reset input high -0.3 2.2 2.4 -0.3 2.2 3.3 3.6 0.8 VCC + 0.3 4.0 0.4 VCC + 0.3 V V V V V V bq4802LY Minimum 4.5 Typical 5.0 Maximum 5.5 Unit V Notes BQ4802Y
Typical values indicate operation at TA = 25C.
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BQ4802Y/LY
DC Electrical Characteristics (TA = TOPR, VCCmin
Symbol I LI I LO VOH VOHB VOL I CC I SB1 I SB2 VSO I CCB VPFD VOUT1 VOUT2 VRST VINT VWDO I WDIL I WDIH Notes: Parameter Input leakage current Output leakage current Output high voltage VOH, BC Supply Output low voltage Operating supply current Standby supply current Standby supply current Supply switch-over voltage Battery operation current Power-fail-detect voltage Minimum 2.2 VBC- 0.3 Typical 5 3 1.5 VPFD VBC 0.3 4.37 2.53 -10 20 VCC VCCmax) Unit A A V V V mA mA mA V V A V V V V A A Conditions/Notes VIN = VSS to VCC CS = VIH or OE = VIH or WE = VIL I OH = -2.0 mA VBC > VCC, IOH = -10A I OL = 4.0 mA Min. cycle, duty = 100%, CS = VIL, II/O = 0mA CS = VIH CS VCC - 0.2V, 0V VIN 0.2V, or VIN VCC - 0.2V VBC > VPFD VBC < VPFD VBC = 3V TA = 25C, no load , on VOUT or CEOUT BQ4802Y bq4802LY I OUT = 80mA, VCC > VBC I OUT = 100A, VCC < VBC I RST = 4mA I INT = 4mA I SINK = 4mA I SOURCE = 2mA 0 < VWDI < 0.8V 2.2 < VWDI < VCC
Maximum 1 1 0.4 9 0.5 4.5 2.65 0.4V 0.4V 0.4V 50
4.30 2.4 VOUT voltage VCC - 0.3V VOUT voltage VBC - 0.3V RST output voltage INT output voltage WDO output voltage 2.4 Watchdog input low current -50 Watchdog input high current -
Typical values indicate operation at TA = 25C, VCC = 3.3V. RST and INT are open-drain outputs.
Crystal Specifications (DT-26 or Equivalent)
Symbol fO CL TP k Q R1 C0 C0/C1 DL f/fO Parameter Oscillation frequency Load capacitance Temperature turnover point Parabolic curvature constant Quality factor Series resistance Shunt capacitance Capacitance ratio Drive level Aging (first year at 25C) Minimum 20 40,000 Typical 32.768 6 25 70,000 1.1 430 1 Maximum 30 -0.042 45 1.8 600 1 W ppm K pF Unit kHz pF C ppm/C
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BQ4802Y/LY
Capacitance (TA = 25C, F = 1MHz, VCC = 3.3V)
Symbol CI/O CIN Note: Parameter Input/output capacitance Input capacitance Minimum Typical Maximum 7 5 Unit pF pF Conditions Output voltage = 0V Input voltage = 0V
These parameters are sampled and not 100% tested.
AC Test Conditions--BQ4802Y/LY
Parameter Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) Test Conditions 0V to 3.0V 5ns 1.5V (unless otherwise specified) See Figures 4 and 5
+3V 962 DOUT 510 100pF DOUT 510
+3V 962
5pF
OL-24
OL-25
Figure 4. Output Load A
Figure 5. Output Load B
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BQ4802Y/LY
Read Cycle
Symbol t RC t AA t ACS t OE t CLZ t OLZ t CHZ t OHZ t OH Read cycle time Address access time Chip select access time Output enable to output valid Chip select to output in low Z Output enable to output in low Z Chip deselect to output in high Z Output disable to output in high Z Output hold from address change (TA = TOPR, VCC = 5V) Parameter Min. 200 8 0 0 0 10 Max. 100 100 100 45 45 Unit ns ns ns ns ns ns ns ns ns Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A Conditions
Write Cycle
Symbol t WC t CW t AW t AS t WP t WR1 t WR2 t DW t DH1 t DH2 t WZ t OW Notes:
(TA =TOPR , VCC = 5V) Parameter Min. 200 195 195 30 165 5 15 50 0 10 0 0 Max. 45 Unit ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) Measured from address valid to beginning of write. (2) Measured from beginning of write to end of write. (1) Measured from WE going high to end of write cycle. (3) Measured from CS going high to end of write cycle. (3) Measured to first low-to-high transition of either CS or WE. Measured from WE going high to end of write cycle. (4) Measured from CS going high to end of write cycle. (4) I/O pins are in output state. (5) I/O pins are in output state. (5) Conditions
Write cycle time Chip select to end of write Address valid to end of write Address setup time Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write
1. A write ends at the earlier transition of CS going high and WE going high. 2. A write occurs during the overlap of a low CS and a low WE. A write begins at the later transition of CS going low and WE going low. 3. Either t WR1 or t WR2 must be met. 4. Either t DH1 or t DH2 must be met. 5. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.
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BQ4802Y/LY
Read Cycle
Symbol t RC t AA t ACS t OE t CLZ t OLZ t CHZ t OHZ t OH Read cycle time Address access time Chip select access time Output enable to output valid Chip select to output in low Z Output enable to output in low Z Chip deselect to output in high Z Output disable to output in high Z Output hold from address change (TA = TOPR, VCC = 3.3V) Parameter Min. 300 15 0 0 0 18 Max. 150 150 150 60 60 Unit ns ns ns ns ns ns ns ns ns Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A Conditions
Write Cycle
Symbol t WC t CW t AW t AS t WP t WR1 t WR2 t DW t DH1 t DH2 t WZ t OW Notes:
(TA =TOPR , VCC = 3.3V) Parameter Min. 300 250 250 56 280 8 25 80 0 15 0 0 Max. 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) Measured from address valid to beginning of write. (2) Measured from beginning of write to end of write. (1) Measured from WE going high to end of write cycle. (3) Measured from CS going high to end of write cycle. (3) Measured to first low-to-high transition of either CS or WE. Measured from WE going high to end of write cycle. (4) Measured from CS going high to end of write cycle. (4) I/O pins are in output state. (5) I/O pins are in output state. (5) Conditions
Write cycle time Chip select to end of write Address valid to end of write Address setup time Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write
1. A write ends at the earlier transition of CS going high and WE going high. 2. A write occurs during the overlap of a low CS and a low WE. A write begins at the later transition of CS going low and WE going low. 3. Either t WR1 or t WR2 must be met. 4. Either t DH1 or t DH2 must be met. 5. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.
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BQ4802Y/LY
Read Cycle number 1 (Address Access) 1, 2
Read Cycle number 2 (CS Access) 1, 3, 4
tRC CS
tACS tCLZ DOUT High-Z
tCHZ
High-Z
Rc-36
Read Cycle No. 3 (OE Access)
1,5
Notes:
1. WE is held high for a read cycle. 2. Device is continuously selected: CS = OE = VIL. 3. Address is valid prior to or coincident with CS transition low. 4. OE = VIL. 5. Device is continuously selected: CS = VIL.
15
BQ4802Y/LY
Write Cycle No. 1 (WE-Controlled) 1,2,3
Write Cycle No. 2 (CS-Controlled) 1,2,3,4,5
Notes:
1. CS or WE must be high during address transition. 2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If OE is high, the I/O pins remain in a state of high impedance. 4. Either t WR1 or t WR2 must be met. 5. Either t DH1 or t DH2 must be met.
16
BQ4802Y/LY
Power-Down/Power-Up Timing (TA = TOPR)
Symbol tF t FS tR t PF Parameter VCC slew from 3.0 to 0V VCC slew from 0V to 3.0V VCC slew from VSO to VPFD(MAX) Interrupt delay from VPFD Minimum Typical Maximum 300 10 100 6 10 90 t WPT Write-protect time for external RAM 150 170 210 s 100 24 40 125 Unit s s s s s s BQ4802Y bq4802LY BQ4802Y Delay after VCC slews down past VPFD before SRAM is write-protected and RST activated. bq4802LY Delay after VCC slews down past VPFD before SRAM is write-protected and RST activated. BQ4802Y Internal write-protection period after VCC passes VPFD on power-up. bq4802LY Internal write-protection period after VCC passes VPFD on power-up. Reset active time-out period Time during which external SRAM is write-protected after VCC passes VPFD on power-up. BQ4802Y Output load A bq4802LY Output load A Conditions
100 t CSR CS at VIH after power-up 170 t RST t CER VPFD to RST inactive Chip enable recovery time t CSR t CSR -
200
300
ms
330 9 15
500 tCSR t CSR 15 25 -
ms ms ms ns ns s
t CED
Chip enable propagation delay to external SRAM Push-button low time
t PBL
1
-
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Note: Typical values indicate operation at TA = 25C.
17
BQ4802Y/LY
Power-Down/Power-Up Timing
VCC
2.8
TD4802.eps
Notes:
PWRIE set to "1" to enable power fail interrupt. RST and INT are open drain and require an external pull-up resistor.
Push-Button Reset Timing
tPBL RST VPBRL
tRST VPBRH
TD4802PRT.eps
18
BQ4802Y/LY
28-Pin SOIC (DW)
28-Pin SOIC (DW)
Dimension A A1 B C D E e H L Minimum 0.095 0.004 0.013 0.008 0.700 0.290 0.045 0.395 0.020 Maximum 0.105 0.012 0.020 0.013 0.715 0.305 0.055 0.415 0.040
All dimensions are in inches.
28-Pin TSSOP (PW)
28-Pin TSSOP (PW)
Inches Dimension A A1 B C D E e H L Min. 0.002 0.007 0.004 0.378 0.169 Max. 0.043 0.006 0.012 0.007 0.386 0.176 Millimeters Min. 0.05 0.18 0.09 9.60 4.30 Max. 1.10 0.15 0.30 0.18 9.80 4.48
0.0256BSC 0.246 0.020 0.256 0.028
0.65BSC 6.25 0.50 6.50 0.70
Notes: 1. Controlling dimension: millimeters. Inches shown for reference only. 2 'D' and 'E' do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side 3 Each lead centerline shall be located within 0.10mm of its exact true position. 4. Leads shall be coplanar within 0.08mm at the seating plane. 5 Dimension 'B' does not include dambar protrusion. The dambar protrusion(s) shall not cause the lead width to exceed 'B' maximum by more than 0.08mm. 6 Dimension applies to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 7 'A1' is defined as the distance from the seating plane to the lowest point of the package body (base plane).
19
BQ4802Y/LY
28-Pin SOIC for SNAPHAT Module
28-Pin DSH (SNAPHAT Base)
Inches Dimension A
A2 B e A C eB CP
Millimeters Min. 0.05 2.34 0.36 0.15 17.71 8.23 Max. 3.05 0.36 2.69 0.51 0.32 18.49 8.89
Min. 0.002 0.092 0.014 0.006 0.697 0.324
Max. 0.120 0.014 0.106 0.020 0.012 0.728 0.350
A1 A2 B C D E
D
N
E
H A1 L
e eB H L N CP
0.050 typ. 0.126 0.453 0.016 0 28 0.004 0.142 0.500 0.050 8
1.27 typ. 3.20 11.51 0.41 0 28 0.10 3.61 12.70 1.27 8
1 SOH
SNAPHAT Housing for SOIC-28 SNAPHAT Module
28-Pin DSH (SNAPHAT Top)
Inches
A1 A2 A A3
Millimeters Min. 6.73 6.48 0.46 21.21 14.22 15.55 3.20 2.03 Max. 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29
Dimension A A1
Min. 0.265 0.255 0.018 0.835 0.560 0.612 0.126 0.080
Max. 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
eA D
B eB
L
A2 A3 B D E
E
eA eB L
20
BQ4802Y/LY
Ordering Information
BQ4802Y/LY DSH Temperature Range:
Blank = Commercial
Package Option:
DW = 28-pin SOIC PW = 28-pin TSSOP DSH= 28-pin SNAPHAT module SOIC base
Device:
BQ4802Y Real-Time Clock with CPU Supervisor or bq4802LY 3.3V Real-Time Clock with CPU Supervisor
Note:
The SNAPHAT housing is ordered seperately under the part number bq48SH-x6 for plastic tube or bq48SH-x6TR in tape and reel form.
Caution: Do not place the SNAPHAT battery/crystal package bq48SH-x6 in conductive foam, since this will drain the lithium button-cell battery.
21
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Copyright (c)
2000, Texas Instruments Incorporated

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