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Features
* * * * * * * * * *
Single Supply Voltage Range, 2.7V to 3.6V Single Supply for Read and Write Fast Read Access Time - 70 ns Internal Program Control and Timer 8K Bytes Boot Block with Lockout Fast Erase Cycle Time - 10 Seconds Byte-by-Byte Programming - 30 s/Byte Typical Hardware Data Protection DATA Polling for End of Program Detection Low Power Dissipation - 25 mA Active Current - 50 A CMOS Standby Current * Typical 10,000 Write Cycles
Description
The AT49BV512 is a 3-volt only, 512K Flash memories organized as 65,536 words of 8 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 A. To allow for simple in-system reprogrammability, the AT49BV512 does not require high input voltages for programming. Three-volt only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing
512K (64K x 8) Single 2.7-volt Battery-VoltageTM Flash Memory AT49BV512
Pin Configurations
Pin Name A0 - A15 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
DIP Top View
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
VSOP Top View (8 x 14 mm) or TSOP Top View (8 x 20 mm) Type 1
A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
PLCC Top View
4 3 2 1 32 31 30 A12 A15 NC NC VCC WE NC I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 14 15 16 17 18 19 20 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7
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the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
VCC GND OE WE CE DATA INPUTS/OUTPUTS I/O0 - I/O7
OE, CE AND WE LOGIC
DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY (56K BYTES) OPTIONAL BOOT BLOCK (8K BYTES) FFFFH 2000H 1FFFH 0000H
Y DECODER ADDRESS INPUTS
X DECODER
Device Operation
READ: The AT49BV512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 64K bytes memory array (or 56K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical "1". The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical "0") on a byte-by-byte basis. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle.
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BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49BV512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV512 in the following ways: (a) VCC sense: if V CC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
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Command Definition (in Hex)
Command Sequence Read Chip Erase Byte Program Boot Block Lockout(1) Product ID Entry Product ID Exit(2) Product ID Exit(2) Notes: Bus Cycles 1 6 4 6 3 3 1 1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 XXXX Data DOUT AA AA AA AA AA F0 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 5555 5555 5555 5555 5555 80 A0 80 90 F0 5555 Addr 5555 AA DIN AA 2AAA 55 5555 40 2AAA 55 5555 10 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data
1. The 8K byte boot sector has the address range 0000H to 1FFFH. 2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ............................... -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC and AC Operating Range
AT49BV512-70 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 2.7V to 3.6V AT49BV512-90 0C - 70C -40C - 85C 2.7V to 3.6V AT49BV512-12 0C - 70C -40C - 85C 2.7V to 3.6V AT49BV512-15 0C - 70C -40C - 85C 2.7V to 3.6V
Operating Modes
Mode Read Program (2) Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware VIL VIL VIH A1 - A15 = V IL, A9 = VH,(3), A0 = VIL A1 - A15 = VIL, A9 = V H,(3), A0 = VIH Software(5) A0 = VIL, A1 - A15 = VIL A0 = VIH, A1 - A15 = V IL Notes: 1. 2. 3. 4. 5. X can be VIL or VIH. Refer to AC Programming Waveforms. VH = 12.0V 0.5V. Manufacturer Code: 1FH, Device Code: 03H. See details under Software Product Identification Entry/Exit. Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) CE VIL VIL VIH X X X OE VIL VIH X
(1)
WE VIH VIL X VIH X X
Ai Ai Ai X
I/O DOUT DIN High Z
X VIL VIH
High Z
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH Note:
(1)
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA
Min
Max 10 10 50 1 25 0.6
Units A A A mA mA V V
2.0 IOL = 2.1 mA IOH = -100 A; VCC = 3.0V 2.4 0.45
V V
1. In the erase mode, ICC is 50 mA.
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AC Read Characteristics
AT49BV512-70 Symbol tACC tCE (1) tOE tDF tOH
(2) (3, 4)
AT49BV512-90 Min Max 90 90 40 0 0 25
AT49BV512-12 Min Max 120 120 50 0 0 30
AT49BV512-15 Min Max 150 150 0 0 0 70 40 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 70 70
0 0 0
35 25
AC Read Waveforms(1)(2)(3)(4)
ADDRESS ADDRESS VALID
CE tCE OE tACC OUTPUT
Notes:
tDF tOH OUTPUT VALID
HIGH Z
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL - 5 pF). 4. This parameter is characterized and is not 100% tested.
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Input Test Waveforms and Measurement Level
AC DRIVING LEVELS
tR, tF < 5 ns
2.4V 1.5V 0.4V
AC MEASUREMENT LEVEL
Output Test Load
3.0V 1.8K OUTPUT PIN 1.3K 100 pF
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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AC Byte Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 100 0 0 200 100 0 200 Max Units ns ns ns ns ns ns ns ns
AC Byte Load Waveforms
WE Controlled
OE tOES ADDRESS tAS CE tCS WE tWP tDS DATA IN tWPH tDH tAH tCH tOEH
CE Controlled
OE tOES ADDRESS tAS WE tCS CE tWP tDS DATA IN tWPH tDH tAH tCH tOEH
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Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 100 100 0 200 200 10 Min Typ 30 Max Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
PROGRAM CYCLE OE
CE tWP WE tAS A0-A15 5555 tDS DATA AA 55 A0
INPUT DATA
tWPH
tBP
tAH 2AAA
tDH 5555 ADDRESS
Chip Erase Cycle Waveforms
OE
CE tWP WE tAS A0-A15 5555 tDS DATA AA BYTE 0 55 BYTE 1 80 BYTE 2 AA BYTE 3 55 BYTE 4 10 BYTE 5 tAH 2AAA tDH 5555 5555 2AAA 5555 tEC tWPH
Note:
OE must be high only when WE and CE are both low.
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Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 0 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
0
ns
Data Polling Waveforms
WE
CE tOEH OE tDH I/O7 tOE tWR
A0-A15
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 150 0 Min 0 10 Typ Max Units ns ns ns ns ns
Toggle Bit Waveforms(1)(2)(3)
WE
CE tOEH OE tDH I/O6 tOE HIGH Z tWR tOEHP
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555
Boot Block Lockout Feature Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 90 TO ADDRESS 5555
LOAD DATA 80 TO ADDRESS 5555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 5555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 40 TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
PAUSE 1 second(2)
LOAD DATA F0 TO ADDRESS 5555
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A15 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does note remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturers Code: 1FH Device Code: 03H.
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Ordering Information(1)
tACC (ns) 70 ICC (mA) Active 25 Standby 0.05 Ordering Code AT49BV512-70JC AT49BV512-70PC AT49BV512-70TC AT49BV512-70VC AT49BV512-70JI AT49BV512-70PI AT49BV512-70TI AT49BV512-70VI AT49BV512-90JC AT49BV512-90PC AT49BV512-90TC AT49BV512-90VC AT49BV512-90JI AT49BV512-90PI AT49BV512-90TI AT49BV512-90VI AT49BV512-12JC AT49BV512-12PC AT49BV512-12TC AT49BV512-12VC AT49BV512-12JI AT49BV512-12PI AT49BV512-12TI AT49BV512-12VI AT49BV512-15JC AT49BV512-15PC AT49BV512-15TC AT49BV512-15VC AT49BV512-15JI AT49BV512-15PI AT49BV512-15TI AT49BV512-15VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0C - 70C)
25
0.05
Industrial (-40C - 85C)
90
25
0.05
Commercial (0C - 70C)
25
0.05
Industrial (-40C - 85C)
120
25
0.05
Commercial (0C - 70C)
25
0.05
Industrial (-40C - 85C)
150
25
0.05
Commercial (0C - 70C)
25
0.05
Industrial (-40C - 85C)
Note:
1. The AT49BV512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring boot block protection to be in the higher address range should contact Atmel.
Package Type
32J 32P6 32T 32V 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-lead, Thin Small Outline Package (TSOP) (8 x 20 mm) 32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
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Packaging Information
32J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D2
MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
NOM - - - - - - - - - - - 1.270 TYP
MAX 3.556 2.413 - 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
A A1 A2 D D1 D2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.
E E1 E2 B B1 e
Note 2
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B
R
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32P6 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 41.783 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 42.291 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 1 Note 1 NOTE
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 32P6 REV. B
R
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32T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 7.90 0.50 NOM - - 1.00 20.00 18.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 32T REV. B
R
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32V - VSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 13.80 12.30 7.90 0.50 NOM - - 1.00 14.00 12.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 14.20 12.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) DRAWING NO. 32V REV. B
R
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Battery-Voltage TM is the trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1026E-FLASH-06/02 xM

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