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| Microcontrollers ApNote APXXXX01.EXE available AP1633 o additional file Connecting a Fast External A/D Converter on the CAPCOM- Unit Connecting an Fast External A/D Converter (800ns Conversion-Time) by using the PEC and the 50ns Resolution on the CAPCOM-Unit Harald Lehmann / Siemens Cupertino Semiconductor Group 03.96, Rel. 01 1 2 2.1 2.2 Triggering of the ADC............................................................................................... 3 Data transfer of the ADC result................................................................................ 4 The Hardware Solution ............................................................................................. 4 The Software Solution .............................................................................................. 6 AP1633 ApNote - Revision History Actual Revision : Rel.01 Previous Revison: none Page of Page of Subjects changes since last release) actual Rel. prev. Rel. Semiconductor Group 03.96, Rel. 01 Connecting an Fast External A/D Converter on the CAPCOM - Unit There are particular fast A/D converters (ADC) which are providing a result after three 800ns-cycles and then continuously every 800ns-cycle. 1 Triggering of the ADC In order to use this ADC the signal as followed has to be generated: (after falling edge a result is ready 300ns 800ns This signal will be generated with the CAPCOM unit by using the 50ns shift of each channel as followed (see also ApNote "Generation of High Resolution PWM Signals"): There are two internal scanners (parallel running) for the CAPCOM unit for the lower (0-7) and upper (8-15) channels: Scanner 1: 50ns 701234567012345670123 Scanner 2: 189111111891111118911 400ns 400ns Channel CC(0-7) Channel CC(8- T1: (T1REL: 0FFFE ; reload value for timer T1) 0FFFF 0FFFE 800ns CC1 = 0FFFF (compare value) 0FFFF 800ns CC3 = 0FFFF (compare value) 800ns CC1 AND CC3: 300ns 800ns Semiconductor Group 3 of 7 AP1633 03.97 Connecting an Fast External A/D Converter on the CAPCOM - Unit 2 2.1 Data transfer of the ADC result The Hardware Solution: The external ADC will provide a result after three cycles and then continuously every cycle. After each 800ns cycle there have to be an (external) interrupt to trigger the PEC and transfer the ADC result (8 Bit from a Port) to a location RAM (intern or extern). The external Interrupt will be generated as followed: with the falling edge of CC3 channel. Now the timing of PEC transfer can be fine tuned by selecting the Capture channel for generating the PEC. Example: Have the interrupt request flag (IR) set at the beginning at each cycle. As the previous page shows, the falling edge (CC1) will be generated when the scanner finished channel CC1/CC9. There are additional delays before the Port-pin will actually change its level: Compare match to Output:100ns plus the delay , depending on external Port-load (<50ns @100nF Port-load) 100ns + ~50ns = ~150ns For the input Capture of signals is only one delay to add on: Sample Pin to Capture IR Setting: 100ns Q T S Main cycle: (CC1 AND CC3) 300ns 800ns 300ns CC1: 800ns next cycle! 7012345670123456701234567012 1891111118911111189111111891 T Delay , depending on external Port-load (<50ns @100nF Port-load) CC1I CC7I "point of perfect timed Q Signal definitely available! S PEC transfer" 150ns (minimal PEC response time, see Note) connecting CC1IO Compare Output to CC7IO Capture Input As shown in this example, the Interrupt flag CC7IR is set before the next cycle begins! Now it can be "fine tuned" (by changing the Capture Input Channel) in respect of additional delays caused by the hardware and/or software. Semiconductor Group 4 of 7 AP1633 03.97 Connecting an Fast External A/D Converter on the CAPCOM - Unit Note: Now you have to add up only the PEC response time as is described in the User's Manual to get the timing for the transfer of the results. For example: The worst case PEC response time during internal ROM program execution adds to 9 state times (450ns @ 20 MHz CPU clock). The minimal response is 150ns, this 150ns can be incorporated in the "fine tuning", too. Semiconductor Group 5 of 7 AP1633 03.97 Connecting an Fast External A/D Converter on the CAPCOM - Unit 2.2 The Software Solution: With the following sketch is it an easy way to determine the appropriate Compare Channels for generating the interrupt to trigger the PEC-transfer. Please note that you have to start at the point where do you wish to have the PEC-transfer scheduled ("point of perfect timed PEC transfer"). 7012345670123456701234567012 1891111118911111189111111891 7012345670123456701234567012 capture Input S 1891111118911111189111111891 7012345670123456701234567012 1891111118911111189111111891 capture IR or compare match compare interrupt R 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 compare 2 Q 1891111118911111189111111891 delay for having the result from the ext. ADC settled on the Input Port output Main cycle: (CC1 AND CC3) 300ns capture channel X: "point of perfect timed PEC transfer" 150ns (minimal PEC response time, see Note) 1 Q R S Here you pick then the Compare-Channel (Channel or 9) Compare match to Output(100ns) + delay for switching the transistor (<50ns @100nF load) = 150ns Compare match to IR: 50ns Sample Pin to Capture IR Setting = 100ns CAP/COM Scan Mechanism Overview Now it can be "fine tuned" (by changing the Compare-Channel) in respect of additional delays caused by the hardware and/or software. Note: Now you have to add up only the PEC response time as is described in the User's Manual to get the timing for the transfer of the results. Semiconductor Group 6 of 7 AP1633 03.97 Connecting an Fast External A/D Converter on the CAPCOM - Unit For example: The worst case PEC response time during internal ROM program execution adds to 9 state times (450ns @ 20 MHz CPU clock). The minimal response is 150ns, this 150ns can be incorporated in the "fine tuning", Semiconductor Group 7 of 7 AP1633 03.97 |
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