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| Microcontrollers ApNote AP162601.EXE available AP1626 additional file Software emulation of the I 2C-bus using the High-Speed Synchronous Serial Interface of C166 family This is a software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of the C166 family to generate the clock and data. The I 2C-bus is used in many applications mainly to communicate between devices connected to the bus. Author: Tan Choon Hock / SCPL HL RM LAB Semiconductor Group 2.97, Rel. 01 Software emulation of I C-bus using High-Speed Synchronous Serial Interface of C166 family 2 1 Introduction to I 2C-bus.................................................................................................. 3 2 2 I C-bus Specifications .................................................................................................. 3 2.1 Data Transfer Formats ................................................................................................. 3 2.2 Timing Diagram ............................................................................................................ 7 2.3 Hardware Connection................................................................................................... 9 3 Software Description .................................................................................................. 10 3.1 Software Concept....................................................................................................... 10 3.2 Description of Module Subroutines ............................................................................ 12 3.3 Software Compilation ................................................................................................. 17 AP1626 ApNote - Revision History Actual Revision : Rel. 01 Previous Revision: none (Original Version) Page of Page of actual Rel. prev. Rel. Semiconductor Group 2 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family 1 Introduction to I 2C-bus The I 2C-bus or Inter-Integrated Circuit bus has been developed by Philips. It allows integrated circuits to communicate directly with each other via a simple bi-directional 2wire bus. The two bus lines are serial clock line (SCL), and serial data line (SDA). 2 Nowadays, the I C-bus becomes a standard bus system which is used in consumer electronics, telecommunications, and industrial electronics. This software module of I 2Cbus emulation supports the single master protocol only. It is using the High-Speed Synchronous Serial Interface to generate clock, and transmit or receive the data. The clock frequency of the I 2C-bus can achieve up to 100 KHz with 20 MHz CPU of the C16x microcontroller. 2 2.1 2 I C-bus Specifications Data Transfer formats A HIGH-to-LOW transition of the data line (SDA) while the clock line (SCL) is HIGH indicates a START condition. A LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP condition. The data line can only be changed when the clock signal on the SCL line is LOW. Therefore, the data on the SDA line must be stable during the HIGH period of the clock signal. The bus is considered to be busy after the Start condition and is considered to be free at a certain time interval after the STOP condition. Each information puts on the SDA line must be 8-bit long. The data is transferred serially with the most significant bit first, and followed by an acknowledge bit. The 9th clock pulse of the acknowledge bit is generated by the master. The transmitting device has to release the SDA line (HIGH or in the high impedance state) during this clock pulse while the device that needs to acknowledge has to pull down the SDA line during this clock pulse. The number of data bytes transferred between the START and STOP condition from the transmitter and receiver is not limited. The receiver is obliged to generate an acknowledge bit after each byte of data that has been received. When the receiver does not provide an acknowledge bit after having received a byte of data, the data line must be left HIGH or in the high impedance state by the slave. The master can then generate a STOP condition to abort the transfer. One of the reasons for the receiver not providing the acknowledge bit is that the receiver is performing some real-time function. If the master is receiving data, it must signal the end of the data to the slave by not generating an acknowledge bit on the last byte of data received. Then, the slave must release the data line to allow the master to generate the STOP condition. Semiconductor Group 3 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family A complete data transfer format is shown in Figure 1. After a START condition, a slave address is sent. The address is 7 bits long followed by an 8th bit which is a data direction bit (R/W). A "0" for data direction bit indicates a transmission (WRITE), and a "1" indicates a request for data (READ). Figure 2 shows the I 2C-bus data transfer format of writing data from master to slave device. Figure 3 shows the data transfer format of reading data from the slave device. A data transfer is always terminated by STOP condition generated by the master. However, if the master still wishes to communicate on the bus, it can generate a repeated START condition and address the same device or another slave device without first generating a STOP condition. This combined data transfer format is shown in figure 4. SCL 1-7 SDA 8 9 1-7 8 9 1-7 8 9 Start Condition Address R/W Ack Data Ack Data Ack Stop Condition AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAA A AAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA A AAAAAAAA AAAAAAAA A AAAA AAAAAAAA SlaveAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA P AAAA AAAAAAAA AAAAAAAA AAAAAAAA S AAAAAAAA Address AAAA R/W Data AA Data A/NA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAA A AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA A AAAAAAAA AAAA Start-Frame Read- or W rite-Frame Stop-Frame Transfer-Frame AAAAAAAA AAAAAAAA AAAAAAAA from master to slave. AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA from master to slave or AAAAAAAA AAAAAAAA AAAAAAAA form slave to master depends AAAAAAAA AAAAAAAA of the R /W bit. from slave to master. A/NA = Acknowledge.(SDA = LOW ) or not acknowledge(SDA = HIGH) if it is the last data to be read by master. Figure 1: A complete data transfer format of I 2C-bus Semiconductor Group 4 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family AAAAAAAA AAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAA Address AAAAAAA AAAAS AAAASlaveAAAAAAAAAAA R/W A AAAAAAAA AAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA Data Data P AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA Data transfer (n bytes + acknowledge) 0 (WRITE) AAAAAAA AAAAAAA AAAAAAA AAAAAAA From master to slave. From slave to master. Figure 2: I 2C-bus data transfer format of writing data to slave AAAAAAAAA AAAAAAAAAAAAAAA AAA AAAA AAAAAAA AAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAA AAAA AAAA AAAAS AAAASlaveAAAAAAAAAAA R/W A Address AAAAAAA AAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAA AAAAAAAAA AAAAAAAAAAAAAAA AAA AAAA AAAAAAA AAAAAAAAA AAAA AAAA Data AAAAAAA AAAAAAA AAAAAAA A AAAAAAA AAAAAAA AAAAAAA Data AAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAA P NA AAAAAAAA AAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAA AAAAAAAA Data transfer (n bytes + aknowledge) 1 (READ) AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA From master to slave. From slave to master. NA -- not acknowledge for the last data to be received. (SDA = HIGH) Figure 3: I 2C-bus data transfer format of reading data from slave Semiconductor Group 5 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family AAA AAAAAAA AAAAAAAAAAAAAAA AAA AAAA AAAA AAAAAAA AAAAAAAAAAAAAAA AAA AAAA AAAAAAA Slave1 A ddress AAAAAAA A S AAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAAAAAAAAAA R/W AAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAA AAAA AAAA read or w rite D ata D ata AAAA A /N AAAAAAAA Slave1 AAAAAAAAAAA AAA A Sr AAAAAAAAAAAAAAAAAAA AAA R/W AAAAAAAA A ddress AAAA AAAAAAA AAAAAAAAAAAAAAAAAAA AAA AAAAAAA AAAA AAAAAAA AAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAA AAAAAAAAAAAAAAAAAAA AAA AAAA (n bytes + ack.) read or w rite Sr = repeated STA RT condition AAAAAAA AAAAAAA A /N A AAAAAAA P AAAAAAA AAAAAAA AAAAAAA (n bytes + ack.) AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA From m aster to slave. Transfer dirction of data and acknow ledge bit depend on R/W bit. A /N A = acknow ledge. (SD A = LO W ) or not acknow ledge (SD A = H IG H ) if it is the last data to be read by m aster. Figure 4: 2 A combined data transfer format for I C-bus Semiconductor Group 6 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family 2.2 Timing Diagram 2 The clock frequency of SCL is in the range of 0 up to 100 KHz. The clock on the I C-bus has a minimum LOW period of 4.7 s , and a minimum HIGH period of 4.0 s. Occasionally, the slave device may slow down the transmission by holding the clock line low after receiving a byte of data from microcontroller. This event is defined as a WAIT condition. Therefore, the master needs to switch the SCL output to high impedance and read the SCL line before transmitting another byte of data to the slave device. Figure 5 shows the data transfer timing requirements in detail. The description of the abbreviations used is shown in the Table 1. The minimum timing requirements are needed to be fulfilled in order for I 2C-bus to operate properly. tR Stop Start tF Repeat Start Stop SCL tHIGH t LOW tHD;STA SD A t BUF t HD;STA t HD;DAT t SU;DAT tSU;STA tSU;STO Figure 5: I 2C-bus timing diagram Semiconductor Group 7 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family Table 1: Abbreviation for I 2C-bus timing diagram Parameter Symbol Limit Values min. 1. Bus free time between a STOP and START condition 2. Hold time for START condition. After this period, the first pulse is generated. 3. The HIGH period of SCL clock. 4. The LOW period of SCL clock. 5. Data hold time 6. Rise time for both SCL and SDA signals. 7. Fall time for both SCL and SDA signals. 8. Data set-up time 9. Set-up time for a repeated START condition. 10. Set-up time for STOP condition. 11. SCL clcok frequency 12. Capacitor load for each bus line tBUF tHD;STA tHIGH tLOW tHD;DAT tR tF tSU;DAT tSU;STA tSU;STO fSCL Cb 250 4.7 4.0 0 100 400 4.7 4.0 4.0 4.7 0* 1.0 300 max. s s s s s s ns ns s s KHz pF Unit * A device must internally provide a hold time of at least 300 ns for SDA signal in order to bridge the undefined region of the falling edge of SCL. Semiconductor Group 8 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family 2.3 Hardware Connection Every device connected to the I 2C-bus must have an open drain/open collector output for both the clock (SCL) and data (SDA) lines. Each of the lines is connected to the VDD supply via a common pull-up resistor of 10 K in value. The connection among master and many slave devices is shown in figure 6. The number of devices that can be connected to the I 2C-bus is limited only by the maximum bus load capacitance of 400 pF. V DD 10K 10K ( S C L K ) P 3 .1 3 ( M T S R ) P 3 .9 ( M R S T ) P 3 .8 SC L SD A S la v e 1 C 16X C SC L SD A S la v e n Figure 6: Hardware connection among master and slave devices Semiconductor Group 9 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family 3 3.1 Software Description Software Concept The clock and data of the I 2C-bus are generated by the High-Speed Synchronous Serial Interface of the C16x microcontroller. The clock frequency of the I 2C-bus is 100 KHz with 20 MHz CPU of the microcontroller. The baud rate generator for the SCL line can be determined by the following formula: BSSC = fCPU 2 * ( ) -1 Semiconductor Group 10 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family The I2C_SW.C software module is divided into 5 software subroutines which can be accessed by the main or external program. Those 5 software subroutines are used to construct the data transfer format of the I 2C-bus. Those 5 software subroutines are I2cInit, I2cStart, I2cMasterWrite, I2cMasterRead, and I2cStop. The two types of data transfer format (master write, and master read/combined format) are written in the HSSCTEST.C. The HSSCTEST.C is a simple test program which just to verify the I2C_HSSC.C software module. This test program is to transmit 10 bytes of data to E2PROM IC from the array location of the microcontroller. The 10 bytes of data will be stored in the word address 0 to 9 of the E2PROM IC. Next, the microcontroller will read back the contents of the 10 bytes from the word address 0 to 9 of the E2PROM IC and then store it into another array location of the microcontroller. Semiconductor Group 11 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family 3.2 Description of Module Subroutines I2 C-BUS Software Module Source file: Header file: I2C_HSSC.C Description This module is a standard I 2C-bus single master protocol by using High-Speed Synchronous Serial Interface of the C16x microcontroller. The clock and as well as transmit/receive data are handled by the hardware peripheral of HS-SSC. Module Subroutines 1. void Delay(unsigned int count); 2. unsigned char Check_SCL(); 3. unsigned char I2cInit(); 4. void I2cStart(); 5. unsigned char I2cMasterWrite(unsigned char input_byte); 6. unsigned char I2cMasterRead(unsigned char ack); 7. unsigned char I2cStop(); void Delay(unsigned int count) To generate START and STOP condition, and 9th clock pulse. Parameter unsigned int count Description number of count for time delay. Semiconductor Group 12 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family unsigned char Check_SCL() Send HIGH and read the SCL line. It will wait until the line has been released from slave device with the time-out of 10 ms. Parameter None Description Return The return value is "0" if the clock and data lines have no problem. Otherwise, the return value will be "1". unsigned char I2cInit() Initialize the I 2C-bus. P3.8 = MRST, P3.9 = MTSR, P3.13 = SCL. The MRST and MTSR are connected together for I 2C operation. Configure the High-Speed Synchronous Serial interface to generate 100 Kbaud clock frequency and set the control register to produce a 8 bit data with MSB first, in master mode, shift transmit data on the leading clock edge, latch on trailing edge, idle clock line is low, and leading clock edge is low-to-high transition. It also check the clock and data lines for any bus faulty like no pull-up resistor on SDA/SCL or pull-down to low by the slave device. Parameter None Description Return The return value is "0" if the clock and data lines have no problem. Otherwise, the return value will be "1". void I2cStart() Generate a START condition on I 2C-bus. Parameter None Description Semiconductor Group 13 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family unsigned char I2cMasterWrite(unsigned char input_byte) Output one byte of data to the slave device. Parameter unsigned char Description one byte of data to be sent to slave device. input_byte Return If the return value is "0", writing one byte of data to slave device is successfully. Otherwise, one byte of data is needed to be sent again because there is no acknowledge from the slave device. unsigned char I2cMasterRead(unsigned char ack) Read one byte of data from the slave device. Parameter unsigned char ack Description "0" - generate LOW output by the master after a byte of data is received. "1" - generate HIGH output by the master after a byte of data is received. Return If the return value is "0", reaing one byte of data from slave device is successfully. Otherwise, one byte of data is needed to be received again because there is no acknowledge from the slave device. unsigned char I2cStop() Generate a STOP condition on the I 2C-bus. In addition, it will generate clock pulses until the line is released by the slave device and the time-out is 10 ms before returning a "HIGH" value indicating an error. Parameter None Description Return The return value is "0" if the clock and data lines have no problem. Otherwise, the return value will be "1". Semiconductor Group 14 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family I2 C-BUS Application Software Source file: Header file: HSSCTEST.C I2C_HSSC.H Description This program is just for testing only. The purpose of this program is to make use of the standard I 2C protocol module (I2C_HSSC.C) to control the nonvolatile memory (E2PROM). This program writes 10 bytes of data into E2PROM in sequence and the data is retrieved from the array location of microcontroller. Then read back 10 bytes of data from the E2PROM at the same location to which they have been programmed and store them in the array location of microcontroller. Software subroutines 1. unsigned char CheckWrite(); 2. unsigned char WriteE2prom(unsigned char sub_addr,unsigned char *buffer,unsigned 3. unsigned char ReadE2prom (unsigned char sub_addr,unsigned char *buffer,unsigned address, signed int char count); address,signed int char count); unsigned char CheckWrite() Check for the completion of programming after the memory write. If the programming is completed, the acknowledge bit will be "0". Parameter None Description Return If the return value is "0", the programming of E2PROM is consider done. Otherwise, the programming of E2PROM is still in progress. Semiconductor Group 15 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family unsigned char WriteE2prom(unsigned char adress, signed int sub_addr,unsigned char *buffer,unsigned char count) Write number of data bytes to E2PROM. The flow of this subroutine is derived from the data format of writing to the E2PROM as in the figure 2. Parameter unsigned char address signed int sub_addr unsigned char *buffer unsigned char count Description specifies the slave device address specifies the sub-address/word address point to the location of data to be sent number of bytes to be sent Return If the return value is "0", the programming of E2PROM is completed. Otherwise, the data is needed to be sent again because there is no acknowledge from slave device. unsigned char ReadE2prom(unsigned char address, signed int sub_addr,unsigned char *buffer,unsigned char count) Read number of data bytes from E2PROM. The flow of this subroutine is derived from the data format of reading from the E2PROM as in the figure 3. Parameter unsigned char address signed int sub_addr unsigned char *buffer unsigned char count Description specifies the slave device address specifies the sub-address point to the location of data to be stored number of bytes to be received Return If the return value is "0", the reading of E2PROM is completed. Otherwise, the data is needed to be sent again because there is no acknowledge from slave device. Semiconductor Group 16 of 17 AP1626 2.97 Software emulation of I 2C-bus using High-Speed Synchronous Serial Interface of C166 family 3.3 Software Compilation The compilation of this software is using the KEIL C166 compiler. Firsts of all, under the PROJECT menu, clicks on the "New Project", then key in the name of this project and add files to the project which are the I2C_HSSC.C and HSSCTEST.C. Then, save the project. After-that, go to the OPTIONS menu and click on the "C166 Compiler..." . Lastly, select the option under OBJECT and cross the box under "Enable 80C167 instructions". This option will allow you to use the C16x derivatives. Now the project is really to compile and link all the object files. The compiling and linking of the project can be done by clicking the icon "BUILD ALL". The AP162601.EXE is a compressed file and contains I2C_HSSC.H, I2C_HSSC.C, and HSSCTEST.C. All these files are necessary to complete the compilation of the software program. Semiconductor Group 17 of 17 AP1626 2.97 |
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