View AP162401_974630.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Microcontrollers ApNote
AP162401.EXE available
AP1624
additional file
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the C166 family
This is a software emulation of the I2C-bus by using two general purpose timers of a microcontroller from the C166 family. The I2C-bus is used in many applications mainly to communicate between devices connected to the bus.
Author: Tan Choon Hock / SCPL HL RM LAB
Semiconductor Group
1.97, Rel. 01
Software emulation of the I C-bus using the General Purpose Timer unit 1 of the 166 family
2
1 Introduction to I2C-bus ................................................................................................ 3 2 I2C-bus Specifications ................................................................................................. 3 2.1 Data Transfer Formats................................................................................................. 3 2.2 Timing Diagram............................................................................................................ 6 2.3 Hardware Connection .................................................................................................. 8 3 Software Description .................................................................................................... 9 3.1 Software Concept......................................................................................................... 9 3.2 Description of Module Subroutines............................................................................ 10 3.3 Software Compilation................................................................................................. 15
AP1624 ApNote - Revision History Actual Revision : Rel. 01 Previous Revision: none (Original Version) Page of Page of actual Rel. prev. Rel.
Semiconductor Group
2 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
1
Introduction to I2C-bus
The I2C-bus or Inter-Integrated Circuit bus has been developed by Philips. It allows integrated circuits to communicate directly with each other via a simple bi-directional 2wire bus. The two bus lines are serial clock line (SCL), and serial data line (SDA). 2 Nowadays, the I C-bus becomes a standard bus system which is used in consumer electronics, telecommunications, and industrial electronics. This software module for I2Cbus emulation supports the single master protocol only. It is using a timer interrupt to generate clock and transmit or receive the data. The clock frequency of the I2C-bus can achieve up to 100 KHz with 20 MHz CPU of the C16x microcontroller.
2 2.1
I2C-bus Specification Data Transfer formats
A HIGH-to-LOW transition of the data line (SDA) while the clock line (SCL) is HIGH indicates a START condition. A LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP condition. The data line can only be changed when the clock signal on the SCL line is LOW. Therefore, the data on the SDA line must be stable during the HIGH period of the clock signal. The bus is considered to be busy after the START condition and is considered to be free at a certain time interval after the STOP condition. Each information put on the SDA line must be 8-bit long. The data is transferred serially with the most significant bit first, and followed by an acknowledge bit. The 9th clock pulse of the acknowledge bit is generated by the master. The transmitting device has to release the SDA line (HIGH or in the high impedance state) during this clock pulse while the device that needs to acknowledge has to pull down the SDA line during this clock pulse. The number of data bytes transferred between the START and STOP condition from the transmitter and receiver is not limited. The receiver is obliged to generate an acknowledge bit after each byte of data that has been received. When the receiver does not provide an acknowledge bit after having received a byte of data, the data line must be left HIGH or in the high impedance state by the slave. The master can then generate a STOP condition to abort the transfer. One of the reasons for the receiver not to provide the acknowledge bit is that the receiver is performing some real- time function. If the master is receiving data, it must signal the end of the data to the slave by not generating an acknowledge bit on the last byte of data received. Then, the slave must release the data line to allow the master to generate the STOP condition.
Semiconductor Group
3 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
A complete data transfer format is shown in Figure #1. After a START condition, a slave address is sent. The address is 7 bits long followed by an 8th bit which is a data direction bit (R/W). A "0" for data direction bit indicates a transmission (WRITE), and a "1" indicates a request for data (READ). Figure #2 shows the I2C-bus data transfer format of writing data from master to slave device. Figure #3 shows the data transfer format of reading data from the slave device. A data transfer is always terminated by a STOP condition generated by the master. However, if the master still wishes to communicate on the bus, it can generate a repeated START condition and address the same device or another slave device without first generating a STOP condition. This combined data transfer format is shown in figure #4.
SCL 1-7 SDA 8 9 1-7 8 9 1-7 8 9
Start Condition
Address
R/W
Ack
Data
Ack
Data
Ack
Stop Condition
AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAA AAAA A AAAAAAAA AAAAAAAA AAAAAAAA SlaveAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAA AAAAAAAA S AAAAAAAA A ddress AAAA R/W Data AA Data A/NA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA PAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAA AAAAAAAA AAAA
Start-Frame Read- or W rite-Frame Stop-Frame
Transfer-Fram e
AAAAAAA AAAAAAA AAAAAAA from master to slave. AAAAAAA AAAAAAA AAAAAAA
AAAAAAAA AAAAAAAA from master to slave or AAAAAAAA AAAAAAAA form slave to master depends AAAAAAAA AAAAAAAA
of the R/W bit.
from slave to master.
A/NA = A cknowledge.(SDA = LOW ) or not acknow ledge(SDA = HIGH) if it is the last data to be read by master.
Figure 1: A complete data transfer format of I2C-bus
Semiconductor Group
4 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
AAAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAAA SlaveAAAAAAAAAAA R/W A AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAA S AAAAAAAA Address AAAAAA Data AAAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAA Data P AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Data transfer (n bytes + acknowledge) 0 (WRITE)
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
From master to slave.
From slave to m aster.
Figure 2: I2C-bus data transfer format of writing data to slave
AAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAA Slave AAAAAAAAAAAR/W A AAAA S AAAAAAAA Address AAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAA AAAAAAAAAAAAAAA AA AAAA AAAAAAAAAAAAAAAAAAA AA AAAAAA AAAA AAAAAA
Data
AAAAAAA AAAAAAA AAAAAAA A AAAAAAA AAAAAAA AAAAAAA
Data
AAAAAAA AAAAAAAA AAAAAAA AAAAAAAA AAAAAAA PAAAA NA AAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAA AAAAAAA AAAAAAAA
Data transfer (n bytes + acknowledge) 1 (READ)
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
From master to slave.
From slave to m aster.
NA -- not acknowledge for the last data to be received. (SDA = HIGH)
Figure 3:
2 I C-bus data transfer format of reading data from slave
Semiconductor Group
5 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
AAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAA AAAAAAAAAAAAAAA AA AAAA AAAA AAAAAA Slave1AAAAAAAAAAAR/W A AAAA S AAAA AAAAAA AAAAAAAAAAAAAAA AA AAAAAAAA Address AAAAAA AAAAAA AAAAAAAAAAAAAAA AAAA AAAAAA
read or write Data A/NA AAAAAA P
Data
A/NAAAAAAAA Slave1 AddressAAAA AAA A Sr AAAAAAAAAAAAAAAA AAAA R/W
AAAAAAA AAAAAAAAAAAAAAAA AAA AAAA AAAA AAAAAAA AAAAAAAAAAAAAAAA AAA AAAA AAAA AAAAAAA AAAAAAAAAAAAAAAA AAA AAAA AAAA AAAAAAA AAAAAAAAAAAAAAAA AAA AAAA AAAA
(n bytes + ack.)
read or w rite Sr = repeated START condition
AAAAAA AAAAAA AAAAAA AAAAAA
(n bytes + ack.)
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
From master to slave.
Transfer dirction of data and acknow ledge bit depend on R /W bit.
A/NA = acknowledge. (SDA = LOW ) or not acknowledge (SD A = HIGH) if it is the last data to be read by master.
Figure 4: A combined data transfer format for I2C-bus
Semiconductor Group
6 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
2.2
Timing Diagram
The clock frequency of SCL is in the range of 0 up to 100 KHz. The clock on the I2C-bus has a minimum LOW period of 4.7s, and a minimum HIGH period of 4.0s. Occasionally, the slave device may slow down the transmission by holding the clock line low after receiving a byte of data from microcontroller. This event is defined as a WAIT condition. Therefore, the master needs to switch the SCL output to high impedance and read the SCL line before transmitting another byte of data to the slave device. Figure #5 shows the data transfer timing requirements in detail. The description of the abbreviations used is shown in the Table #1. The minimum timing requirements are needed to be fulfilled in order for I2C-bus to operate properly.
tR
Stop Start
tF
Repeat Start Stop
SCL
tHIGH
t LOW
tHD;STA
SDA
tBUF tHD;STA
t HD;DAT
tSU;DAT tSU;STA t SU;STO
Figure 5: I2C-bus timing diagram
Semiconductor Group
7 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
Table 1: Abbreviation for I2C-bus timing diagram Parameter Symbol Limit Values min. 1. Bus free time between a STOP and START condition 2. Hold time for START condition. After this period, the first pulse is generated. 3. The HIGH period of SCL clock. 4. The LOW period of SCL clock. 5. Data hold time 6. Rise time for both SCL and SDA signals. 7. Fall time for both SCL and SDA signals. 8. Data set-up time 9. Set-up time for a repeated START condition. 10. Set-up time for STOP condition. 11. SCL clcok frequency 12. Capacitor load for each bus line tBUF tHD;STA tHIGH tLOW tHD;DAT tR tF tSU;DAT tSU;STA tSU;STO 0 Cb 250 4.7 4.0 100 400 4.7 4.0 4.0 4.7 0* 1.0 300 max. s s s s s s ns ns s s KHz pF Unit
* A device must internally provide a hold time of at least 300 ns for SDA signal in order to bridge the undefined region of the falling edge of SCL.
Semiconductor Group
8 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
2.3
Hardware Connection
Every device connected to the I2C-bus must have an open drain/open collector output for both the clock (SCL) and data (SDA) lines. Each of the lines is connected to the VDD supply via a common pull-up resistor of 10K in value. The connection among master and many slave devices is shown in Figure 6. The number of devices that can be 2 connected to the I C-bus is limited only by the maximum bus load capacitance of 400pF.
V DD 10K 10K
S C L ( P 3 .2 ) S D A ( P 3 .3 )
SC L SD A
S la v e 1 C 16x C
SC L SD A
S la v e n
Figure 6: Hardware connection among master and slave devices
Semiconductor Group
9 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
3 3.1
Software Description Software Concept
The clock and data of the I2C-bus are generated by the timer T3 interrupt of the C16x microcontroller. The clock frequency of the I2C-bus is 100 KHz with 20 MHz CPU of the microcontroller. A reload mode for the timer is required to generate a clock frequency of 100KHz. The reload mode requires two general purpose timers; one of the timer is used as the core timer (T3) with 400ns resolution, the other timer is the auxiliary timer in reload mode (T2). The reload value for the T2 timer is 24 which will generate an interrupt every 10s/100KHz((24+1)*400ns) in count-down mode. A complete cycle of the clock will be generated within the timer interrupt service routine. The priority of the timer interrupt is at the lowest which can be changed depending on the priority in your application. The I2C_HW.C software module is divided into 5 software subroutines which can be accessed by the main or external program. Those 5 software subroutines are used to 2 2 construct the data transfer format of the I C-bus. Those 5 software subroutines are I CInit, I2CStart, I2CMasterWrite, I2CMasterRead, and I2CStop. The two types of data transfer format (master write, and master read/combined format) are written in the I2CHW_TS.C. The I2CHW_TS.C is a simple test program which just to verify the I2C_HW.C software module. This test program transmits 10 bytes of data to an E2PROM IC from the array location of the microcontroller. The 10 bytes of data will be stored in the word address 0 to 9 of the E2PROM IC. Next, the microcontroller will read back the contents of the 10 bytes from the word address 0 to 9 of the E2PROM IC and then store it into another array location of the microcontroller.
Semiconductor Group
10 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
3.2
Description of Module Subroutines
I2C-BUS Software Module
Source file: Header file: User definition file: I2C_HW.C I2C.DEF
Description This module is a standard I2C-bus single master protocol by using timer T3 interrupt. The clock as well as transmit/receive data are handled by the timer interrupt.
Module Subroutines 1. void Delay(unsigned int count); 2. unsigned char Check_SCL(); 3. unsigned char I2CInit(); 4. void I2CStart(); 5. void I2CMasterWrite(unsigned char input_byte); 6. void I2CMasterRead(unsigned char ack); 7. unsigned char I2CStop();
void Delay(unsigned int count) To create time delay for clock and data signal. Parameter unsigned int count Description number of count for time delay.
Semiconductor Group
11 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
unsigned char Check_SCL() Send HIGH and read the SCL line. It will wait until the line has been released from slave device with the time-out of 10 ms.
Parameter None
Description
Return The return value is "0" if the clock and data lines have no problem. Otherwise, the return value will be "1".
unsigned char I2CInit() Set up timer in reload mode which requires two timers; T2 as the reload timer, and T3 as the core timer. Those two timers will act like a reload timer and have an resolution of 100 KHz.(1/(400ns * 25)). After that, check the clock and data lines for any bus faulty like no pull-up resistor on SDA/SCL or pull-down to low by the slave device. Parameter None Description
Return The return value is "0" if the clock and data lines have no problem. Otherwise, the return value will be "1".
void I2CStart() Generate a START condition on I2C- bus. Parameter None Description
Semiconductor Group
12 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
void I2CMasterWrite(unsigned char input_byte) Check for any WAIT condition before writing one byte of data to the slave device. Set-up the first bit of data right after the START condition.
Parameter Description unsigned char input_byte one byte of data to be sent to slave.
void I2CMasterRead(unsigned char ack) Check for WAIT condition before reading one byte of data from the slave device. Parameter unsigned char ack Description
"0" - generate LOW output by the master after a byte of data is received. "1" - generate HIGH output by the master after a byte of data is received.
unsigned char I2CStop() Generate a STOP condition on the I2C bus. In addition, it will generate clock pulses until the line is released by the slave device and the time-out is 10 ms before returning a "HIGH" value indicating an error. Parameter None Description
Return The return value is "0" if the clock and data lines have no problem. Otherwise, the return value will be "1".
Semiconductor Group
13 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
I2C-BUS Application Software
Source file: Header file: I2CHW_TS.C I2C_HW.H
Description This program is for testing only. The purpose of this program is to make use of the standard I2C protocol module (I2C_HW.C) to control the nonvolatile memory (E2PROM). This program writes 10 bytes of data into the E2PROM in sequence and the data is retrieved from the array location of the microcontroller. Then read back 10 bytes of data from the E2PROM at the same location to which they have been programmed and store it in the array location of the microcontroller.
Software subroutines 1. unsigned char CheckWrite() 2. unsigned char WriteE2prom(unsigned char address,signed int sub_addr,unsigned char *buffer,unsigned char count) 3. unsigned char ReadE2prom (unsigned char address,signed int sub_addr,unsigned char *buffer,unsigned char count)
unsigned char CheckWrite() Check for the completion of programming after the memory write. If the programming is completed, the acknowledge bit will be "0". Parameter None Return If the return value is "0", the programming of E2PROM is considered to be done. Otherwise, the programming of E2PROM is still in progress. Description
Semiconductor Group
14 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
unsigned char WriteE2prom(unsigned char adress, signed int sub_addr,unsigned char *buffer,unsigned char count) Write number of data bytes to E2PROM. The flow of this subroutine is derived from the data format of writing to the E2PROM as in the figure #2. Parameter unsigned char address signed int sub_addr unsigned char *buffer unsigned char count Return If the return value is "0", the programming of E2PROM is completed. Otherwise, the data is needed to be sent again because there is no acknowledge from the slave device. Description specifies the slave device address specifies the sub-address/word address point to the location of data to be sent number of bytes to be sent
unsigned char ReadE2prom(unsigned char address, signed int sub_addr,unsigned char *buffer,unsigned char count) Read number of data bytes from E2PROM. The flow of this subroutine is derived from the data format of reading from the E2PROM as in the figure #3. Parameter unsigned char address signed int sub_addr unsigned char *buffer unsigned char count Return If the return value is "0", the reading of E2PROM is completed. Otherwise, the data is needed to be sent again because there is no acknowledge from the slave device. Description specifies the slave device address specifies the sub-address point to the location of data to be stored number of bytes to be received
Semiconductor Group
15 of 16
AP1624 1.97
Software emulation of the I2C-bus using the General Purpose Timer unit 1 of the 166 family
3.3
Software Compilation
The compilation of this software is using the KEIL C166 compiler. First of all, under the PROJECT menu, click on the "New Project", then key in the name of this project and add files to the project which are the I2C_HW.C and I2CHW_TS.C. Then, save the project. After that, go to the OPTIONS menu and click on the "C166 Compiler..." . Lastly, select the option under OBJECT and cross the box under "Enable 80C167 instructions". This option will allow you to use the C16x derivatives. Now the project is ready to compile and link all the object files. The compiling and linking of the project can be done by clicking the icon "BUILD ALL". The AP162401.EXE is a compressed file and contains I2C_HW.H, I2C_DEF, I2C_HW.C, and I2CHW_TS.C. All these files are necessary to complete the compilation of the software program.
Semiconductor Group
16 of 16
AP1624 1.97

▲Up To Search▲

Price & Availability of AP162401

	To Download AP162401 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .