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| AN46 Application Note CDB5509 CAPTURE INTERFACE By John Lis INTRODUCTION The CDB5509 evaluation board requires a simple modification to interface with the CAPTURE board. The CAPTURE board requires an SCLK input signal to collect data. However, the SCLK pin on the CS5509 is a digital input only. For the CDB5509 to interface with the CAPTURE board, an SCLK signal needs to be created. One possible solution is to derive the SCLK from the XOUT signal. The frequency of the XOUT pin is within the specifications for the SCLK signal and the serial port can accept a continuous clock. The CAPTURE board is designed to ignore extra clock signals on the SCLK line when using a continuous serial clock. Using XOUT as the SCLK input signal is a simple modification of the evaluation board. It is easy to implement, requiring no extra components. The following steps describe the modifications. The source of the SCLK signal is the XOUT pin on the CS5509. Install a jumper on the CS5509 from U1-5 to U1-14. (Make sure that adjustments are made for the CAB5509 adapter board. U1-5 translates to U1-6 and U1-14 translates to U1-21 on the bottom of the evaluation board.) The 100 k resistor R25 needs to be removed to reduce the load upon XOUT. Next the 74HC125 buffer needs to be modified. U3-3 is isolated from the circuit, so there aren't two devices driving the SCLK node. Finally U3-8 is isolated, allowing U3B to be active and able to drive the SCLK output signal to the CAPTURE board. Figure 1 is a schematic for the modified evaluation board. The following check list summarizes the modifications. q q q q REMOVE R25 JUMPER U1-5 to U1-14 ISOLATE U3-3 ISOLATE U3-8 Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved) FEB `98 AN46REV1 1 2 +5V D1 6.8V GND + C2 10 uF C5 +5 C9 0.1 uF + 2 LT1019 -2.5 V 4 6 5 External VREF MODIFICATIONS TO THE CDB5509 FOR INTERFACING TO CDBCAPTURE R22 +5 10 VD+ C10 0.1 uF 11 DGND VA+ 13 VD+ CAL R27 1K R26 1K C19 10nF C20 10nF 3 C17 TP10 9 10 CONV VREF+ TP9 VREFCS 1 TP8 6 U1 2B CS5509 3A DRDY TP11 16 TP12 15 TP13 14 R23 100k 14 R24 100k R25 100k U2F 8 5 U3B 4 VD+ 100k 6 VD+ 14 3 0.1 uF SCLKI 2 C18 U3A R1 1 BP/UP 100k J1 R21 8 AIN0.01 uF 47k 8 10 XIN 4 XOUT 5 Y1 32.768 kHz GND 12 7 U3C 9 VD+ S2 U2 74HC4050 U3 74HC125 A1 A0 R3 50 CLKIN R2 200 CONV BP/UP 15 SCLKO TP7 10 U2D 9 U2C 7 4 U2B 5 VD+ R19 100k VD+ R20 100k R18 A0 47k A1 2 0.1 uF 1 U2A 2 3 47k CS VD+ R17 VD+ CONV CAL + C16 10 uF +5 +5 DRDY SCLK C11 0.01 uF R10 20k R11 100k J2 CAL SDATA R9 +5 +5 C7 0.1 uF 10 AGND 0.1 uF 1A 1B 2A R8 C8 25k 0.1 uF DRDY 11 U2E 12 SDATA - 3B SDATA SCLK TP14 402 AIN+ R31 100k AINR12 100k 402 R13 R4 C15 TP15 TP6 7 AIN+ BP/UP 6 11 13 U3D R16 12 Note: Remove R25 Isolate U3-3 Isolate U3-8 Jumper U1-5 to U1-14 AN46REV1 AN46 Figure 1. Schematic of CDB5509 Modified for the CAPTURE Interface * Notes * |
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