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ADS 124 0
ADS 124 1
ADS1240 ADS1241
SBAS173B - JUNE 2001 - REVISED JUNE 2003
24-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 24 BITS NO MISSING CODES q SIMULTANEOUS 50Hz AND 60Hz REJECTION (-90dB MINIMUM) q 0.0015% INL q 21 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) q PGA GAINS FROM 1 TO 128 q SINGLE CYCLE SETTLING q PROGRAMMABLE DATA OUTPUT RATES q EXTERNAL DIFFERENTIAL REFERENCE OF 0.1V TO 5V q ON-CHIP CALIBRATION q SPITM COMPATIBLE q 2.7V TO 5.25V SUPPLY RANGE q 600W POWER CONSUMPTION q UP TO EIGHT INPUT CHANNELS q UP TO EIGHT DATA I/O
DESCRIPTION
The ADS1240 and ADS1241 are precision, wide dynamic range, delta-sigma, Analog-to-Digital (A/D) converters with 24-bit resolution operating from 2.7V to 5.25V power supplies. The delta-sigma A/D converter provides up to 24 bits of no missing code performance and effective resolution of 21 bits. The input channels are multiplexed. Internal buffering can be selected to provide very high input impedance for direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/A) converter provides an offset correction with a range of 50% of the Full-Scale Range (FSR). The Programmable Gain Amplifier (PGA) provides selectable gains of 1 to 128, with an effective resolution of 19 bits at a gain of 128. The A/D conversion is accomplished with a 2nd-order delta-sigma modulator and programmable Finite-Impulse Response (FIR) filter that provides a simultaneous 50Hz and 60Hz notch. The reference input is differential and can be used for ratiometric conversion. The serial interface is SPI compatible. Up to eight bits of data I/O are also provided that can be used for input or output. The ADS1240 and ADS1241 are designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation.
APPLICATIONS
q q q q q q INDUSTRIAL PROCESS CONTROL WEIGH SCALES LIQUID /GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTATION
AIN0/D0 AIN1/D1 AIN2/D2 AIN3/D3 AIN4/D4 AIN5/D5 AIN6/D6 AIN7/D7 AINCOM MUX
AVDD AGND
VREF+ VREF-
XIN
XOUT
AVDD Clock Generator 2A Offset DAC
A = 1:128 2nd-Order Modulator Digital Filter
BUF
+
PGA
Controller
Registers
POL SCLK Serial Interface DIN DOUT CS AGND BUFEN DVDD DGND PDWN DSYNC RESET DRDY
ADS1241 Only
2A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2001-2003, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
AVDD to DGND ...................................................................... -0.3V to +6V DVDD to DGND ...................................................................... -0.3V to +6V Input Current ............................................................... 100mA, Momentary DGND to AGND .................................................................... -0.3V to 0.3V Input Current ................................................................. 10mA, Continuous AIN ................................................................. AGND -0.5V to AVDD + 0.5V Digital Input Voltage to DGND ................................. -0.3V to DVDD + 0.3V Digital Output Voltage to DGND .............................. -0.3V to DVDD + 0.3V Maximum Junction Temperature ................................................... +150C Operating Temperature Range ......................................... -40C to +85C Storage Temperature Range .......................................... -60C to +150C Lead Temperature (soldering, 10s) .............................................. +300C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
EVALUATION MODULE ORDERING INFORMATION
PRODUCT ADS1241EVM DESCRIPTION ADS1240 and ADS1241 Evaluation Module
PACKAGE/ORDERING INFORMATION
PACKAGE DESIGNATOR(1) DB SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING ADS1240E ORDERING NUMBER ADS1240E ADS1240E/1K ADS1241E ADS1241E/1K TRANSPORT MEDIA, QUANTITY Rails, 60 Tape and Reel, 1000 Rails, 48 Tape and Reel, 1000
PRODUCT ADS1240
PACKAGE-LEAD SSOP-24
"
ADS1241
"
SSOP-28
"
DB
"
-40C to +85C
"
ADS1241E
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
DIGITAL CHARACTERISTICS: -40C to +85C, DVDD 2.7V to 5.25V
PARAMETER Digital Input/Output Logic Family Logic Level: VIH VIL VOH VOL Input Leakage: IIH IIL Master Clock Rate: fOSC Master Clock Period: tOSC CONDITIONS MIN TYP MAX UNITS
CMOS 0.8 * DVDD DGND DVDD - 0.4 DGND -10 1 200 DVDD 0.2 * DVDD DGND + 0.4 10 5 1000 V V V V A A MHz ns
IOH = 1mA IOL = 1mA VI = DVDD VI = 0 1/fOSC
2
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ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +2.5V, unless otherwise specified. ADS1240 ADS1241 PARAMETER ANALOG INPUT (AIN0 - AIN7, AINCOM) Analog Input Range Full-Scale Input Range Differential Input Impedance Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.00Hz Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET DAC Offset DAC Range CONDITIONS MIN TYP MAX UNITS
Buffer OFF Buffer ON (In+) - (In-), See Block Diagram, RANGE = 0 RANGE = 1 Buffer OFF Buffer ON -3dB -3dB -3dB User-Selectable Gain Ranges Modulator OFF, T = 25C
AGND - 0.1 AGND + 0.05
AVDD + 0.1 AVDD - 1.5 VREF /PGA VREF /(2 * PGA) 5/PGA 5 1.65 3.44 14.6
V V V V M G Hz Hz Hz
1 9 5 2 VREF /(2 * PGA) VREF /(4 * PGA) 8 10 1
128 pF pA A V V Bits % ppm/C Bits % of FS ppm of FS ppm of FS/C % ppm/C dB dB dB dB dB dB 2.6 AVDD AVDD V V V dB dB A V nA A A A A A A A nA mW
RANGE = 0 RANGE = 1
Offset Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift SYSTEM PERFORMANCE Resolution Integral Nonlinearity Offset Error (1) Offset Drift(1) Gain Error Gain Error Drift(1) Common-Mode Rejection No Missing Codes End Point Fit
24 0.0015 7.5 0.02 0.005 0.5
Normal-Mode Rejection Output Noise Power-Supply Rejection VOLTAGE REFERENCE INPUT VREF Reference Input Range Common-Mode Rejection Common-Mode Rejection Bias Current(3) POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current
fCM = fCM = fSIG = fSIG =
at DC 60Hz, fDATA = 50Hz, fDATA = 50Hz, fDATA = 60Hz, fDATA =
100 15Hz 15Hz 15Hz 15Hz 80 0.1 0 0.1 130 120 100 100 See Typical Characteristics 95 2.5
at DC, dB = -20 log(VOUT /VDD)(2) VREF (REF IN+) - (REF IN-), RANGE = 0 REF IN+, REF IN- RANGE = 1 at DC fVREFCM = 60Hz, fDATA = 15Hz VREF = 2.5V AVDD PDWN = 0, or SLEEP PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON Normal Mode, DVDD = 5V SLEEP Mode, DVDD = 5V Read Data Continuous Mode, DVDD = 5V PDWN PGA = 1, Buffer OFF, DVDD = 5V
120 120 1.3 4.75 1 120 400 160 760 80 60 230 0.5 1.1 5.25 250 675 300 1275 125
Digital Current
Power Dissipation
1.9
NOTES: (1) Calibration can minimize these errors to the level of the noise. (2) VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
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3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications -40C to +85C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +1.25V, unless otherwise specified. ADS1240 ADS1241 PARAMETER ANALOG INPUT (AIN0 - AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Input Impedance Differential Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.00Hz Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET DAC Offset DAC Range CONDITIONS MIN TYP MAX UNITS
Buffer OFF Buffer ON (In+) - (In-) See Block Diagram, RANGE = 0 RANGE = 1 Buffer OFF Buffer ON -3dB -3dB -3dB User-Selectable Gain Ranges Modulator OFF, T = 25C
AGND - 0.1 AGND + 0.05
AVDD + 0.1 AVDD - 1.5 VREF /PGA VREF /(2 * PGA) 5/PGA 5 1.65 3.44 14.6
V V V V M G Hz Hz Hz
1 9 5 2 VREF /(2 * PGA) VREF /(4 * PGA) 8 10 2
128 pF pA A V V Bits % ppm/C Bits % of FS ppm of FS ppm of FS/C % ppm/C dB dB dB dB dB dB 1.30 AVDD 2.6 V V V dB dB A 3.3 1 107 355 118 483 50 75 113 0.5 0.6 225 600 275 1225 100 V nA A A A A A A A nA mW
RANGE = 0 RANGE = 1
Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift SYSTEM PERFORMANCE Resolution Integral Nonlinearity Offset Error(1) Offset Drift(1) Gain Error Gain Error Drift(1) Common-Mode Rejection No Missing Codes End Point Fit
24 0.0015 15 0.04 0.01 1.0
Normal-Mode Rejection Output Noise Power-Supply Rejection VOLTAGE REFERENCE INPUT VREF Reference Input Range Common-Mode Rejection Common-Mode Rejection Bias Current(3) POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current
fCM = fCM = fSIG = fSIG =
at DC 60Hz, fDATA = 50Hz, fDATA = 50Hz, fDATA = 60Hz, fDATA =
100 15Hz 15Hz 15Hz 15Hz 75 0.1 0 0.1 130 120 100 100 See Typical Characteristics 90 1.25 2.5 120 120 0.65 2.7
at DC, dB = -20 log(VOUT /VDD)(2) VREF (REF IN+) - (REF IN-), RANGE = 0 REF IN+, REF IN- RANGE = 1 fVREFCM at DC = 60Hz, fDATA = 15Hz VREF = 1.25
Digital Current
Power Dissipation
AVDD PDWN = 0, or SLEEP PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON Normal Mode, DVDD = 3V SLEEP Mode, DVDD = 3V Read Data Continuous Mode, DVDD = 3V PDWN = 0 PGA = 1, Buffer OFF, DVDD = 3V
1.2
NOTES: (1) Calibration can minimize these errors to the level of the noise. (2) VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
4
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PIN CONFIGURATION (ADS1240)
Top View SSOP
PIN CONFIGURATION (ADS1241)
Top View SSOP
DVDD
DVDD DGND XIN XOUT RESET DSYNC PDWN DGND VREF+ 1 2 3 4 5 6 ADS1240 7 8 9 18 POL 17 AVDD 16 AGND 15 AINCOM 14 AIN3/D3 13 AIN2/D2 24 BUFEN 23 DRDY 22 SCLK 21 DOUT 20 DIN 19 CS
1 2 3 4 5 6 7 8 9 ADS1241
28 BUFEN 27 DRDY 26 SCLK 25 DOUT 24 DIN 23 CS 22 POL 21 AVDD 20 AGND 19 AINCOM 18 AIN3/D3 17 AIN2/D2 16 AIN7/D7 15 AIN6/D6
DGND XIN XOUT RESET DSYNC PDWN DGND VREF+
VREF- 10 AIN0/D0 11 AIN1/D1 12 AIN4/D4 13 AIN5/D5 14
VREF- 10 AIN0/D0 11 AIN1/D1 12
PIN DESCRIPTIONS (ADS1240)
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME DVDD DGND XIN XOUT RESET DSYNC PDWN DGND VREF+ VREF- AIN0/D0 AIN1/D1 AIN2/D2 AIN3/D3 AINCOM AGND AVDD POL CS DIN DOUT SCLK DRDY BUFEN DESCRIPTION Digital Power Supply Digital Ground Clock Input Clock Output, used with external crystals. Active LOW, resets the entire device. Active LOW, Synchronization Control Active LOW, Power Down. The power down function shuts down the analog and digital circuits. Digital Ground Positive Differential Reference Input Negative Differential Reference Input Analog Input 0 / Data I/O 0 Analog Input 1 / Data I/O 1 Analog Input 2 / Data I/O 2 Analog Input 3 / Data I/O 3 Analog Input Common, connect to AGND if unused. Analog Ground Analog Power Supply Serial Clock Polarity Active LOW, Chip Select Serial Data Input, Schmitt Trigger Serial Data Output Serial Clock, Schmitt Trigger Active LOW, Data Ready Buffer Enable
PIN DESCRIPTIONS (ADS1241)
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME DVDD DGND XIN XOUT RESET DSYNC PDWN DGND VREF+ VREF- AIN0/D0 AIN1/D1 AIN4/D4 AIN5/D5 AIN6/D6 AIN7/D7 AIN2/D2 AIN3/D3 AINCOM AGND AVDD POL CS DIN DOUT SCLK DRDY BUFEN DESCRIPTION Digital Power Supply Digital Ground Clock Input Clock Output, used with external crystals. Active LOW, resets the entire device. Active LOW, Synchronization Control Active LOW, Power Down. The power down function shuts down the analog and digital circuits. Digital Ground Positive Differential Reference Input Negative Differential Reference Input Analog Input 0 / Data I/O 0 Analog Input 1 / Data I/O 1 Analog Input 4 / Data I/O 4 Analog Input 5 / Data I/O 5 Analog Input 6 / Data I/O 6 Analog Input 7 / Data I/O 7 Analog Input 2 / Data I/O 2 Analog Input 3 / Data I/O 3 Analog Input Common, connect to AGND if unused. Analog Ground Analog Power Supply Serial Clock Polarity Active LOW, Chip Select Serial Data Input, Schmitt Trigger Serial Data Output Serial Clock, Schmitt Trigger Active LOW, Data Ready Buffer Enable
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SBAS173B
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5
TIMING DIAGRAMS
CS t3 SCLK (POL = 0) SCLK (POL = 1) t4 DIN MSB t5 LSB t7 MSB(1) t8 LSB(1) t9 t6 t2 t11 t1 t2 t10
(Command or Command and Data) DOUT NOTE: (1) Bit order = 0.
SCLK Reset Waveform
ADS1240 or ADS1241 Resets On Falling Edge 300 * tOSC < t12 < 500 * tOSC t13 t13 t13 : > 5 * tOSC 550 * tOSC < t14 < 750 * tOSC t12 t14 t15 1050 * tOSC < t15 < 1250 * tOSC
SCLK
DIAGRAM 1.
tDATA DRDY t17 SCLK t19 t18 RESET, DSYNC, PDWN
t16
DIAGRAM 2.
TIMING CHARACTERISTICS TABLES
SPEC t1 t2 t3 t4 t5 t6 t 7(1) t 8(1) t9 t10 t11 DESCRIPTION SCLK Period SCLK Pulse Width, HIGH and LOW CS low to first SCLK Edge; Setup Time(2) DIN Valid to SCLK Edge; Setup Time Valid DIN to SCLK Edge; Hold Time Delay between last SCLK edge for DIN and first SCLK edge for DOUT: RDATA, RDATAC, RREG, WREG SCLK Edge to Valid New DOUT SCLK Edge to DOUT, Hold Time Last SCLK Edge to DOUT Tri-State NOTE: DOUT goes tri-state immediately when CS goes HIGH. CS LOW time after final SCLK edge. Final SCLK edge of one command until first edge SCLK of next command: RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL SELFCAL RESET (also SCLK Reset or RESET Pin) Pulse Width Allowed analog input change for next valid conversion. DOR update, DOR data not valid. First SCLK after DRDY goes LOW: RDATAC Mode Any other mode 0 ns 50 50 0 6 10 tOSC Periods ns ns tOSC Periods MIN 4 3 200 0 50 50 MAX UNITS tOSC Periods DRDY Periods ns ns ns ns
t16 t17 t18 t19
4 2 4 16 4 5000 4 10 0
tOSC Periods DRDY Periods DRDY Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods
NOTES: (1) Load = 20pF 10k to DGND. (2) CS may be tied LOW.
6
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TYPICAL CHARACTERISTICS
All specifications, AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS vs PGA SETTING 21.5 21.0 20.5 DR = 01
EFFECTIVE NUMBER OF BITS vs PGA SETTING 22
DR = 10
21 DR = 10 20
ENOB (rms)
ENOB (rms)
20.0 19.5 19.0 DR = 00 18.5 18.0 Buffer OFF 17.5 17.0 1 2 4 8 16 32 64 128 PGA Setting
19 DR = 01 18 DR = 00 17 Buffer ON 16 15 1 2 4 8 16 32 64 128 PGA Setting
EFFECTIVE NUMBER OF BITS vs PGA SETTING 20.5 20.0 19.5 DR = 10 2.0 1.8
NOISE vs INPUT SIGNAL
Noise (rms, ppm of FS)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
ENOB (rms)
19.0 18.5 18.0 17.5 17.0 16.5 16.0 1 2 4 8 16 32 Buffer OFF, VREF = 1.25V DR = 00
DR = 01
64
128
0 -2.5
-1.5
-0.5 VIN (V)
0.5
1.5
2.5
PGA Setting
COMMON-MODE REJECTION RATIO vs FREQUENCY 140 120 100
POWER SUPPLY REJECTION RATIO vs FREQUENCY 140 120 100
PSRR (dB)
CMRR (dB)
80 60 40 20 Buffer ON 0 1 10 100 1k 10k 100k Frequency of Power Supply (Hz)
80 60 40 20 Buffer ON 0 1 10 100 1k 10k 100k Frequency of Power Supply (Hz)
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7
TYPICAL CHARACTERISTICS (Cont.)
All specifications, AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified.
OFFSET vs TEMPERATURE (Cal at 25C) 50 PGA1 0 PGA16
GAIN vs TEMPERATURE (Cal at 25C) 1.00010 1.00006 Gain (Normalized) 1.00002 0.99998 0.99994 0.99990 0.99986
Offset (ppm of FS)
-50 PGA64 PGA128 -150
-100
-200 -50 -30 -10 10 30 50 70 90 Temperature (C)
-50
-30
-10
10
30
50
70
90
Temperature (C)
INTEGRAL NONLINEARITY vs INPUT SIGNAL 10 8 6 -40C
ANALOG CURRENT vs TEMPERATURE 150 140 130 AVDD = 5
INL (ppm of FS)
4 2 0 -2 -4 -6 -8
Current (A)
+85C
120 110 100 90 80 70 60
0 VIN (V) 0.5 1.0 1.5 2.0 2.5
AVDD = 3
+25C
Buffer OFF
-10 -2.5 -2.0 -1.5 -1.0 -0.5
50
-50
-30
-10
10
30
50
70
90
Temperature (C)
ANALOG CURRENT vs PGA 900 800 700 AVDD = 5V, Buffer = ON Buffer = OFF 600 500 400 300 200 AVDD = 3V, Buffer = ON Buffer = OFF
DIGITAL CURRENT vs SUPPLY 300 250 200 150 100 50
IANALOG (A)
IDIGITAL (A)
SLEEP 4.91MHz
Normal 4.91MHz
Normal 2.45MHz
100 0 1 2 4 8 16 32 64 128 PGA Setting
Power Down 0 3.0 3.5 4.0 VDD (V) 4.5
SLEEP 2.45MHz 5.0
8
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TYPICAL CHARACTERISTICS (Cont.)
All specifications, AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified.
OFFSET DAC OFFSET vs TEMPERATURE (Cal at 25C) 200 170 140
NOISE HISTOGRAM 3500 3000 10k Readings VIN = 0V
Offset (ppm of FSR)
Number of Occurrences
2500 2000 1500 1000 500 0 -3.5 -3.0 -2.5 -2.0 -1.5 -1 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ppm of FS
110 80 50 20 -10 -40 -70 -100 -50 -30 -10 10 30 50 70 90 Temperature (C)
OFFSET DAC GAIN vs TEMPERATURE (Cal at 25C) 1.00020 1.00016 1.00012
Noise (rms, ppm of FS)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
OFFSET DAC NOISE vs SETTING
Gain (Normalized)
1.00008 1.00004 1.00000 0.99996 0.99992 0.99988 0.99984 0.99980 0.99976 -50 -30 -10 10 30 50 70 90 Temperature (C)
0 -128
-96
-64
-32
0
32
64
96
128
Offset DAC Setting
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9
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 1. For example, if AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative terminal for the differential input
channel. With this method, it is possible to have up to eight single-ended input channels or four independent differential input channels for the ADS1241, and four single-ended input channels or two independent differential input channels for the ADS1240. Note that AINCOM can be treated as an input channel. The ADS1240 and ADS1241 feature a single-cycle settling digital filter that provides valid data on the first conversion after a new channel selection. In order to minimize the settling error, synchronize MUX changes to the conversion beginning, which is indicated by the falling edge of DRDY. In other words, issuing a MUX change through the WREG command immediately after DRDY goes LOW minimizes the settling error. Increasing the time between the conversion beginning (DRDY goes LOW) and the MUX change command (tDELAY) results in a settling error in the conversion data, as shown in Figure 2.
AIN0/D0
AIN1/D1
AVDD
AIN2/D2
Burnout Current Source
AIN3/D3
BURNOUT CURRENT SOURCES
Input Buffer
AIN4/D4
AIN5/D5
Burnout Current Source
AIN6/D6 AGND AIN7/D7
The Burnout Current Sources can be used to detect sensor short-circuit or open-circuit conditions. Setting the Burnout Current Sources (BOCS) bit in the SETUP register activates two 2A current sources called burnout current sources. One of the current sources is connected to the converter's negative input and the other is connected to the converter's positive input. Figure 3 shows the situation for an open-circuit sensor. This is a potential failure mode for many kinds of remotely connected sensors. The current source on the positive input acts as a pull-up, causing the positive input to go to the positive analog supply, and the current source on the negative input acts as a pull-down, causing the negative input to go to ground. The ADS1240/41 therefore outputs full-scale (7FFFFF Hex).
ADS1241 Only
AINCOM
FIGURE 1. Input Multiplexer Configuration.
New Conversion Begins, Previous Conversion Data Complete Previous Conversion
New Conversion Complete
DRDY tDELAY SCLK (POL = 0)
DIN
MSB
LSB
SETTLING ERROR vs DELAY TIME fCLK = 2.4576MHz 10.000000 1.000000
Settling Error (%)
0.100000 0.010000 0.001000 0.000100 0.000010 0.000001 0 2 4 6 8 10 12 Delay Time, tDELAY (ms) 14 16
FIGURE 2. Input Multiplexer Configuration.
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AVDD
2A AVDD OPEN CIRCUIT 0V 2A ADC CODE = 0x7FFFFFH
The buffer draws additional current when activated. The current required by the buffer depends on the PGA setting. When the PGA is set to 1, the buffer uses approximately 50A; when the PGA is set to 128, the buffer uses approximately 500A.
PGA
The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5V full-scale signal, the A/D converter can resolve down to 1V. With a PGA of 128 and a full-scale signal of 39mV, the A/D converter can resolve down to 75nV. AVDD current increases with PGA settings higher than 4.
FIGURE 3. Burnout detection while sensor is open-circuited. Figure 4 shows a short-circuited sensor. Since the inputs are shorted and at the same potential, the ADS1240/41 signal outputs are approximately zero. (Note that the code for shorted inputs is not exactly zero due to internal series resistance, low-level noise and other error sources.)
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input range of the PGA using the Offset DAC (ODAC) register. The ODAC register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Using the offset DAC does not reduce the performance of the A/D converter. For more details on the ODAC, please refer to TI application report SBAA077.
AVDD
MODULATOR
2A AVDD/2 SHORT CIRCUIT AVDD/2 2A ADC CODE 0
The modulator is a single-loop second-order system. The modulator runs at a clock speed (fMOD) that is derived from the external clock (fOSC). The frequency division is determined by the SPEED bit in the SETUP register, as shown in Table I.
SPEED BIT 0 1 0 1 DR BITS 01 1st NOTCH FREQ. 50/60Hz 25/30Hz 100/120Hz 50/60Hz
fOSC 2.4576MHz 4.9152MHz
fMOD 19,200Hz 9,600Hz 38,400Hz 19,200Hz
00 15Hz 7.5Hz 30Hz 15Hz
10
FIGURE 4. Burnout detection while sensor is short-circuited.
7.5Hz 3.75Hz 3.75Hz 1.875Hz 15Hz 7.5Hz 7.5Hz 3.75Hz
TABLE I. Output Configuration.
INPUT BUFFER
The input impedance of the ADS1240/41 without the buffer enabled is approximately 5M/PGA. For systems requiring very high input impedance, the ADS1240/41 provides a chopper-stabilized differential FET-input voltage buffer. When activated, the buffer raises the ADS1240/41 input impedance to approximately 5G. The buffer's input range is approximately 50mV to AVDD - 1.5V. The buffer's linearity will degrade beyond this range. Differential signals should be adjusted so that both signals are within the buffer's input range. The buffer can be enabled using the BUFEN pin or the BUFEN bit in the ACR register. The buffer is on when the BUFEN pin is high and the BUFEN bit is set to one. If the BUFEN pin is low, the buffer is disabled. If the BUFEN bit is set to zero, the buffer is also disabled.
CALIBRATION
The offset and gain errors can be minimized with calibration. The ADS1240 and ADS1241 support both self and system calibration. Self-calibration of the ADS1240 and ADS1241 corrects internal offset and gain errors and is handled by three commands: SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL command performs both an offset and gain calibration. SELFGCAL performs a gain calibration and SELFOCAL performs an offset calibration, each of which takes two tDATA periods to complete. During self-calibration, the ADC inputs are disconnected internally from the input pins. The PGA must be set to 1 prior to issuing a SELFCAL or SELFGCAL command. Any PGA is allowed when issuing a SELFOCAL command. For example, if using PGA = 64, first set PGA = 1 and issue
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SELFGCAL. Afterwards set PGA = 64 and issue SELFOCAL. For operation with a reference voltage greater than (AVDD - 1.5) volts, the buffer must also be turned off during gain selfcalibration to avoid exceeding the buffer input range. System calibration corrects both internal and external offset and gain errors. While performing system calibration, the appropriate signal must be applied to the inputs. The system offset calibration command (SYSOCAL) requires a zero input differential signal (see Table IV, page 18). It then computes the offset that nullifies the offset in the system. The system gain calibration command (SYSGCAL) requires a positive full-scale input signal. It then computes a value to nullify the gain error in the system. Each of these calibrations takes two tDATA periods to complete. System gain calibration is recommended for the best gain calibration at higher PGAs. Calibration should be performed after power on, a change in temperature, or a change of the PGA. The RANGE bit (ACR bit 2) must be zero during calibration. Calibration removes the effects of the ODAC; therefore, disable the ODAC during calibration, and enable again after calibration is complete. At the completion of calibration, the DRDY signal goes low, indicating the calibration is finished. The first data after calibration should be discarded since it may be corrupt from calibration data remaining in the filter. The second data is always valid.
C1 Crystal
XIN
C2
XOUT
FIGURE 5. Crystal Connection.
CLOCK SOURCE Crystal Crystal Crystal Crystal
FREQUENCY 2.4576 4.9152 4.9152 4.9152
C1 0-20pF 0-20pF 0-20pF 0-20pF
C2 0-20pF 0-20pF 0-20pF 0-20pF
PART NUMBER ECS, ECSD 2.45 - 32 ECS, ECSL 4.91 ECS, ECSD 4.91 CTS, MP 042 4M9182
TABLE II. Recommended Crystals. Finite Impulse Response (FIR) digital filter that a user can configure for various output data rates. When a 2.4576MHz crystal is used, the device can be programmed for an output data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions, the digital filter rejects both 50Hz and 60Hz interference. Figure 6 shows the digital filter frequency response for data output rates of 15Hz, 7.5Hz, and 3.75Hz. If a different data output rate is desired, a different crystal frequency can be used. However, the rejection frequencies shift accordingly. For example, a 3.6864MHz master clock with the default register condition has: (3.6864MHz/2.4576MHz) * 15Hz = 22.5Hz data output rate and the first and second notch is: 1.5 * (50Hz and 60Hz) = 75Hz and 90Hz
EXTERNAL VOLTAGE REFERENCE
The ADS1240 and ADS1241 require an external voltage reference. The selection for the voltage reference value is made through the ACR register. The external voltage reference is differential and is represented by the voltage difference between the pins: +VREF and -VREF. The absolute voltage on either pin, +VREF or -VREF, can range from AGND to AVDD. However, the following limitations apply: For AVDD = 5.0V and RANGE = 0 in the ACR, the differential VREF must not exceed 2.5V. For AVDD = 5.0V and RANGE = 1 in the ACR, the differential VREF must not exceed 5V. For AVDD = 3.0V and RANGE = 0 in the ACR, the differential VREF must not exceed 1.25V. For AVDD = 3.0V and RANGE = 1 in the ACR, the differential VREF must not exceed 2.5V.
DATA I/O INTERFACE
The ADS1240 has four pins and the ADS1241 has eight pins that serve a dual purpose as both analog inputs and data I/O. These pins are powered from AVDD and are configured through the IOCON, DIR, and DIO registers. These pins can be individually configured as either analog inputs or data I/O. See Figure 7 (page 14) for the equivalent schematic of an Analog/Data I/O pin. The IOCON register defines the pin as either an analog input or data I/O. The power-up state is an analog input. If the pin is configured as an analog input in the IOCON register, the DIR and DIO registers have no effect on the state of the pin. If the pin is configured as data I/O in the IOCON register, then DIR and DIO are used to control the state of the pin. The DIR register controls the direction of the data pin, either as an input or output. If the pin is configured as an input in the DIR register, then the corresponding DIO register bit reflects the state of the pin. Make sure the pin is driven to a logic one or zero when configured as an input to prevent
CLOCK GENERATOR
The clock source for the ADS1240 and ADS1241 can be provided from a crystal, oscillator, or external clock. When the clock source is a crystal, external capacitors must be provided to ensure start-up and stable clock frequency. This is shown in both Figure 5 and Table II. XOUT is only for use with external crystals and it should not be used as a clock driver for external circuitry.
DIGITAL FILTER
The ADS1240 and ADS1241 have a 1279 tap linear phase
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ADS1240 AND ADS1241 FILTER RESPONSE WHEN fDATA = 15Hz 0 -20 -40 -40 -50 -60
FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 15Hz
Magnitude (dB)
0 20 40 60 80 100 120 140 160 180 200
-60
-70 -80 -90 -100 -110 -120 -130 -140 45 50 55 Frequency (Hz) 60 65
Gain (dB)
-80 -100 -120 -140 -160 -180 Frequency (Hz)
ADS1240 AND ADS1241 FILTER RESPONSE WHEN fDATA = 7.5Hz 0 -20 -40 -40 -50 -60
FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 7.5Hz
Magnitude (dB)
-60
-70 -80 -90 -100 -110 -120 -130 -140
Gain (dB)
-80 -100 -120 -140 -160 -180 0 20 40 60 80 100 120 140 160 180 200 Frequency (Hz) ADS1240 AND ADS1241 FILTER RESPONSE WHEN fDATA = 3.75Hz 0 -20 -40
45
50
55 Frequency (Hz)
60
65
FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 3.75Hz -40 -50 -60
Magnitude (dB)
0 20 40 60 80 100 120 140 160 180 200
-60
-70 -80 -90 -100 -110 -120 -130 -140 45 50 55 Frequency (Hz) 60 65
Gain (dB)
-80 -100 -120 -140 -160 -180 Frequency (Hz)
fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1
DATA OUTPUT RATE 15Hz 7.5Hz 3.75Hz
-3dB BANDWIDTH 14.6Hz 3.44Hz 1.65Hz
ATTENUATION fIN = 50 0.3Hz -80.8dB -85.9dB -93.8dB fIN = 60 0.3Hz -87.3dB -87.4dB -88.6dB fIN = 50 1Hz -68.5dB -71.5dB -86.8dB fIN = 60 1Hz -76.1dB -76.2dB -77.3dB
FIGURE 6. Filter Frequency Responses.
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excess current dissipation. If the pin is configured as an output in the DIR register, then the corresponding DIO register bit value determines the state of the output pin (0 = AGND, 1 = AVDD). It is still possible to perform A/D conversions on a pin configured as data I/O. This may be useful as a test mode, where the data I/O pin is driven and an A/D conversion is done on the pin.
issued when DIN and DOUT are connected. While in RDATAC mode, DIN looks for the STOPC or RESET command. If either of these 8-bit bytes appear on DOUT (which is connected to DIN), the RDATAC mode ends.
DATA READY DRDY PIN
The DRDY line is used as a status signal to indicate when data is ready to be read from the internal data register. DRDY goes LOW when a new data word is available in the DOR register. It is reset HIGH when a read operation from the data register is complete. It also goes HIGH prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. The status of DRDY can also be obtained by interrogating bit 7 of the ACR register (address 2H). The serial interface can operate in 3-wire mode by tying the CS input LOW. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the ADS1240 and ADS1241. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit of the microcontroller.
IOCON DIR
DIO WRITE AINx/Dx To Analog Mux DIO READ
FIGURE 7. Analog/Data Interface Pin.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to communicate synchronously with the ADS1240 and ADS1241. The ADS1240 and ADS1241 operate in slave-only mode. The serial interface is a standard four-wire SPI (CS , SCLK, DIN and DOUT) interface that supports both serial clock polarities (POL pin).
DSYNC OPERATION
Synchronization can be achieved either through the DSYNC pin or the DSYNC command. When the DSYNC pin is used, the digital circuitry is reset on the falling edge of DSYNC. While DSYNC is LOW, the serial interface is deactivated. Reset is released when DSYNC is taken HIGH. Synchronization occurs on the next rising edge of the system clock after DSYNC is taken HIGH. When the DSYNC command is sent, the digital filter is reset on the edge of the last SCLK of the DSYNC command. The modulator is held in RESET until the next edge of SCLK is detected. Synchronization occurs on the next rising edge of the system clock after the first SCLK following the DSYNC command.
Chip Select (CS )
The chip select (CS ) input must be externally asserted before communicating with the ADS1240 or ADS1241. CS must stay LOW for the duration of the communication. Whenever CS goes HIGH, the serial interface is reset. CS may be hard-wired LOW.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input and is used to clock DIN and DOUT data. Make sure to have a clean SCLK to prevent accidental double-shifting of the data. If SCLK is not toggled within 3 DRDY pulses, the serial interface resets on the next SCLK pulse and starts a new communication cycle. A special pattern on SCLK resets the entire chip; see the RESET section for additional information.
POWER-UP--SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate digital supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically.
Clock Polarity (POL)
The clock polarity input (POL) controls the polarity of SCLK. When POL is LOW, data is clocked on the falling edge of SCLK and SCLK should be idled LOW. Likewise, when POL is HIGH, the data is clocked on the rising edge of SCLK and SCLK should be idled HIGH.
RESET
The user can reset the registers to their default values in three different ways: by asserting the RESET pin; by issuing the RESET command; or by applying a special waveform on the SCLK (the SCLK Reset Waveform, as shown in the Timing Diagram). Note: if both POL and SCLK pins are held high, applying the SCLK Reset Waveform to the CS pin also resets the part.
Data Input (DIN) and Data Output (DOUT)
The data input (DIN) and data output (DOUT) receive and send data from the ADS1240 and ADS1241. DOUT is high impedance when not in use to allow DIN and DOUT to be connected together and driven by a bidirectional bus. Note: the Read Data Continuous Mode (RDATAC) command should not be
APPLICATION EXAMPLES
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ADS1240 AND ADS1241 REGISTER
The operation of the device is set up through individual registers. Collectively, the registers contain all the informa-
tion needed to configure the part, such as data format, multiplexer settings, calibration settings, data rate, etc. The set of the 16 registers are shown in Table III.
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
REGISTER SETUP MUX ACR ODAC DIO DIR IOCON OCR0 OCR1 OCR2 FSR0 FSR1 FSR2 DOR2 DOR1 DOR0
BIT 7 ID PSEL3 DRDY SIGN DIO_7 DIR_7 IO7 OCR07 OCR15 OCR23 FSR07 FSR15 FSR23 DOR23 DOR15 DOR07
BIT 6 ID PSEL2 U/B OSET6 DIO_6 DIR_6 IO6 OCR06 OCR14 OCR22 FSR06 FSR14 FSR22 DOR22 DOR14 DOR16
BIT 5 ID PSEL1 SPEED OSET5 DIO_5 DIR_5 IO5 OCR05 OCR13 OCR21 FSR05 FSR13 FSR21 DOR21 DOR13 FSR21
BIT 4 ID PSEL0 BUFEN OSET4 DIO_4 DIR_4 IO4 OCR04 OCR12 OCR20 FSR04 FSR12 FSR20 DOR20 DOR12 DOR04
BIT 3 BOCS NSEL3 BIT ORDER OSET3 DIO_3 DIR_3 IO3 OCR03 OCR11 OCR19 FSR03 FSR11 FSR19 DOR19 DOR11 DOR03
BIT 2 PGA2 NSEL2 RANGE OSET2 DIO_2 DIR_2 IO2 OCR02 OCR10 OCR18 FSR02 FSR10 FSR18 DOR18 DOR10 DOR02
BIT 1 PGA1 NSEL1 DR1 OSET1 DIO_1 DIR_1 IO1 OCR01 OCR09 OCR17 FSR01 FSR09 FSR17 DOR17 DOR09 DOR01
BIT 0 PGA0 NSEL0 DR0 OSET0 DIO_0 DIR_0 IO0 OCR00 OCR08 OCR16 FSR00 FSR08 FSR16 DOR16 DOR08 DOR00
TABLE III. Registers. DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register Reset Value = iiii0000
bit 7 ID bit 6 ID bit 5 ID bit 4 ID bit 3 BOCS bit 2 PGA2 bit 1 PGA1 bit 0 PGA0
MUX (Address 01H) Multiplexer Control Register Reset Value = 01H
bit 7 PSEL3 bit 6 PSEL2 bit 5 PSEL1 bit 4 PSEL0 bit 3 NSEL3 bit 2 NSEL2 bit 1 NSEL1 bit 0 NSEL0
bit 7-4 bit 7-4 bit 3 Factory Programmed Bits BOCS: Burnout Current Source 0 = Disabled (default) 1 = Enabled PGA2: PGA1: PGA0: Programmable Gain Amplifier Gain Selection 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128
bit 2-0
PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel Select 0000 = AIN0 (default) 0001 = AIN1 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1xxx = AINCOM (except when xxx = 111) 1111 = Reserved NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel Select 0000 = AIN0 0001 = AIN1 (default) 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1xxx = AINCOM (except when xxx = 111) 1111 = Reserved
bit 3-0
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ACR (Address 02H) Analog Control Register Reset Value = X0H
bit 7 DRDY bit 6 U/B bit 5 SPEED bit 4 BUFEN bit 3 bit 2 bit 1 DR1 bit 0 DR0 BIT ORDER RANGE
ODAC (Address 03 ) Offset DAC Reset Value = 00H
bit 7 SIGN bit 6 OSET6 bit 5 OSET5 bit 4 OSET4 bit 3 OSET3 bit 2 OSET2 bit 1 OSET1 bit 0 OSET0
bit 7 bit 6
DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin. U/B: Data Format 0 = Bipolar (default) 1 = Unipolar
U/B 0 ANALOG INPUT +FSR Zero -FSR +FSR Zero -FSR DIGITAL OUTPUT (Hex) 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000
bit 7
Sign 0 = Positive 1 = Negative
Offset = VREF OSET [6 : 0] * 2 * PGA 127 VREF 4 * PGA OSET [6 : 0] * 127 RANGE = 0
Offset =
RANGE = 1
1
NOTE: The offset DAC must be enabled after calibration or the calibration nullifies the effects.
bit 5
SPEED: Modulator Clock Speed 0 = fMOD = fOSC/128 (default) 1 = fMOD = fOSC/256 BUFEN: Buffer Enable 0 = Buffer Disabled (default) 1 = Buffer Enabled BIT ORDER: Data Output Bit Order 0 = Most Significant Bit Transmitted First (default) 1 = Least Significant Bit Transmitted First This configuration bit controls only the bit order within the byte of data that is shifted out. Data is always shifted out of the part most significant byte first. Data is always shifted into the part most significant bit first.
DIO (Address 04H) Data I/O Reset Value = 00H
bit 7 DIO 7 bit 6 DIO 6 bit 5 DIO 5 bit 4 DIO 4 bit 3 DIO 3 bit 2 DIO 2 bit 1 DIO 1 bit 0 DIO 0
bit 4
bit 3
If the IOCON register is configured for data, a value written to this register appears on the data I/O pins if the pin is configured as an output in the DIR register. Reading this register returns the value of the data I/O pins. Bit 4 to bit 7 is not used in ADS1240. DIR (Address 05H) Direction Control for Data I/O Reset Value = FFH
bit 7 DIR7 bit 6 DIR6 bit 5 DIR5 bit 4 DIR4 bit 3 DIR3 bit 2 DIR2 bit 1 DIR1 bit 0 DIR0
bit 2
RANGE: Range Select 0 = Full-Scale Input Range equal to V REF (default). 1 = Full-Scale Input Range equal to 1/2 VREF NOTE: This allows reference voltages as high as AVDD, but even with a 5V reference voltage the calibration must be performed with this bit set to 0. DR1: DR0: Data Rate (fOSC = 2.4576MHz, SPEED = 0) 00 = 15Hz (default) 01 = 7.5Hz 10 = 3.75Hz 11 = Reserved
Each bit controls whether the corresponding data I/O pin is an output (= 0) or input (= 1). The default power-up state is as inputs. Bit 4 to bit 7 is not used in ADS1240. IOCON (Address 06H) I/O Configuration Register Reset Value = 00H
bit 7 IO7 bit 6 IO6 bit 5 IO5 bit 4 IO4 bit 3 IO3 bit 2 IO2 bit 1 IO1 bit 0 IO0
bit 1-0
bit 7-0
IO7: IO0: Data I/O Configuration 0 = Analog (default) 1 = Data
Configuring the pin as a data I/O pin allows it to be controlled through the DIO and DIR registers. Bit 4 to bit 7 is not used in ADS1240. OCR0 (Address 07H) Offset Calibration Coefficient (Least Significant Byte) Reset Value = 00H
bit 7 OCR07 bit 6 OCR06 bit 5 OCR05 bit 4 OCR04 bit 3 OCR03 bit 2 OCR02 bit 1 OCR01 bit 0 OCR00
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OCR1 (Address 08H) Offset Calibration Coefficient (Middle Byte) Reset Value = 00H
bit 7 OCR15 bit 6 OCR14 bit 5 OCR13 bit 4 OCR12 bit 3 OCR11 bit 2 OCR10 bit 1 OCR09 bit 0 OCR08
FSR2 (Address 0CH) Full-Scale Register (Most Significant Byte) Reset Value = 55H
bit 7 FSR23 bit 6 FSR22 bit 5 FSR21 bit 4 FSR20 bit 3 FSR19 bit 2 FSR18 bit 1 FSR17 bit 0 FSR16
OCR2 (Address 09H) Offset Calibration Coefficient (Most Significant Byte) Reset Value = 00H
bit 7 OCR23 bit 6 OCR22 bit 5 OCR21 bit 4 OCR20 bit 3 OCR19 bit 2 OCR18 bit 1 OCR17 bit 0 OCR16
DOR2 (Address 0DH) Data Output Register (Most Significant Byte) (Read Only) Reset Value = 00H
bit 7 DOR23 bit 6 DOR22 bit 5 DOR21 bit 4 DOR20 bit 3 DOR19 bit 2 DOR18 bit 1 DOR17 bit 0 DOR16
FSR0 (Address 0AH) Full-Scale Register (Least Significant Byte) Reset Value = 59H
bit 7 FSR07 bit 6 FSR06 bit 5 FSR05 bit 4 FSR04 bit 3 FSR03 bit 2 FSR02 bit 1 FSR01 bit 0 FSR00
DOR1 (Address 0EH) Data Output Register (Middle Byte) (Read Only) Reset Value = 00H
bit 7 DOR15 bit 6 DOR14 bit 5 DOR13 bit 4 DOR12 bit 3 DOR11 bit 2 DOR10 bit 1 DOR09 bit 0 DOR08
FSR1 (Address 0BH) Full-Scale Register (Middle Byte) Reset Value = 55H
bit 7 FSR15 bit 6 FSR14 bit 5 FSR13 bit 4 FSR12 bit 3 FSR11 bit 2 FSR10 bit 1 FSR09 bit 0 FSR08
DOR0 (Address 0FH) Data Output Register (Least Significant Byte) (Read Only) Reset Value = 00H
bit 7 DOR07 bit 6 DOR06 bit 5 DOR05 bit 4 DOR04 bit 3 DOR03 bit 2 DOR02 bit 1 DOR01 bit 0 DOR00
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ADS1240 AND ADS1241 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of the ADS1240 and ADS1241. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes (e.g., WREG requires the count and data bytes). Operands: n = count (0 to 127) r = register (0 to 15) x = don't care
COMMANDS RDATA RDATAC STOPC RREG WREG SELFCAL SELFOCAL SELFGCAL SYSOCAL SYSGCAL WAKEUP DSYNC SLEEP RESET
DESCRIPTION Read Data Read Data Continuously Stop Read Data Continuously Read from REG "rrrr" Write to REG "rrrr" Offset and Gain Self Cal Self Offset Cal Self Gain Cal Sys Offset Cal Sys GainCal Wakup from SLEEP Mode Sync DRDY Put in SLEEP Mode Reset to Power-Up Values
OP CODE 0000 0000 0000 0001 0101 1111 1111 1111 1111 1111 1111 1111 1111 1111 0001 (01H) 0011 (03H) 1111 (0FH) r r r r (1xH) r r r r (5xH) 0000 (F0H) 0001 (F1H) 0010 (F2H) 0011 (F3H) 0100 (F4H) 1011 (FB H) 1100 (FCH) 1101 (FDH) 1110 (FEH)
2nd COMMAND BYTE -- -- -- xxxx_nnnn (# of regs-1) xxxx_nnnn (# of regs-1) -- -- -- -- -- -- -- -- --
NOTE: The received data format is always MSB First; the data out format is set by the BIT ORDER bit in the ACR register.
TABLE IV. Command Summary.
RDATA-Read Data
Description: Read the most recent conversion result from the Data Output Register (DOR). This is a 24-bit value. Operands: Bytes: Encoding: None 1 0000 0001
RDATAC-Read Data Continuous
Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This command eliminates the need to send the Read Data Command on each DRDY. This mode may be terminated by either the STOPC command or the RESET command. Wait at least 10 fOSC after DRDY falls before reading. Operands: Bytes: Encoding: None 1 0000 0011
Data Transfer Sequence:
DIN
0000 0001
* * *(1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
DOUT
MSB
Mid-Byte
LSB
Data Transfer Sequence: Command terminated when "uuuu uuuu" equals STOPC or RESET.
DRDY
NOTE: (1) For wait time, refer to timing specification.
DIN
0000 0011
* * *(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu ***
DOUT
MSB
Mid-Byte
LSB
DRDY
***
DOUT
MSB
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
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STOPC-Stop Continuous
Description: Ends the continuous data output mode. Issue after DRDY goes LOW. Operands: Bytes: Encoding: None 1 0000 1111
SELFCAL-Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset Calibration Register (OCR) and the Full-Scale Register (FSR) are updated with new values after this operation. Operands: Bytes: Encoding: None 1 1111 0000
Data Transfer Sequence:
DRDY
Data Transfer Sequence:
DIN
xxx
0000 1111
DIN
1111 0000
RREG-Read from Registers
Description: Output the data from up to 16 registers starting with the register address specified as part of the instruction. The number of registers read will be one plus the second byte count. If the count exceeds the remaining registers, the addresses wrap back to the beginning. Operands: Bytes: Encoding: r, n 2 0001 rrrr xxxx nnnn
SELFOCAL-Offset Self Calibration
Description: Starts the process of self-calibration for offset. The Offset Calibration Register (OCR) is updated after this operation. Operands: Bytes: Encoding: None 1 1111 0001
Data Transfer Sequence:
Data Transfer Sequence: Read Two Registers Starting from Register 01H (MUX)
DIN 0001 0001 0000 0001 * * *(1) xxxx xxxx xxxx xxxx
DIN
1111 0001
SELFGCAL-Gain Self Calibration
Description: Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with new values after this operation. Operands: None 1 1111 0010 Bytes: Encoding:
DOUT
MUX
ACR
NOTE: (1) For wait time, refer to timing specification.
WREG-Write to Registers
Description: Write to the registers starting with the register address specified as part of the instruction. The number of registers that will be written is one plus the value of the second byte. Operands: Bytes: Encoding: r, n 2 0101 rrrr xxxx nnnn
Data Transfer Sequence:
DIN 1111 0010
Data Transfer Sequence: Write Two Registers Starting from 04H (DIO)
DIN 0101 0100 xxxx 0001 Data for DIO Data for DIR
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SYSOCAL-System Offset Calibration
Description: Initiates a system offset calibration. The input should be set to 0V, and the ADS1240 and ADS1241 compute the OCR value that compensates for offset errors. The Offset Calibration Register (OCR) is updated after this operation. The user must apply a zero input signal to the appropriate analog inputs. The OCR register is automatically updated afterwards. Operands: Bytes: Encoding: None 1 1111 0011
DSYNC-Sync DRDY
Description: Synchronizes the ADS1240 and ADS1241 to an external event. Operands: Bytes: Encoding: None 1 1111 1100
Data Transfer Sequence:
DIN 1111 1100
Data Transfer Sequence:
DIN 1111 0011
SLEEP-Sleep Mode
Description: Puts the ADS1240 and ADS1241 into a low power sleep mode. To exit sleep mode, issue the WAKEUP command. Operands: Bytes: Encoding: None 1 1111 1101
SYSGCAL-System Gain Calibration
Description: Starts the system gain calibration process. For a system gain calibration, the input should be set to the reference voltage and the ADS1240 and ADS1241 compute the FSR value that will compensate for gain errors. The FSR is updated after this operation. To initiate a system gain calibration, the user must apply a full-scale input signal to the appropriate analog inputs. FCR register is updated automatically. Operands: Bytes: Encoding: None 1 1111 0100
Data Transfer Sequence:
DIN 1111 1101
RESET-Reset to Default Values
Description: Restore the registers to their power-up values. This command stops the Read Continuous mode. Operands: Bytes: Encoding: None 1 1111 1110
Data Transfer Sequence:
DIN
1111 0100
Data Transfer Sequence:
DIN 1111 1110
WAKEUP
Description: Wakes the ADS1240 and ADS1241 from SLEEP mode. Operands: Bytes: Encoding: None 1 1111 1011
Data Transfer Sequence:
DIN
1111 1011
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GENERAL-PURPOSE WEIGH SCALE
Figure 8 shows a typical schematic of a general-purpose weigh scale application using the ADS1240. In this example, the internal PGA is set to either 64 or 128 (depending on the maximum output voltage of the load cell) so that the load cell output can be directly applied to the differential inputs of ADS1240.
weigh scale application using the ADS1240. The front-end differential amplifier helps maximize the dynamic range.
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
HIGH PRECISION WEIGH SCALE
Figure 9 shows the typical schematic of a high-precision
2.7V ~ 5.25V EMI Filter 2.7V ~ 5.25V
AVDD VREF+ EMI Filter AIN0 Load Cell
DVDD
VDD
DRDY SCLK ADS1240 DOUT DOUT CS EMI Filter AIN1 XIN VREF- AGND EMI Filter XOUT DGND GND MCLK SPI MSP430x4xx or other P
FIGURE 8. Schematic of a General-Purpose Weigh Scale.
2.7V ~ 5.25V EMI Filter
2.7V ~ 5.25V
AVDD VREF+ EMI Filter RI OPA2335 Load Cell RF AIN0
DVDD
VDD
DRDY SCLK
RG RF
CI
ADS1240 ADS1241
DOUT DIN CS
SPI
MSP430x4xx or other P
RI EMI Filter OPA2335 AIN1 XIN VREF- AGND EMI Filter XOUT DGND GND MCLK
G = 1 + 2 * RF/RG
FIGURE 9. Block Diagram for a High-Precision Weigh Scale.
ADS1240, 1241
SBAS173B
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21
nology used in this data sheet. In that regard, the definition of each term is given as follows: Analog Input Voltage--the voltage at any one analog input relative to AGND. Analog Input Differential Voltage--given by the following equation: (IN+) - (IN-). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 1, the positive full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when the differential is -2.5V. In each case, the actual input voltages must remain within the AGND to AVDD range. Conversion Cycle--the term conversion cycle usually refers to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time period. Data Rate--The rate at which conversions are completed. See definition for fDATA. fDATA = fOSC SPEED * 1280 * 2DR
fDATA--the frequency of the digital output data produced by the ADS1240 and ADS1241, fDATA is also referred to as the Data Rate.
PGA SETTING 1, 2, 4, 8 SAMPLING FREQUENCY
f SAMP = f SAMP =
f SAMP =
fOSC mfactor fOSC * 2 mfactor
fOSC * 4 mfactor
16
32
64, 128
f SAMP =
fOSC * 8 mfactor
Full-Scale Range (FSR)--as with most A/D converters, the full-scale range of the ADS1240 and ADS1241 is defined as the input, that produces the positive full-scale digital output minus the input, that produces the negative full-scale digital output. For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: [1.25V (positive full-scale) minus -1.25V (negative full-scale)] = 2.5V. Least Significant Bit (LSB) Weight--this is the theoretical amount of voltage that the differential voltage at the analog input has to change in order to observe a change in the output data of one least significant bit. It is computed as follows: LSB Weight = Full- Scale Range 2N - 1
128 * 2
SPEED = 0, 1 DR = 0, 1, 2 fOSC--the frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1240 and ADS1241. fMOD--the frequency or speed at which the modulator of the ADS1240 and ADS1241 is running. This depends on the SPEED bit as given by the following equation: fMOD f fOSC = OSC = mfactor 128 * 2 SPEED
where N is the number of bits in the digital output. tDATA--the inverse of fDATA, or the period between each data output.
fSAMP--the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the following equations:
SPEED = 0 mfactor 128 SPEED = 1 256
5V SUPPLY ANALOG INPUT(1) GAIN SETTING 1 2 4 8 16 32 64 128 FULL-SCALE RANGE 5V 2.5V 1.25V 0.625V 312.5mV 156.25mV 78.125mV 39.0625mV DIFFERENTIAL INPUT VOLTAGES(2) 2.5V 1.25V 0.625V 312.5mV 156.25mV 78.125mV 39.0625mV 19.531mV PGA OFFSET RANGE 1.25V 0.625V 312.5mV 156.25mV 78.125mV 39.0625mV 19.531mV 9.766mV FULL-SCALE RANGE 2 * VREF PGA
GENERAL EQUATIONS DIFFERENTIAL INPUT VOLTAGES(2) VREF PGA RANGE = 0 VREF PGA VREF 2 * PGA RANGE = 1 VREF 4 * PGA PGA SHIFT RANGE VREF 2 * PGA
NOTES: (1) With a 2.5V reference. (2) Refer to electrical specification for analog input voltage range.
TABLE VI. Full-Scale Range versus PGA Setting.
22
ADS1240, 1241
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SBAS173B
PACKAGE DRAWING
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
ADS1240, 1241
SBAS173B
www.ti.com
23
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