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5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
5890 AND 5891
BIMOS II 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
Frequently applied in non-impact printer systems, the UCN5890A, UCN5890LW, UCN5891A, and UCN5891LW are BiMOS II serial-input, latched source (high-side) drivers. The octal, high-current smartpower ICs merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS control logic (strobe and output enable) with sourcing power Darlington outputs. Typical applications include multiplexed LED and incandescent displays, relays, solenoids, and similar peripheral loads to a maximum of -500 mA per output. Except for output voltage ratings, these smart high-side driver ICs are equivalent. The UCN5890A/LW are rated for operation with load supply voltages of 20 V to 80 V and a minimum output sustaining voltage of 50 V. The UCN5891A/LW are optimized for operation with supply voltages of 5 V to 50 V (35 V sustaining). BiMOS II devices have higher data-input rates than the original BiMOS circuits. With a 5 V logic supply, they will typically operate at better than 5 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs are compatible with standard CMOS and NMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors to ensure a proper input-logic high. A CMOS serial data output, allows cascading these devices in multiple drive-line applications required by many dot matrix, alphanumeric, and bar graph displays. Suffix `A' devices are supplied in a standard dual in-line plastic package with copper lead frame for enhanced package power dissipation characteristics. Suffix `LW' devices are supplied in a standard wide-body SOIC package for surface-mount applications. Similar driver, featuring reduced output saturation voltage, are the UCN5895A and A5895SLW. Complementary, 8-bit serial-input, latched sink drivers are the Series UCN5820A.
Data Sheet 26182.12B*
GROUND CLOCK SERIAL DATA IN STROBE OUT 1 OUT 2 OUT 3 OUT 4
1 2 3 4 5 6 7 8 ST LATCHES CLK SHIFT REGISTER
16 VDD 15 OE 14 VBB 13 12 11 10 9
SERIAL DATA OUT LOGIC SUPPLY OUTPUT ENABLE LOAD SUPPLY OUT 8 OUT 7 OUT 6 OUT 5
Dwg. PP-026-2A
Note the suffix `A' devices (DIP) and the suffix `LW' devices (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = +25C
Output Voltage, VOUT (UCN5890A & UCN5890LW) .........80 V (UCN5891A & UCN5891LW) .........50 V Logic Supply Voltage Range, VDD .................................... 4.5 V to 15 V Driver Supply Voltage Range, VBB (UCN5890A/LW) ................20 V to 80 V (UCN5891A/LW) ............... 5.0 V to 50 V Input Voltage Range, VIN ........................ -0.3 V to V DD + 0.3 V Continuous Output Current, IOUT ........................................... -500 mA Allowable Package Power Dissipation, PD ......................................... See Graph Operating Temperature Range, TA .................................. -20C to +85C Storage Temperature Range, TS ................................ -55C to +150C
Caution: CMOS devices have input static protection, but are susceptible to damage when exposed to extremely high static electrical charges.
FEATURES
s s s s s 50 V or 80 V Source Outputs Output Current to -500 mA Output Transient-Suppression Diodes To 3.3 MHz Data-lnput Rate Low-Power CMOS Logic and Latches
Always order by complete part number, e.g., UCN5891LW .
5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
FUNCTIONAL BLOCK DIAGRAM
CLOCK
2.0
SUFFIX 'A', R JA = 60C/W
SERIAL DATA IN
8-BIT SERIAL-PARALLEL SHIFT REGISTER
SERIAL DATA OUT
1.5
STROBE GROUND LATCHES
VDD
1.0
MOS BIPOLAR
OUTPUT ENABLE
SUFFIX 'LW', R
0.5
JA
= 80C/W
VBB
0 25
50 75 100 125 AMBIENT TEMPERATURE IN C
150
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Dwg. GP-018B
Dwg. No. A-12,654
TYPICAL INPUT CIRCUIT
VDD
Number of Outputs ON at IOUT = -200 mA 8 7 6 5 4 3 2 1
UCN5890/91A Max. Allowable Duty Cycle at T A of 50C 53% 60% 70% 83% 100% 100% 100% 100% 60C 47% 54% 64% 75% 94% 100% 100% 100% 70C 41% 48% 56% 67% 84% 100% 100% 100%
IN
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
V BB
Number of Outputs ON at IOUT = -200 mA
OUT
UCN5890/91LW Max. Allowable Duty Cycle at T A of 50C 40% 45% 53% 62% 80% 100% 100% 100% 60C 35% 41% 48% 56% 71% 96% 100% 100% 70C 31% 36% 42% 50% 62% 84% 100% 100%
Dwg. No. A-12,648
8 7 6 5 4 3 2 1
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1985, 1999, Allegro MicroSystems, Inc.
5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 80 V (UCN5890A/LW) or 50 V (UCN5891A/LW), VDD = 5 V and 12 V (unless otherwise noted).
Characteristic Output Leakage Current Symbol I CEX VBB Max. TA = +25C TA = +70C Output Saturation Voltage VCE(SAT) 50 V IOUT = -100 mA IOUT = -225 mA IOUT = -350 mA Output Sustaining Voltage VCE(sus) Max. IOUT = -350 mA, L = 2 mH, UCN5891A/LW IOUT = -350 mA, L = 2 mH, UCN5890A/LW Input Voltage VIN(1) 50 V VDD = 5.0 V VDD = 12 V VIN(0) Input Current IIN(1) 50 V 50 V VDD = 5 V to 12 V VDD = V IN = 5.0 V VDD = V IN = 12 V Input lmpedance ZIN 50 V VDD = 5.0 V VDD = 12 V Max. Clock Frequency Serial Data Output Resistance Turn-ON Delay Turn-OFF Delay Supply Current fc ROUT 50 V 50 V VDD = 5.0 V VDD = 12 V tPLH tPHL IBB 50 V 50 V 50 V Output Enable to Output, IOUT = -350 mA Output Enable to Output, IOUT = -350 mA All outputs ON, All outputs open All outputs OFF lDD 50 V VDD = 5 V, All outputs OFF, Inputs = 0 V VDD = 12 V, All outputs OFF, Inputs = 0 V VDD = 5 V, One output ON, All Inputs = 0 V VDD = 12 V, One output ON, All Inputs = 0 V Diode Leakage Current IR Max. TA = +25C TA = +70C Diode Forward Voltage VF Open IF = 350 mA Test Conditions Min. -- -- -- -- -- 35 50 3.5 10.5 -0.3 -- -- 100 50 3.3 -- -- -- -- -- -- -- -- -- -- -- -- -- Limits Max. -50 -100 1.8 1.9 2.0 -- -- 5.3 12.3 +0.8 50 240 -- -- -- 20 6.0 2.0 10 10 200 100 200 1.0 3.0 50 100 2.0 Units A A V V V V V V V V A A k k MHz k k s s mA A A A mA mA A A V
NOTES: Turn-off delay is influenced by load conditions. Systems applications well below the specified output loading may require timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem pole configuration. Positive (negative) current is defined as going into (coming out of) the specified device pin.
5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the latches or shift register. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches.
CLOCK DATA IN
A
B
D
E C
F
STROBE BLANKING G OUTN
Dwg. No. A-12,649A
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) .......................................................................... 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................. 75 ns C. Minimum Data Pulse Width ................................................................ 150 ns D. Minimum Clock Pulse Width ............................................................... 150 ns E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns F. Minimum Strobe Pulse Width ............................................................. 100 ns G. Typical Time Between Strobe Activation and Output Transition ............................................................................ 1.0 s
TRUTH TABLE
Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN X L H X R1 R2 R3 ... P1 P2 P3 ... ... X X H RN-1 RN PN-1 PN L L L L P1 P2 P3 ... PN-1 PN ... L L Latch Contents I1 I2 I3 ... IN-1 IN Output Enable Output Contents I1 I2 I3 ... IN-1 I N
R1 R2 R3 ... X X X ...
P1 P2 P3 ...
PN-1 PN X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
TYPICAL APPLICATION
SOLENOID OR RELAY DRIVER
+5V UCN5890A
1 16 SHIFT REGISTER
+48V
DATA OUT
CLOCK DATA IN STROBE
2 3 4 5 6 7 8
VDD 15
OE 14 13 12 11 10 9
OUTPUT ENABLE (ACTIVE LOW)
LATCHES
VBB
Dwg. No. A-12,548
5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
UCN5890A and UCN5891A
Dimensions in Inches (controlling dimensions)
16 9 0.014 0.008
0.430 0.280 0.240
MAX
0.300
BSC
1 0.070 0.045
0.100 0.775 0.735
BSC
8 0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-16A in
Dimensions in Millimeters (for reference only)
16 9 0.355 0.204
10.92 7.11 6.10
MAX
7.62
BSC
1 1.77 1.15
2.54 19.68 18.67
BSC
8 0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-16A mm
NOTES: 1. Lead thickness is measured at seating plane or below. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor's option within limits shown.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
UCN5890LW and UCN5891LW
Dimensions in Inches (for reference only)
16 9 0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013
1
2
3 0.4133 0.3977
0.050
BSC
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-16A in
Dimensions in Millimeters (controlling dimensions)
16 9 0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33
1
2
3 10.50 10.10
1.27
BSC
0 TO 8
2.65 2.35 0.10 MIN.
Dwg. MA-008-16A mm
NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor's option within limits shown.
5890 AND 5891 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
BiMOS II (Series 5800) & DABiC IV (Series 6800) INTELLIGENT POWER INTERFACE DRIVERS SELECTION GUIDE
Function
8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit 9-Bit 10-Bit (active pull-downs) 12-Bit (active pull-downs) 20-Bit (active pull-downs) 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers)
Output Ratings *
SERIAL-INPUT LATCHED DRIVERS -120 mA 350 mA 350 mA 350 mA 350 mA 1.6 A -25 mA -25 mA -25 mA -25 mA 100 mA 100 mA 50 V 50 V 80 V 50 V 80 V 50 V 60 V 60 V 60 V 60 V 30 V 40 V
Part Number
5895 5821 5822 5841 5842 5829 5810-F and 6809/10 5811 and 6811 5812-F and 6812 5818-F and 6818 5833 5832
PARALLEL-INPUT LATCHED DRIVERS 4-Bit 8-Bit 8-Bit 350 mA -25 mA 350 mA 50 V 60 V 50 V 5800 5815 5801
SPECIAL-PURPOSE FUNCTIONS Unipolar Stepper Motor Translator/Driver Addressable 28-Line Decoder/Driver 1.25 A 450 mA 50 V 30 V 5804 6817
* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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