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ST70134 - ST70134A
ASCOTTM INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
s FULLY INTEGRATED AFE FOR CPE ADSL s OVERALL 12 BIT RESOLUTION, 1.1MHz
SIGNAL BANDWIDTH IN Rx
s 8.8MS/s ADC s 8.8MS/s DAC s THD: -60dB @FULL SCALE s 4-BIT DIGITAL INTERFACE TO/FROM THE
DMT MODEM TQFP64 ORDERING NUMBER: ST70134 (TQFP64) ST70134A (TQFP64) The ST70134 analog front end handles 2 transmission channels on a balanced 2 wire interconnection; a 16 to 640Kbit/s upstream transmit channel and a 1.536Mbit/s to 8.192Mbit/s downstream receive channel. This asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order analog filtering to reduce the echo and noise in both receivers and transmitters. External low noise driver and input stage used with ST70134 guarantee low noise performances. The filters, with a programmable cutoff frequency, use automatic Continuous Time Tuning to avoid time varying phase characteristic which can be of dramatic consequence for DMT modem. It requires few external components, uses a 3.3V supply. It is packaged in a 64-pin TQFP in order to reduce PCB area.
s 1V FULL SCALE INPUT s DIFFERENTIAL ANALOG I/O s ACCURATE CONTINUOUS-TIME CHANNEL
FILTERING
s 3rd & 4th ORDER TUNABLE CONTINUOUS
TIME LP FILTERS
s 0.5 WATT AT 3.3V s 0.5mm HCMOS5 LA TECHNOLOGY s 64 PIN TQFP PACKAGE
DESCRIPTION ST70134 is the Analog Front End of the STMicroelectronics ASCOTTM ADSL chipset and when coupled with ST70135A or ST70235 (DMT modem) allows to get a T1.413 Issue 2 or G.dmt compliant solution.
January 2001
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ST70134A
Figure 1 : Block Diagram
R-MOS-C TUNING
I/V-REF
XTAL-DRIVER VCXO DAC
G = -15...0dB step = 1dB TXP TXN
ADC 13 Bits DIGITAL IF
Rx (0:3)
AGCtx 1.1MHz HC2 G = 0...31dB step = 1dB RXP(0:1) RXN(0:1) AGCrx 1.1MHz HC1 138kHz SC2
DAC 12 Bits
Tx (0:3)
The Receiver (RX) Part The DMT signal coming from the line to the ST70134 is first filtered by two external filters, Pots HP and channel filters. An analog multiplexer allows the selection between two input ports which can be used to select an attenuated (0, 10dB for ex.) version of the signal in case of short loop or large echo. The signal is amplified by a low noise gain stage (0-31dB) then low-pass filtered to avoid aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise.A 13-bit A/D converter samples the data at 8.832MS/s (or 4.416MS/s in alternative mode), transforms the signal into a digital representation and sends it to the DMT signal processor via the digital interface. The Transmitter (TX) part The 12-bit data words at 8.832MS/s (or 4.416MS/ s) coming from the DMT signal processor through the digital interface are transformed by D/A converter into a analog signal. This signal is then filtered to decrease DMT sidelobes level and meet the ANSI transmitter spectral response but also to reduce the out-of-band noise (which can be echoed to the RX path) to an acceptable level. The pre-driver buffers the signal
for the external line driver and in case of short loop provide attenuation (-15...0dB). The VCXO Part The VCXO is divided in a XTAL driver and a auxiliary 8 bits DAC for timing recovery.The XTAL driver is able to operate at 35.328MHz. The DAC which is driven by the CTRLIN pin provides a current output with 8-bit resolution and can be used to tune the XTAL frequency with the help of external components. A time constant between DAC input and VCXO output can be introduced (via the CTLIN interface) and programmed with the help of an external capacitor (on VCOC pin).See chapter 'VCXO' for the external circuit related to the VCXO. The Digital Interface Part The digital part of the ST70134 can be divided in 2 sections: - The data interface converts the multiplexed data from/to the DMT signal processor into valid representation for the TX DAC and RX ADC. - The control interface allows the board processor to configure the STL70134 paths (RX/TX gains, filter band, ...) or settings (OSR, vcodac enable, digital / analog loopback,...).
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ST70134A
DMT Signal (Done by the DMT companion chip) A DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct carrier. The frequency separation of each carrier is 4.3125kHz with a total number of 256 carriers (ANSI). For N large, the signal can be modelled by a gaussian process with a certain amplitude probability density function. Since the maximum amplitude is expected to arise very rarely, we decide to clip the signal and to trade-off the resulting SNR loss against AD/DA dynamic. A clipping factor (Vpeak/Vrms = "crest factor") of 5.3 will be used resulting in a maximum SNR of 75dB. ADSL DMT signals are nominally sent at an average of -38dBmHz (-1.65dBm/carrier) with a maximal power of 15.7mW for the transmitter (upstream for ADSL over Pots, DMT carriers are Table 1 : Target Signal Levels (on the line)
ATU - R Parameter RX Max level Max RMS level Min level Min RMS level 3.95 Vpdif * 791 mVrms 42 mVpdif 8 mVrms TX 6.8 Vpdif 671 mVrms 839 mVpdif 168 mVrms RX 1.66 mVpdif 168 mVrms 54 mVpdif 11 mVrms TX 15.8 Vpdif * 3.16 Vrms 3.95 Vpdif 791 mVrms ATU - C (for reference)
from 7 to 31, for ADSL over ISDN DMT carriers are from 31 to 64). Maximum / Minimum Signal Levels The following table gives the transmitted and received signal levels for CPE (ATU-R) and, for reference, at ATU-C. All the levels are referred to the line voltages (i.e. after hybrid and transformers in TX direction, before hybrid and transformer in RX direction). Note that signal amplitudes shown below are for illustration purpose and depending on the transmit power and line impedance signal amplitudes can differ from these values. The reference line impedance for all power calculations is 100. Package The ST70134 is packaged in a 64-pin TQFP package (body size 10x10mm, pitch 0.5mm).
* Power cut back software co facility.
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ST70134A
Figure 2 : Pin Connection
AVDD1 AVDD2 DVSS2 XTALO AVSS6 AVSS1 AVSS2 RXIN1 49 48 RXIP0 RXIN0 GC1 GC0 VCOC GP2 AVDD6 AVDD5 RES RES AGND 38 37 36 35 34 33 17 DVDD2 VREF GP0 VRAP PDOWN AVSS3 RESETN RES RES 18 19 20 21 22 23 24 25 26 VRAN 27 AVDD3 28 AVDD4 29 NC0 30 NC1 31 TXP 32 TXN RES RES AVSS5 AVSS4 GP1 47 46 45 44 43 42 41 40 39 RXIP1 50 VCXO IVCO XTALI
64 TX1 TX0 NU3 NU2 NU1 NU0 CTRLIN DVSS1 CLKM 9 10 11 12 13 14 15 16 CLNIB CLWD RX3 RX2 RX1 RX0 DVDD1 8 7 6 5 4 3 2 1
63
62
61
60
59
58
57
56
55
54
53
IREF 52
RES
TX3
TX2
51
ST70134
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ST70134A
Table 2 : Pin Functions
Numbers Name Function PCB connection Supply
ANALOG INTERFACE 24 25 26 31 32 38 44 45 46 47 48 49 50 53 55 56 59 60 1 2 7 9 10 11 12 13 14 15 18 20 22 33 43 63 64 19, 21 36, 37, 39, 40, 57 VRAP VREF VRAN TXP TXN AGND VCOC GC0 GC1 RXN0 RXP0 RXN1 RXP1 IREF IVCO VCXO XTALI XTALO TX1 TX0 CTRLIN CLKM CLNIB CLWD RX3 RX2 RX1 RX0 PDOWN RESETN GP0 GP1 GP2 TX3 TX2 RES RES Positive Voltage Reference ADC Ground Reference ADC Negative Voltage Reference ADC Pre Driver Output Pre Driver Output Virtual Analog Ground (AVDD/2 = 1.65V) VCODAC Time Constant Capacitor External Gain Control Output LSB External Gain Control Output MSB Analog Receive Negative Input Gain 0 Analog Receive Positive Input Gain 0 Analog Receive Negative Input Gain 1 (Most Sensitive Input) Analog Receive Positive Input Gain 1 (Most Sensitive Input) Current Reference TX DAC/DACE Current Reference VCO DAC VXCO Control Current XTAL Oscillator Input Pin XTAL Oscillator Output Pin Digital Transmit Input, Parallel Data Digital Transmit Input, Parallel Data Serial Data Input (Settings) Master Clock Output, f = 35.328MHz Nibble Clock Output, f = 17.664MHz (OSR = 2) or ground (OSR = 4) Word Clock Output, f = 8.832/4.416MHz Digital Receive Output, Parallel Data Digital Receive Output, Parallel Data Digital Receive Output, Parallel Data Digital Receive Output, Parallel Data Power Down Select, "1" = Power Down Reset Pin (Active Low) General Purpose Output 0 (on AVDD 1) General Purpose Output 1 (on AVDD 1) General Purpose Output 2 (on AVDD 1) Digital Transmit Input, Parallel Data Digital Transmit Input, Parallel Data RESERVED RESERVED Decoupling network Decoupling network Decoupling network Line driver input Line driver input Decoupling network VCODAC cap. Echo filter output Echo filter output Echo filter output Echo filter output Decoupling network VCO bias network VCXO filter Crystal + varicap Crystal + varicap Async Interface Load = CL<30pF Load = CL<30pF Load = CL<30pF Load = CL<30pF Load = CL<30pF Load = CL<30pF Load = CL<30pF Power Down Input RC- Reset Echo filter output Echo filter output Echo filter output Load = CL<30pF Load = CL<30pF Must Be Connected to DVSS (Input) Must Be Connected to AVSS (Input) AVDD3 AVDD3 AVDD3 AVDD4 AVDD4 AVDD5 AVDD5 AVDD5 AVDD5 AVDD5 AVDD5 AVDD5 AVDD5 AVDD2 AVDD1 AVDD1 AVDD1 AVDD1 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 AVDD AVDD AVDD DVDD2 DVDD2 -
DIGITAL INTERFACE
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ST70134A
Numbers
Name
Function
PCB connection
Supply
SUPPLY VOLTAGES 8 16 17 23 27 28 34 35 41 42 51 52 54 58 61 62 SPARES 3 4 5 6 29 30 NU3 NU2 NU1 NU0 NC0 NC1 Not Used Inputs Not Used Inputs Not Used Inputs Not Used Inputs DVSS DVSS DVSS DVSS DVSS1 DVDD1 DVDD2 AVSS3 AVDD3 AVDD4 AVSS4 AVSS5 AVDD5 AVDD6 AVSS6 AVSS2 AVDD2 AVDD1 AVSS1 DVSS2 Digital I/O Supply Voltage Digital Internal Supply Voltage ADC Supply Voltage TX Pre - Drivers Supply CT Filter Supply LNA Supply DAC and Support Circuit XTAL Oscillator Supply Voltage DVSS DVDD DVDD AVSS AVDD AVDD AVSS AVSS AVDD AVDD AVSS AVSS AVDD AVDD AVSS DVSS -
Figure 3 : Grounding and Decoupling Networks
10F VRAP Pin VRAN Pin Analog VDD 4.7H L1 AVDD (Each pin must have its own capacitor) 100nF
10F
100nF
10F
100nF
10F
100nF
VREF Pin 10F 100nF 10F
IREF Pin 100nF 10F
VCOC Pin 100nF
AGND Pin 10F
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ST70134A
BLOCK DIAGRAM Application principle is described in Figure 4. A LP filter may be used on the TX path to reduce DMT sidelobes and out of band noise influence on the receiver. On the RX path, a HP filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS speech and signalling. Low pass POTS filter can be very simple for Lite - ADSL application (see Figure 4). RX Path Speech Filter An external bi-directional LC filter for up and downstream POTS service splits the speech signal from the ADSL signal to the POTS circuits. The ADSL analog front end integrated circuit does not contain any circuitry for the POTS service but it guarantees that bandwidth is not disturbed by spurious signals from the ADSL-spectrum. Figure 4 : Block Diagram
POTS Line Zo = 100 LP POTSFILTER
Channel Filters The external analog circuits provide partial echo cancellation by an analog filtering of the transmit upstream signal. This is feasible because the upstream and the downstream data are modulated on separate carriers (FDM) (see Figure 4). Signal to Noise Performance
RX- PATH SENSITIVITY AT MAXIMUM GAIN
The RX path sensitivity at the maximal RX-AGC of the receiver is defined at -140dBm/Hz (for 100 ref) on the line. This figure corresponds to the equivalent input noise of 31nVHz-1/2 seen on the line. The maximum noise density within the pass band can exceed the average value as follows: RX path (max AGC setting): <100nVHz-1/2 @ 138kHz <31nVHz-1/2 for 250kHz < f
1.1
VCXOUT 56
35.328MHz
HP POTSFILTER
60
59 9 Master Clock 35.328MHz Nibbles 17.664MHz Word 8.832/4.416MHz
VCODAC
R R
XTAL DRIVER
10 11 13 Bits A/D Converter 4 12 13 14 15
RXP(0:1) HPF + Attenuator 48 50
LNA
50k
50k
GRX
47 49
LP 1.1MHz HC1
To ST70135
RXn
2R
2R
RXN(0:1) 7 CTRLIN
20
GTX LINE DRIVER
RESETN
TXP 31 LPF 32 TXN
-15.0dB LP 138KHz SC2 * 12 Bits D/A Converter 1 TXn 2
PD
* For ADSL over ISDN, instead of SC2, HC2 1.1MHz LP filter is programmed.
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ST70134A
RX-PATH NOISE AT MINIMUM GAIN
At the minimum AGC the total average thermal noise of the analog RX-path at the ADC input should be lower than the ADC quantisation noise. The maximum noise density within the pass band can exceed the average value as follows: RX path (min AGC setting) <500nVHz-1/2 @ 138kHz < f These noise specifications correspond to 10bit resolution of the complete RX-path. Table 3 : RX Common-mode Voltage
Description Common mode signal VCM at RXIN1 and RXIN2: Value/Unit 1.6V < VCM <1.7V
This can be used to make lower gain paths in case of high input signal. Table 4 : AGC Characteristics
Description Value/Unit
Input referred noise(max. gain) 31nVHz-1/2 Max. input level Max. output level Gain range Gain and step accuracy 1Vpd 1Vpd 0 to 31dB with step = 1dB 0.3dB
AGC of RX Path The AGC gain in the RX-path is controlled through a 5-bits digital code. Four inputs are provided for RX input and the selection is made with the RXMUX bits of the CTRLIN interface. Table 5 : Integrated HC Filter Characteristics
Description Maximum input level Maximum output level Type Frequency band Frequency tuning Max. in-band ripple Matlab Model Default cut off frequency @ -3dB Actual cut off @ -3dB HC Freq. selection register
RX Filters The combination of the external filter (an LC ladder filter typically) with the integrated lowpass filter must provide: - Echo reduction to improve dynamic range. - DMT sidelobe and out of band (anti-aliasing) attenuation. - Anti alias filter (60dB rejection @ image frequency). RX Filters The integrated filter have the following characteristics:
Value / Unit 1Vpd 1Vpd 3rd order butterworth 1.104MHz (0% setting, see below) -43.75% -> +0% 1dB [B, A] = butter (3, w0, 's') F0 = 1560KHz w0 = 2 * pi * F0/((20 + n)/16) n = -4,..,3 see (AFE settings,Table 19)
Table 6 : Phase Characteristic
Description Total RX filter group delay Total RX filter group delay distortion Value / Unit < 50s @ 138kHz < f < 1.104MHz < 15s @ 138kHz < f < 1.104MHz
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ST70134A
Figure 5 : HC Filter Mask for RX
Amplitude 0dB 1dB
5dB 36dB 50dB
30
1104 2208 7728 16560
kHz
Note: The total RX path (including ADC) group delay distortion is 16s (i.e. = 15s + 1s of ADC) Linearity of RX Linearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5Vpd amplitude (total 1Vpd) at the output of the RX - AGC amplifier (i.e: before the ADC) for the case of minimal AGC setting. Table 7 lists the RX path intermodulation distortion (as S/IM3 ratio) in downstream and upstream bandwidth. Table 7 : Linearity of RX
f1 (0.5Vpd) f2 (0.5Vpd) S/IM3 (AGC = 0dB) 300kHz 200kHz 59.5dB @ 100kHz 53.5dB @ 400kHz 43.5dB @ 700kHz 42.5dB @ 800kHz 500kHz 400kHz 59.5dB @ 300kHz 48.0dB @ 600kHz 700kHz 600kHz 48.0dB @ 500kHz 42.5dB @ 800kHz
Table 8 : RX Filter to A/D Interface
RX filter to A/D maximal level: 1Vpd = full scale of A/D
Table 9 : A/D Converters
Numbers of bits: Minimum resolution of the A/D converter Linearity error of the A/D converter Full scale input range: Sampling rate: Maximum attenuation at 1.1MHz: Maximum group delay: Maximum group delay distortion: 11bits <1LSB (out of 12bits) 1 Vpdif 5% 8.832MHz (or 4.416MHz in OSR = 2 mode) <0.5dB without in-band ripple <3s <1s 12bits
Power Supply Rejection The noise on the power supplies for the RX path must be lower than the following: <50mVrms in band white noise for any AVDD. In this case, PSR (power supply rejection) of ST70134 RX path is lower than -43dB.
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ST70134A
TX Pre-driver Capability The pre-driver drives an external line power amplifier which transmits the required power to the line. Table 10 : TX Pre-driver
TX drive level to the external line driver for max. AGC setting External line driver input impedance: Pre-driver characteristics: Closed loop gain: Output characteristics Output offset voltage (0dB) Output noise voltage (0dB) < 10mV 0dB < 150nVHz-1/2 @ f > 250kHz -1/2 @ 34.5kHz < f < 138kHz < 500nVHz 1.6V < Vcm < 1.7V -15dB...0dB with step = 1dB resistive capacitive 1.5 Vpdif > 500 < 30pF
Output common mode voltage:
TX Filter The TX filter acts not only to suppress the DMT sidebands but also as smoothing filter on the D/A convertor's output to suppress the image spectrum. For this reason it must be realized in a continuous time approach. ATU-R TX Filter The purpose of this filter is to remove out-of-band noise of the TX path echoed to the RX path. In order to meet the transmitter spectral response, an additional filtering must be (digitally) performed. The integrated filter has the following characteristics: Table 11 : Integrated SC Filter Characteristics
Description Maximum input level Maximum output level Type Frequency band Frequency tuning Max. in-band ripple Matlab Model Default cut-off frequency @ -3dB Actual cut-off @ -3dB SC Frequency selection register Total TX filter group delay Total TX filter group delay distortion 1Vpd 1Vpd 4th order chebytchef 138kHz (0% setting see below) -25% -> +25% 1dB [B,A] = cheby1 (4,0.5,W0,'s') {ripple = 0.5} F0 = 151.8kHz W0 = 2*pi*F0/((17+n)/16) n = -4,..,3 see (AFE settings, Table 19) < 50s @ 34.5kHz < f < 138kHz < 20s @ 34.5kHz < f < 138kHz Value/Unit
Note: The total TX path (including DAC) group delay distortion is 16s (i.e. = 15s + 1s of DAC).
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ST70134A
Figure 6 : SC Filter Mask for TX
Amplitude 1dB 0dB 20dB
30
138 250
kHz
Table 12 : D/A Converter (A current steering architecture is used)
Description Numbers of bits: Minimum resolution of the D/A converters Linearity error of the A/D converter Full scale input range: Sampling rate: Maximum group delay: Maximum group delay distortion: 12bits 11bits <1LSB (out of 12bits) 1 Vpdif 5% 8.832MHz (or 4.416MHz in compatible mode) <3s <1s Value / Unit
Linearity in TX Linearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5Vpd amplitude (total 1Vpd) at the output of the pre-driver for the case of a total AGC = 0dB. Table 13 : Linearity in TX
f1 (0.5Vpd) f2 (0.5Vpd) S/IM3 (AGC = 0 dB) 80kHz 70kHz 59.5dB (@ 60KHz, 90KHz)
TX Idle Channel Noise The idle channel noise specifications correspond with 11bit resolution of the complete TX-path. TX idle channel output noise on TXP, TXN. Table 14 : TX idle channel noise
For max AGC setting (0dB) In-band noise Out-of-band noise For min AGC setting (=-15dB) In-band noise 500nVHz-1/2 @ 34kHz -138kHz 1.6VHz-1/2 150nVHz-1/2 @ 34.5kHz -138kHz @ 250kHz -1.104MHz
Power Supply Rejection The noise on the power supplies for the TX-path must be lower than the following: < 50mVrms in-band white noise for AVDD. < 15mVrms in-band white noise for Pre-driver AVDD. VCXO A voltage controlled crystal oscillator driver is integrated in ST70134. The nominal frequency is 35.328MHz. The quartz crystal is connected between the pins XTALI and XTALO. The principle of the VCXO control is shown in Figure 7.
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ST70134A
The information coming from the digital processor via the CTRLIN path is used to drive an 8-bit DAC which generates a control current. This current is externally converted and filtered to generate the required control voltage (range:-15V to 0.5V) for the varicap. The VCXO circuit characteristics are given in Table 15. Table 15 : VCXO circuit Characteristics
Symbol fabs frange IO Ii Parameter Absolute frequency accuracy Frequency Tuning Range VCXO Output Current Reference Input Current 100A Minimum -15ppm Nominal 35.328MHz 50ppm 100A 1mA Rref = 16.5k AVDD = 3.3V AVDD = 3.3V Maximum +15ppm Note
N.B: frequency tuning range is proportional to the crystal dynamic capacitance Cm. Figure 7 : Principle of VCXO control
AVDD Cs VCOC 44 1M 8 Bits CTRLIN 7 DAC 30% 56 Io = li Filtered VCXO (see CTRLIN table) XTALO Clk35 60 Cp Ct Rt AGND VCXO 55 IVCO li AVDD/22 / AVDD/2 Rref AVDD
59 XTALI
-15V
The tuning must be monotonic with 8-bit resolution with the worst-case tuning step of <2ppm/LSB (8-bit). The time constant of the tuning must be variable from 5s to 10s through an external capacitor Cs (R = 1M 30%). This determines the speed of the VCXO in normal operation (slow speed in "show time") with filtered VCXO. For faster tracking, the previous filter is not used and the speed depends on CtRt. DIGITAL INTERFACE Control Interface The digital setting codes for the ST70134 configuration are sent over a serial line (CTRLIN) using the word clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit ('0'), the three LSBs being used to identify the data contained in the 12 remaining bits.
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Note
LSB RX SETTINGS b10 0 0 0 0 0 0 X 1 0 0 1 1 b10 0 0 0 0 0 X b10 0 0 0 0 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 1 1 1 1 1 1 1 1 X X 0 0 1 b0 0 0 0 0 0 0 0 0 Normal Mode (Digital path) Digital Loopback (digital TX to digital RX - DAC not used) Normal Mode (Analog path) Analog loopback (RXi to TXi - ADC not used) 1 VCO DAC disabled VCO DAC enabled HC2 filter disabled HC2 filter enabled (init) (init) (init) 0 0 0 0 0 1 0 1 0 1 0 1 0 1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 0 Normal mode Filter selection TX SETTINGS Transmit TX - AGC setting -15dB Transmit TX - AGC setting -14dB Transmit TX - AGC setting (X - 15) dB Transmit TX - AGC setting 0dB Not used General Purpose Output (GPO) setting AFE SETTINGS (init) (init) (init = 000) (init) 0 0 0 0 Force HC1 for RX path 1 0 0 0 Force HC2 for RX path, TX grounded 0 0 0 0 Normal mode Filter selection 1 1 1 0 0 0 AGC RX Gain setting 31dB (init) X X X 0 0 0 AGC RX Gain setting XdB 0 0 1 0 0 0 AGC RX Gain setting 1dB 0 0 0 0 0 0 AGC RX Gain setting 0dB 0 0 Rx input selected = RXIN1, RXIP1 (init) 0 0 Rx input selected = RXIN0, RXIP0 (init) 0 0 External Gain Control GC0 (init = 0) 0 0 External Gain Control GC1 (init = 0) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
MSB
b15
b14
b13
b12
b11
0
X
0
X
0
0
0
1
0
0
0
0
0
X
0
1
0
Table 16 : Control Interface Bit Mapping
0
0
0
b15
b14
b13
b12
b11
0
0
0
0
0
0
0
0
0
1
0
X
X
X
X
0
1
1
1
1
1. After initialization, this bit has to be cleared (0) to make the device properly operate.
0
0
b15
b14
b13
b12
b11
0
0
0
1
0
0
0
1
0
0
0
1
0
0
ST70134A
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0
1
MSB b10 0 1 1 0 1 1 0 0 1 b10 0 X 1 b10 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 b10 X X X X X X X X X X X X X X X b9 b8 b7 b6 b5 X X X b4 X X X b3 X X X 1 1 1 1 1 1 1 1 b2 1 1 1 1 1 0 0 0 0 0 0 0 0 b1 0 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 b0 1 0 1 RESERVED RESERVED RESERVED 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 0 HFC2 Active HFC2 in powerdown HFC1 Active HFC1 in powerdown SCF2 Active SCF2 in powerdown LNA Active LNA in powerdown DAC Active DAC in powerdown VCODAC Active VCODAC in powerdown XTAL Active XTAL in powerdown RESERVED 0 0 ADC Active ADC in powerdown 0 0 N.U. 0 0 N.U. 0 0 TXD in powerdown 0 0 TXD Active 0 0 0 0 0 0 0 1 0 0 Init b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 0 1 1 X X X 0 1 1 VCO DAC CURRENT value @ X VCO DAC CURRENT value @ MAXIMUM POWER DOWN ANALOG BLOCK SETTINGS 0 0 0 0 1 1 VCO DAC CURRENT value @ MINIMUM b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VCO DAC VALUE SETTINGS 0 1 0 VCXO output filtered 0 1 0 VCXO output NOT filtered ("show-time") 1 1 0 1 0 HC freq. selection: Fc ~ 768kHz * (init) 0 0 0 1 0 HC freq. selection: Fc = 1.104MHz 0 1 0 1 0 SC freq. selection: Fc ~ 170kHz * (init) * 1 1 0 1 0 SC freq. selection: Fc ~ 110kHz * 1 1 0 1 0 SC freq. selection: Fc = 138kHz (init) * 0 1 0 OSR set to 2 0 1 0 OSR set to 4 (init) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AFE SETTINGS
LSB
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b15
b14
b13
b12
b11
0
ST70134A
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
0
0
0
0
0
0
X
X
X
X
0
1
1
1
1
b15
b14
b13
b12
b11
0
0
0
0
0
0
0
0
1
Table 17 : Control Interface Bit Mapping (continued)
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
* For each filter, 8 possible frequency values (see Table 5 and Table 11). Notation is 2's complement range from -4 = 100b +3 = 011b. Fc is the frequency band (-1dB)
0
X
X
X
X
0 0
X X
X X
X X
X X
ST70134A
Control Interface Timing The word clock (CLWD) is used to sample at negative going edge the control information. The start bit b15 is transmitted first followed by bits b[14:0] and at least 16 stop bits need to be provided to validate the data. Figure 8 : Control Interface
CLWD
CTRLIN >=16 Stop Bits = High
Start Bit
Data ID.
Data set-up and hold time versus falling edge CLWD must be greater than 10nsec. Receive / Transmit Interface RECEIVE / TRANSMIT PROTOCOL The digital interface is based on 4 x 8.832MHz (35.328MHz) data lines in the following manner: If OSR = 2 (OSR bit set to 1) is selected, CLKNIB is used as nibble clock (17.664MHz, disabled in normal mode), and all the RXi, TXi, CLKWD periods are twice as long as in normal mode. This ensures a compatibility with lower speed products. TX Signal Dynamic The dynamic of data signal for both TX DACs is 12 bits extracted from the available signed 16 bit representation coming from the digital processor. The maximal positive number is 214-1, the most negative number is -214 , the 3 LSBs are filled with '0'. Any signal exceeding these limits is clamped to the maximum value. Table 18 : TX Data Bit Map
BIT MAP/NIBBLE TXD0 TXD1 TXD2 TXD3 N0 not used not used not used d0 = data bit 0 (LSB) N1 data bit 1 data bit 2 data bit 3 data bit 4 N2 data bit 5 data bit 6 data bit 7 data bit 8 N3 data bit 9 data bit 10 data SIGN data SIGN
Table 19 : TX Nibble Bit Map
N3 sign sign d10 d9 d8 d7 N2 d6 d5 d4 d3 N1 d2 d1 d0 n.u. N0 n.u. n.u.
The two sign bits must be identical.
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RX Signal Dynamic The dynamic of the signal from the ADC is limited to 13bits. Those bits are converted to a signed (2's complement) representation with a maximal positive number of 214 -1 and a most negative number -214. The 2 LSBs are filled with '0'. Table 20 : RX Data Bit Map
BIT MAP/NIBBLE RXD0 RXD1 RXD2 RXD3 N0 0 0 d0 = data bit 0 (LSB) data bit 1 N1 data bit 2 data bit 3 data bit 4 data bit 5 N2 data bit 6 data bit 7 data bit 8 data bit 9 N3 data bit 10 data bit 11 data SIGN data SIGN
Table 21 : RX Nibble Bit Map
N3 sign sign d11 d10 d9 d8 N2 d7 d6 d5 d4 N1 d3 d2 d1 d0 N0 0 0
The two sign bits must be identical. Figure 9 : TX/ RX Digital Interface Timing
CLKM 35.328MHz CLWD 8.832MHz TXDx/RXDx N0 N1 N2 N3 OSR = 4 CLKNIB 17.664MHz CLWD 4.4162MHz TXDx/RXDx N0 N1 OSR = 2 N2 N3
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ST70134A
Receive / Transmit Interface Timing The interface is a quadruple (RX, TX) nibble serial interface running at 8.8MHz sampling (normal mode). The data are represented in 16bits format, and transferred in groups of 4 bits (nibbles). The LSBs are transferred first. The ST70134 generates a nibble clock (CLKM master clock in normal mode, CLKNIB in OSR = 2 mode) and word signals shared by the three interfaces. Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the falling edge of CLKM/CLKNIB. This holds for the data stream from ST70134 and from the digital processor. Data, CLWD setup and hold times are 5ns with reference to the falling edge of CLKM/CLKNIB. (not floating). Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going edge of CLKM/CLKNIB. This holds for the data stream from ST70134 and from the digital processor.Data, CLWD setup and hold times are 5ns with reference to the falling edge of CLKM/ CLKNIB. (not floating). Power Down When pin Pdown = "1", the chip is set in power down mode. As the Pdown signal is synchronously sampled, minimum duration is 2 periods of the 35MHz clock. In this mode all analog functional blocks are deactivated except: preamplifiers (TX), clock circuits for output clock CLKM. Pdown will not affect the digital part of the chip. Anyway, after a Pdown transition, the digital part status, is updated after 3 clock periods (worst case). The chip is activated when Pdown = "0". In power down mode the following conditions hold: - Output voltages at TXP/TXN = AGND - Preamplifier is on with maximum gain setting (0dB), (digital gain setting coefficients are overruled) - The XTAL output clock on pin CLKM keeps running. - All digital setting are retained. - Digital output on pins RXDx don't care(not floating). In power-down mode the power consumption is 100mW. Following external conditions are added: - Clock pin CLW is running. - CTRLIN signals can still be allowed. - AGND remains at AVDD/2 (circuit is powered up) - Input signal at TXDx inputs are not strobed. The Pdown signal controls asynchronously the power-down of each analog module: - After a few s the analog channel is functional - After about 100ms the analog channel delivers full performance Reset Function The reset function is implied when the RESETN pin is at a low voltage input level. In this condition, the reset function can be easily used for power up reset conditions. Detailed Description During reset: (reset is asynchronous, tenths of ns are enough to put the IC in reset). All clock outputs are deactivated and put to logical "1" (except for the XTAL and master clock CLKM). After reset: (4 clock periods after reset transition, as worst case). - OSR = 4 - All analog gains (RX, TX) are set to minimum value - Nominal filter 1.104MHz) frequency bands (138kHz,
- LNA input = "11" (max. attenuation) - VCO dac disabled Digital outputs are placed in don't care condition (non-floating). N.B. If a Xtal oscillator is used, the RESET must be released at last 10s after power-on, to ensure a correct duty cycle for the clk35 clock signal.
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ST70134A
ELECTRICAL RATINGS AND CHARACTERISTICS Absolute Maximum Ratings
Symbol VDD Vin Tstg TL ILU IAVDD IAVDD IDVDD IDVDD Parameter Any VDD Supply Voltage, related to substrate Voltage at any input pin Storage Temperature Lead Temperature (10 second soldering) Latch - up current @80C Analog Supply Current @ 3.6V - normal operation Analog Supply Current @ 3.6V - power down Analog Supply Current @ 3.6V - normal operation Analog Supply Current @ 3.6V - power down 100 165 30 56 50 Minimum - 0.5 -0.5 -40 Maximum 5 VDD +0.5 125 300 Unit V V xC xC mA mA mA mA mA
Thermal Data
Symbol Rth j-amb Thermal and Junction ambient Parameter Value 50 Unit C/W
Operating Conditions (Unless specified, the characteristic limits of 'Static Characteristics' in this document apply over an Top = -40 to 80C; VDD within the range 3 to 3.6V ref. to substrate.
Symbol AVDD DVDD Vin /Vout Pd Tamb Tj Parameter AVDD Supply Voltage, related to substrate DVDD Supply Voltage, related to substrate Voltage at any input and output pin Power Dissipation Ambient Temperature Junction Temperature Minimum 3.0 2.7 0 0.4 -40 -40 Maximum 3.6 3.6 VDD 0.6 80 110 Unit V V V W C C
STATIC CHARACTERISTICS Digital Inputs Schmitt-trigger inputs: TXi, CTRLIN, PDOWN, RESETN
Symbol VIL VIH VH Cimp 18/22 Parameter Low Level Input Voltage High Level Input Voltage Hysteresis Input Capacitance 0.7 x DVDD 1.0 1.3 3 Test Condition Minimum Typical Maximum 0.3 x DVDD Unit V V V pF
ST70134A
Digital Outputs Hard Driven Outputs: RXi
Symbol VOL VOH Cload Parameter Low Level Output Voltage High Level Output Voltage Load Capacitance Test Condition Iout = -4mA Iout = 4mA 0.85 x DVDD 30 Minimum Typical Maximum 0.15 x DVDD Unit V V pF
Clock Driver Output: CLKM, CLNIB, CLKWD
Symbol VOL VOH Cload DC Parameter Low Level Output Voltage High Level Output Voltage Load Capacitance Duty Cycle 45 Test Condition Iout = -4mA Iout = 4mA 0.85 x DVDD 30 55 Minimum Typical Maximum 0.15 x DVDD Unit V V pF %
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ST70134A
PACKAGE MECHANICAL DATA Figure 10 : Package Outline TQFP64
A A2 64 e A1 49 0,10 mm .004 inch SEATING PLANE
1
48
16
33
E3 E1 E
17
D3 D1 D
32
L1
L
K
0,25 mm .010 inch GAGE PLANE
Millimeter Dimension Minimum A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0 (minimum), 7 (maximum) 0.75 0.0157 Typical Maximum 1.60 0.15 1.45 0.28 0.20 0.002 0.053 0.007 0.0047 Minimum
B
c
Inch Typical Maximum 0.063 0.006 0.055 0.009 0.0063 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0236 0.0393 0.0295 0.057 0.011 0.0079
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ST70134A
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - All Rights Reserved
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