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1CY 7C34 0 Family
EPL D
fax id: 6100
CY7C340 EPLD Family
Multiple Array Matrix High-Density EPLDS
Features
* Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions * 0.8-micron double-metal CMOS EPROM technology (CY7C34X) * Advanced 0.65-micron CMOS technology to increase performance (CY7C34XB) * Multiple Array MatriX architecture optimized for speed, density, and straightforward design implementation -- Programmable Interconnect Array (PIA) simplifies routing -- Flexible macrocells increase utilization -- Programmable clock control -- Expander product terms implement complex logic functions * Warp2(R) -- Low-cost VHDL compiler for CPLDs and PLDs -- IEEE 1164-compliant VHDL -- Available on PC and Sun platforms * Warp3(R) -- VHDL synthesis -- ViewLogic graphical user interface -- Schematic capture (ViewDrawTM) -- VHDL simulation (ViewSimTM) -- Available on PC and Sun platforms tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. The MAX architecture makes it ideal for replacing large amounts of TTL SSI and MSI logic. For example, a 74161 counter utilizes only 3% of the 128 macrocells available in the CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes less than 1% of the over 1,000 product terms in the CY7C342B. This allows the designer to replace 50 or more TTL packages with just one MAX EPLD. The family comes in a range of densities, shown below. By standardizing on a few MAX building blocks, the designer can replace hundreds of different 7400 series part numbers currently used in most digital systems. The family is based on an architecture of flexible macrocells grouped together into Logic Array Blocks (LABs). Within the LAB is a group of additional product terms called expander product terms. These expanders are used and shared by the macrocells, allowing complex functions of up to 35 product terms to be easily implemented in a single macrocell. A Programmable Interconnect Array (PIA) globally routes all signals within devices containing more than one LAB. This architecture is fabricated on the Cypress 0.8-micron, double-layer-metal CMOS EPROM process, yielding devices with significantly higher integration, density and system clock speed than the largest of previous generation EPLDs. The CY7C34XB devices are 0.65-micron shrinks of the original 0.8-micron family. The CY7C34XBs offer faster speed bins for each device in the Cypress MAX family. The density and performance of the CY7C340 family is accessed using Cypress's Warp2 and Warp3 design software. Warp2 provides state-of-the-art VHDL synthesis for MAX and FLASH370TM at a very low cost. Warp3 is a sophisticated CAE tool that includes schematic capture (ViewDraw) and timing simulation (ViewSim) in addition to VHDL synthesis. Consult the Warp2 and Warp3 datasheets for more information about the development tools.
General Description
The Cypress Multiple Array Matrix (MAX(R)) family of EPLDs provides a user-configurable, high-density solution to general-purpose logic integration requirements. With the combina-
Max Family Members
Feature Macrocells MAX Flip-Flops MAX MAX Latches[1] Inputs[2] CY7C344(B) 32 32 64 23 16 28H,J,W,P CY7C343(B) 64 64 128 35 28 44H,J CY7C342B 128 128 256 59 52 68H,J,R CY7C346(B) 128 128 256 84 64 84H,J 100R,N CY7C341B 192 192 384 71 64 84H,J,R
MAX Outputs Packages
Key: P--Plastic DIP; H--Windowed Ceramic Leaded Chip Carrier; J--Plastic J-Lead Chip Carrier; R--Windowed Pin Grid Array; W--Windowed Ceramic DIP; N--Plastic Quad Flat Pack
Notes: 1. When all expander product terms are used to implement latches. 2. With one output.
PAL is a registered trademark of Advanced Micro Devices. MAX is a registered trademark of Altera Corporation. FLASH370 is a trademark of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. ViewDraw and ViewSim are trademarks of ViewLogic Corp.
Cypress Semiconductor Corporation
*
3901 North First Street
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San Jose * CA 95134 * 408-943-2600 December 1988 - Revised October 1995
CY7C340 EPLD Family
DEDICATED INPUTS
MULTIPLE ARRAYS (LABS) LOGIC BLOCK ARRAY (LAB)
DUAL I/O FEEDBACK EXPANDER PRODUCT TERMS
MACROCELLS
PROGRAMMABLE INTERCONNECT ARRAY (PIA)
C340-1
Figure 1. Key MAX Features
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CY7C340 EPLD Family
Functional Description
The Logic Array Block The logic array block, shown in Figure 2, is the heart of the MAX architecture. It consists of a macrocell array, expander product term array, and an I/O block. The number of macrocells, expanders, and I/O vary, depending upon the device used. Global feedback of all signals is provided within a LAB, giving each functional block complete access to the LAB resources. The LAB itself is fed by the programmable interconnect array and dedicated input bus. The feedbacks of the macrocells and I/O pins feed the PIA, providing access to them through other LABs in the device. The members of the CY7C340 family of EPLDs that have a single LAB use a global bus, so a PIA is not needed (see Figure 3). The MAX Macrocell Traditionally, PLDs have been divided into either PLA (programmable AND, programmable OR), or PAL(R) (programmable AND, fixed OR) architectures. PLDs of the latter type provide faster input-to-output delays, but can be inefficient due to fixed allocation of product terms. Statistical analysis of PLD logic designs has shown that 70% of all logic functions (per macrocell) require three product terms or less. The macrocell structure of MAX has been optimized to handle variable product term requirements. As shown in Figure 4, each macrocell consists of a product term array and a configurable register. In the macrocell, combinatorial logic is implemented with three product terms ORed together, which then feeds an XOR gate. The second input to the XOR gate is also controlled by a product term, providing the ability to control active HIGH or active LOW logic and to implement T- and JK-type flip-flops.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A A A A MACROCELL I/O A A A I/O A ARRAY PINS A A A BLOCK A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A EXPANDER A A A A PRODUCT A A A A TERM A A ARRAY A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A
C340-2
If more product terms are required to implement a given function, they may be added to the macrocell from the expander product term array. These additional product terms may be added to any macrocell, allowing the designer to build gate-intensive logic, such as address decoders, adders, comparators, and complex state machines, without using extra macrocells. The register within the macrocell may be programmed for either D, T, JK, or RS operation. It may alternately be configured as a flow-through latch for minimum input-to-output delays, or bypassed entirely for purely combinatorial logic. In addition, each register supports both asynchronous preset and clear, allowing asynchronous loading of counters of shift registers, as found in many standard TTL functions. These registers may be clocked with a synchronous system clock, or clocked independently from the logic array. Expander Product Terms The expander product terms, as shown in Figure 5, are fed by the dedicated input bus, the programmable interconnect array, the macrocell feedback, the expanders themselves, and the I/O pin feedbacks. The outputs of the expanders then go to each and every product term in the macrocell array. This allows expanders to be "shared" by the product terms in the logic array block. One expander may feed all macrocells in the LAB, or even multiple product terms in the same macrocell. Since these expanders feed the secondary product terms (preset, clear, clock, and output enable) of each macrocell, complex logic functions may be implemented without utilizing another macrocell. Likewise, expanders may feed and be shared by other expanders, to implement complex multilevel logic and input latches.
I N P U T S
P I A
I N P U T S
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A A A A MACROCELL I/O A A A I/O A ARRAY PINS A A A BLOCK A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A EXPANDER A A A A PRODUCT A A A A TERM A A A A ARRAY A A A A A A A A A A A A A A A A A A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A
C340-3
PROGRAMMABLE INTERCONNECT ARRAY
Figure 2. Typical LAB Block Diagram
Figure 3. 7C344 LAB Block Diagram
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CY7C340 EPLD Family
16 MACROCELL FEEDBACKS (32 FOR 7C344)
PROGRAMMABLE INTERCONNECT SIGNALS
D PROGRAMMABLEFLIP-FLOP
(D, T,JK,SR)
D REGISTEREDORFLOW-
I/O OUTPUT ENABLE
THROUGH-LA TCH OPERATION
D PROGRAMMABLECLOCK D ASYNCCLEARANDPRESET
PRESET
P
TO I/O CONTROL
Q C
ARRAY CLOCK
CLEAR
MACROCELL FEEDBACK
NOTE: ONE SYSTEM CL OCK PER LAB 8 DEDICATED INPUTS 32 EXPANDER PRODUCT TERMS (64 FOR 7C344)
TO PIA
C340-4
Figure 4. Macrocell Block Diagram
MACROCELL P-TERMS
I/O OUTPUT ENABLE
FROM MACROCELL IN LAB
I/O PAD
THREE-STATE BUFFER
TO PIA (LAB FOR 7C344) EXPANDER P-TERMS C340-5
C340-6
Figure 5. Expander Product Terms
Figure 6. I/O Block Diagram
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CY7C340 EPLD Family
I/O Block Separate from the macrocell array is the I/O control block of the LAB. Figure 6 shows the I/O block diagram. The three-state buffer is controlled by a macrocell product term and the drives the I/O pad. The input of this buffer comes from a macrocell within the associated LAB. The feedback path from the I/O pin may feed other blocks within the LAB, as well as the PIA. By decoupling the I/O pins from the flip-flops, all the registers in the LAB are "buried," allowing the I/O pins to be used as dedicated outputs, bidirectional outputs, or as additional dedicated inputs. Therefore, applications requiring many buried flip-flops, such as counters, shift registers, and state machines, no longer consume both the macrocell register and the associated I/O pin, as in earlier devices. The Programmable Interconnect Array PLD density and speed has traditionally been limited by signal routing; i.e., getting signals from one macrocell to another. For smaller devices, a single array is used and all signals are available to all macrocells. But as the devices increase in density, the number of signals being routed becomes very large, increasing the amount of silicon used for interconnections. Also, because the signal must be global, the added loading on the internal connection path reduces the overall speed performance of the device. The MAX architecture solves these problems. It is based on the concept of small, flexible logic array blocks that, in the larger devices, are interconnected by a PIA. The PIA solves interconnect limitations by routing only the signals needed by each LAB. The architecture is designed so that every signal on the chip is within the PIA. The PIA is then programmed to give each LAB access to the signals that it requires. Consequently, each LAB receives only the signals needed. This effectively solves any routing problems that may arise in a design without degrading the performance of the device. Unlike masked or programmable gate arrays, which induce variable delays dependent on routing, the PIA has a fixed delay from point to point. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic.
Warp3 Warp3 is a sophisticated design tool that is based on the latest version of ViewLogic's CAE design environment. Warp3 features schematic capture (ViewDraw), VHDL waveform simulation (ViewSim), a VHDL debugger, and VHDL synthesis, all integrated in a graphical design environment. Warp3 is available on PCs using Windows 3.1 or subsequent versions, and on Sun and HP workstations.
For further information on Warp software, see the Warp2 and Warp3 datasheets contained in this data book. Third-Party Software Cypress maintains a very strong commitment to third-party design software vendors. All major third-party software vendors provide support for the MAX family of devices. To expedite this support, Cypress supplies vendors with all pertinent architectural information as well as design fitters for our products.
Programming
The Impulse3TM device programmers from Cypress will program all Cypress PLDs, CPLDs, FPGAs, and PROMs. The unit is a standalone programmer that connects to any IBM-compatible PC via the printer port. Third-Party Programmers As with development software, Cypress strongly supports third-party programmers. All major third-party programmers support the MAX family.
Cross Reference
ALTERA PREFIX EPM PREFIX: EP 22V10-10C 22V10-10C 22V10-10C 22V10-10C 22V10-15C 22V10-15C 5032DC 5032DC-2 5032DC-15 5032DC-17 5032DC-20 5032DC-25 5032DM 5032DM-25 5032JC 5032JC-2 5032JC-15 5032JC-17 5032JC-20 5032JC-25 CYPRESS PREFIX: CY PREFIX: PALC PALC22V10D-7C PALC22V10D-10C PAL22V10C-7C+ PAL22V10C-10C+ PALC22V10B-15C PALC22V10D-15C 7C344-25WC 7C344-20WC 7C344-15WC Call Factory 7C344-20WC 7C344-25WC 7C344-25WMB 7C344-25WMB 7C344-25HC 7C344-20HC 7C344-15HC Call Factory 7C344-20HC 7C344-25HC
Development Software Support
Warp2 Warp2 is a state-of-the-art VHDL compiler for designing with Cypress PLDs and CPLDs. Warp2 utilizes a proper subset of IEEE 1164 VHDL as its Hardware Description Language (HDL) for design entry. VHDL provides a number of significant benefits for the design entry process. Warp2 accepts VHDL input, synthesizes and optimizes the entered design, and outputs a JEDEC map for the desired device. For functional simulation, Warp2/ provides a graphical waveform simulator (NOVA).
VHDL (VHSIC Hardware Description Language) is an open, powerful, non-proprietary language that is a standard for behavioral design entry and simulation. It is already mandated for use by the Department of Defense, and supported by every major vendor of CAE tools. VHDL allows designers to learn a single language that is useful for all facets of the design process.
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CY7C340 EPLD Family
Cross Reference (continued)
ALTERA 5032JM 5032JM-25 5032LC 5032LC-2 5032LC-15 5032LC-17 5032LC-20 5032LC-25 5032PC 5032PC-2 5032PC-15 5032PC-17 5032PC-20 5032PC-25 5064JC 5064JC-1 5064JC-2 5064JI 5064JM 5064LC 5064LC-1 5064LC-2 5128AGC-12 5128AGC-15 5128AGC-20 5128AJC-12 5128AJC-15 5128AJC-20 5128ALC-12 5128ALC-15 5128ALC-20 5128GC 5128GC-1 5128GC-2 5128GM 5128JC 5128JC-1 5128JC-2 5128JI 5128JI-2 5128JM 5128LC 5128LC-1 5128LC-2 CYPRESS 7C344-25HMB 7C344-25HMB 7C344-25JC 7C344-20JC 7C344-15JC Call Factory 7C344-20JC 7C344-25JC 7C344-25PC 7C344-20PC 7C344-15PC Call Factory 7C344-20PC 7C344-25PC 7C343-35HC 7C343-25HC 7C343-30HC 7C343-35HI 7C343-35HMB 7C343-35JC 7C343-25JC 7C343-30JC 7C342B-12RC 7C342B-15RC 7C342B-20RC 7C342B-12HC 7C342B-15HC 7C342B-20HC 7C342B-12JC 7C342B-15JC 7C342B-20JC 7C342-35RC 7C342-25RC 7C342-30RC 7C342-35RMB 7C342-35HC 7C342-25HC 7C342-30HC 7C342-35HI 7C342-30HI 7C342-35HMB 7C342-35JC 7C342-25JC 7C342-30JC
Cross Reference (continued)
ALTERA 5128LI 5128LI-2 5130GC 5130GC-1 5130GC-2 5130GM 5130JC 5130JC-1 5130JC-2 5130JM 5130LC 5130LC-1 5130LC-2 5130LI 5130LI-2 5130QC 5130QC-1 5130QC-2 5130QI 5192AGC-15 5192AGC-20 5192AJC-15 5192AJC-20 5192ALC-1 5192ALC-2 5192GC 5192GC-1 5192GC-2 5192JM 5192JC 5192JC-1 5192JC-2 5192GM 5192JI 5192LC 5192LC-1 5192LC-2 CYPRESS 7C342-35JI 7C342-30HI 7C346-35RC 7C346-25RC 7C346-30RC 7C346-35RM 7C346-35HC 7C346-25HC 7C346-30HC 7C346-35HM 7C346-35JC 7C346-25JC 7C346-30JC 7C346-35JI 7C346-30JI 7C346-35NC 7C346-25NC 7C346-30NC 7C346-35NI 7C341B-15RC 7C341B-20RC 7C341B-15HC 7C341B-20HC 7C341B-15JC 7C341B-20JC 7C341-35RC 7C341-25RC 7C341-30RC 7C341-35HM 7C341-35HC 7C341-25HC 7C341-30HC 7C341-35RM 7C341-35HI 7C341-35JC 7C341-25JC 7C341-30JC
Document #: 38-00087-D
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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