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CMOS SyncBiFIFOTM 256 x 18 x 2 512 x 18 x 2
FEATURES:
* * * * * * * * * * *
IDT72605 IDT72615
Two independent FIFO memories for fully bidirectional data transfers 256 x 18 x 2 organization (IDT72605) 512 x 18 x 2 organization (IDT72615) Synchronous interface for fast (20ns) read and write cycle times Each data port has an independent clock and read/write control Output enable is provided on each port as a three-state control of the data bus Built-in bypass path for direct data transfer between two ports Two fixed flags, Empty and Full, for both the A-to-B and the Bto-A FIFO Programmable flag offset can be set to any depth in the FIFO The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin Quad Flatpack) and 68-pin PLCC Industrial temperature range (-40C to +85C)
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power bidirectional First-In, First-Out (FIFO) memories, with synchronous interface for fast
read and write cycle times. The SyncBiFIFOTM is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous. Each Port has its own independent clock. Data transfers to the I/O registers are gated by the enable signals. The transfer direction for each port is controlled independently by a read/write signal. Individual output enable signals control whether the SyncBiFIFO is driving the data lines of a port or whether those data lines are in a high-impedance state. Bypass control allows data to be directly transferred from input to output register in either direction. The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full, and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full and Almost-Empty flags can be programmed to any location. The SyncBiFIFO is fabricated using IDT's high-speed, submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
ENA R/WA OEA
HIGH Z CONTROL CLKA INPUT REGISTER OUTPUT REGISTER MUX MEMORY ARRAY 512 x 18 256 x 18 MUX MEMORY ARRAY 512 x 18 256 x 18 RESET LOGIC RS
CSA A2 A1 A0 EFAB PAEAB PAFAB FFAB
P INTERFACE FLAG LOGIC
FLAG LOGIC
EFBA PAEBA PAFBA FFBA
3 7
POWER SUPPLY INPUT REGISTER
VCC GND
CLKB OEB R/WB ENB HIGH Z CONTROL
OUTPUT REGISTER
BYPB
DB0-DB17
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
APRIL 2003
DSC-2704/7
IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
DA15 GND DA14 DA13 DA12 DA11 DA10 VCC GND DA9 DA8 DA7 DA6 DA5 GND DA4 DA3
DA16 CA17 CLKA R/WA ENA CSA A0 A1 A2 VCC EFAB FFAB PAEAB PAFAB OEA DB17 DB16
9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 1 60 10 59 11 58 12 57 13 56 14 55 15 54 16 53 17 52 18 51 19 50 20 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DB15 GND DB14 DB13 DB12 DB11 DB10 VCC GND DB9 DB8 DB7 DB6 DB5 GND DB4 DB3
DA2 DA1 DA0 EFBA FFBA PAEBA PAFBA GND BYPB OEB ENB R/WB CLKB RS DB0 DB1 DB2
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PLCC (J68-1, order code: J) TOP VIEW
PIN 1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 GND VCC DA10 DA11 DA12 DA13 DA14 DA15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DB3 DB4 GND DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 GND DB15 DB16
DA16 DA17 CLKA R/WA ENA CSA A0 A1 A2 VCC EFAB FFAB PAEAB PAFAB OEA DB17
DA1 DA0 EFBA FFBA PAEBA PAFBA GND BYBB OEB ENB R/WB CLKB RS DB0 DB1 DB2
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TQFP (PN64-1, order code: PF) TOP VIEW 2
IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol DA0-DA17 CSA R/WA Name Data A Chip Select A Read/Write A I/O I/O I I Description Data inputs & outputs for the 18-bit Port A bus. Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH. This pin controls the read or write direction of Port A. If R/WA is LOW, Data A input data is written into Port A. If R/WA is HIGH, Data A output data is read from Port A. In bypass mode, when R/WA is LOW, message is written into AB output register. If R/WA is HIGH, message is read from BA output register. CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of CLKA. When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data transfers occur. When R/WA is HIGH, Port A is an output bus and OEA controls the high-impedance state of DA0-DA17. If OEA is HIGH, Port A is in a high-impedance state. If OEA is LOW while CSA is LOW and R/WA is HIGH, Port A is in an active (low-impedance) state. When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources. Data inputs & outputs for the 18-bit Port B bus. This pin controls the read or write direction of Port B. If R/WB is LOW, Data B input data is written into Port B. If R/WB is HIGH, Data B output data is read from Port B. In bypass mode, when R/WB is LOW, message is written into BA output register. If R/WB is HIGH, message is read from AB output register. Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLKB. When ENB is LOW, data can be read or written to Port B. When ENB is HIGH, no data transfers occur. When R/WB is HIGH, Port B is an output bus and OEB controls the high-impedance state of DB0-DB17. If OEB is HIGH, Port B is in a high-impedance state. If OEB is LOW while R/WB is HIGH, Port B is in an active (low-impedance) state. When EFAB is LOW, the AB FIFO is empty and further data reads from Port B are inhibited. When EFAB is HIGH, the FIFO is not empty. EFAB is synchronized to CLKB. In the bypass mode, EFAB HIGH indicates that data DA0-DA17 is available for passing through. After the data DB0-DB17 has been read, EFAB goes LOW. When PAEAB is LOW, the AB FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset programmed into PAEAB Register. When PAEAB is HIGH, the AB FIFO contains more than offset in PAEAB Register. The default offset value for PAEAB Register is 8. PAEAB is synchronized to CLKB. When PAFAB is LOW, the AB FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset programmed into PAFAB Register. When PAFAB is HIGH, the AB FIFO contains less than or equal to the depth minus the offset in PAFAB Register. The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA. When FFAB is LOW, the AB FIFO is full and further data writes into Port A are inhibited. When FFAB is HIGH, the FIFO is not full. FFAB is synchronized to CLKA. In bypass mode, FFAB tells Port A that a message is waiting in Port B's output register. If FFAB is LOW, a bypass message is in the register. If FFAB is HIGH, Port B has read the message and another message can be written into Port A. When EFBA is LOW, the BA FIFO is empty and further data reads from Port A are inhibited. When EFBA is HIGH, the FIFO is not empty. EFBA is synchronized to CLKA. In the bypass mode, EFBA HIGH indicates that data DB0-DB17 is available for passing through. After the data DA0-DA17 has been read, EFBA goes LOW on the following cycle. When PAEBA is LOW, the BA FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset programmed into PAEBA Register. When PAEBA is HIGH, the BA FIFO contains more than offset in PAEBA Register. The default offset value for PAEBA Register is 8. PAEBA is synchronized to CLKA. When PAFBA is LOW, the BA FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset programmed into PAFBA Register. When PAFBA is HIGH, the BA FIFO contains less than or equal to the depth minus the offset in PAFBA Register. The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB. When FFBA is LOW, the BA FIFO is full and further data writes into Port B are inhibited. When FFBA is HIGH, the FIFO is not full. FFBA is synchronized to CLKB. In bypass mode, FFBA tells Port B that a message is waiting in Port A's output register. If FFBA is LOW, a bypass message is in the register. If FFBA is HIGH, Port A has read the message and another message can be written into Port B. This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYPB is LOW, Port A has placed the FIFO into bypass mode. If BYPB is HIGH, the synchronous BiFIFO passes data into memory. BYPB is synchronized to CLKB. A LOW on this pin will perform a reset of all synchronous BiFIFO functions. There are three +5V power pins for the PLCC and two for the TQFP. There are seven ground pins for the PLCC and four for the TQFP.
CLKA ENA OEA
Clock A Enable A Output Enable A
I I I I I/O I
A0, A1, A2 Addresses DB0-DB17 Data B Read/Write B R/WB
CLKB ENB OEB EFAB
Clock B Enable B Output Enable B AB Empty Flag AB Programmable Almost-Empty Flag AB Programmable Almost-Full Flag AB Full Flag
I I I O
PAEAB
O
PAFAB
O
FFAB
O
EFBA
BA Empty Flag BA Programmable Almost-Empty Flag BA Programmable Almost-Full Flag BA Full Flag
O
PAEBA
O
PAFBA
O
FFBA
O
BYPB RS VCC GND
Port B Bypass Flag Reset Power Ground
O I
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG IOUT Rating Terminal Voltage with Respect to Ground Storage Temperature DC Output Current Industrial -0.5 to +7.0 -55 to +125 -50 to +50 Unit V C mA
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL VCC GND VIH VIL TA
(1)
PARAMETER Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Operating Temperature
MIN. TYP. MAX. UNIT 4.5 0 2.0 -- -40 5.0 0 -- -- -- 5.5 0 -- 0.8 85 V V V V C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5V 10%, TA = -40C to +85C)
IDT72615L IDT72605L Industrial tCLK = 20, 25, 35, 50ns Symbol ILI
(1) (2)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOUT = -2mA Output Logic "0" Voltage IOUT = 8mA Active Power Supply Current
Min. -1 -10 2.4 -- --
Typ. -- -- -- -- --
Max. 1 10 -- 0.4 230
Unit A A V V mA
ILO
VOH VOL ICC
(3)
NOTES: 1. Measurements with 0.4V VIN VCC. 2. OEA, OEB VIH; 0.4 VOUT VCC. 3. Tested with outputs open (IOUT = 0). Testing frequency f=20MHz.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN(2) COUT(1,2) Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 10 Unit pF pF
NOTES: 1. With output deselected. 2. Characterized values, not currently tested.
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
AC TEST CONDITIONS
In Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 2
+5V 1.1K D.U.T. 680 30pF*
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or equivalent circuit Figure 2. Output Load
* Includes jig and scope capacitances.
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5V 10%, TA = -40C to +85C)
IDT72615L20 IDT72605L20 Min. Max. -- 50 20 8 8 20 12 12 -- 3 6 1 6 1
(2)
Symbol Parameter Clock frequency fCLK tCLK tCLKH tCLKL tRS tRSS tRSR tRSF tA tCS tCH tDS tDH tOE tOLZ tOHZ tFF tEF tPAE tPAF tSKEW1 tSKEW2 Clock cycle time Clock HIGH time Clock LOW time Reset pulse width Reset setup time Reset recovery time Reset to flags in initial state Data access time Control signal setup time(1) Control signal hold time(1) Data setup time Data hold time Output Enable LOW to output data valid Output Enable LOW to data bus at Low-Z(2) Output Enable HIGH to data bus at High-Z Clock to Full Flag time Clock to Empty Flag time Clock to Programmable Almost-Empty Flag time Clock to Programmable Almost-Full Flag time Skew between CLKA & CLKB for Empty/Full Flags(2) Skew between CLKA & CLKB for Programmable Flags(2)
(2)
Industrial IDT72615L25 IDT72615L35 IDT72605L25 IDT72605L35 Min. Max. Min. Max. -- 40 -- 28 25 10 10 25 15 15 -- 3 6 1 6 1 3 0 3 -- -- -- -- 12 19 -- -- -- -- -- -- 28 15 -- -- -- -- 13 -- 13 15 15 15 15 -- -- 35 14 14 35 21 21 -- 3 8 1 8 1 3 0 3 -- -- -- -- 17 25 -- -- -- -- -- -- 35 21 -- -- -- -- 20 -- 20 21 21 21 21 -- --
IDT72615L50 IDT72605L50 Min. Max. -- 20 50 20 20 50 30 30 -- 3 10 1 10 1 3 0 3 -- -- -- -- 20 34 -- -- -- -- -- -- 50 25 -- -- -- -- 28 -- 28 30 30 30 30 -- --
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing Figures -- 4,5,6,7 4,5,6,7,12,13,14,15 4,5,6,7,12,13,14,15 3 3 3 3 5,7,8,9,10,11 4,5,6,7,8,9,10,11, 12, 13,14,15 4,5,6,7,10,11,12, 13, 14,15 4,6,8,9,10,11 4,6 5,7,8,9,10,11 5,7,8,9,10,11 5,7,10,11 4,6,10,11 5,7,8,9,10,11 12,14 13,15 4,5,6,7,8,9,10,11 4, 7,12,13,14,15
-- -- -- -- -- -- 27 10 -- -- -- -- 10 -- 10 10 10 12 12 -- --
3 0 3 -- -- -- -- 10 17
NOTES: 1. Control signals refer to CSA, R/WA, ENA, A2, A1, A0, R/WB, ENB. 2. Minimum values are guaranteed by design.
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral applications. Data can be stored or retrieved from two sources simultaneously. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. Each port has its own independent clock. Data transfers to the I/O registers are gated by the enable signals. The transfer direction for each port is controlled independently by a read/write signal. Individual output enable signals control whether the SyncBiFIFO is driving the data lines of a port or whether those data lines are in a highimpedance state. The processor connected to Port A of the BiFIFO can send or receive messages directly to the Port B device using the 18-bit bypass path. The SyncBiFIFO can be used in multiples of 18-bits. In a 36- to 36-bit configuration, two SyncBiFIFOs operate in parallel. Both devices are programmed simultaneously, 18 data bits to each device. This configuration can be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, etc.) by adding more SyncBiFIFOs to the configuration. Figure 1 shows multiple SyncBiFIFOs configured for multiprocessor communication. The microprocessor or microcontroller connected to Port A controls all operations of the SyncBiFIFO. Thus, all Port A interface pins are inputs driven by the controlling processor. Port B interfaces with a second processor. The Port B control pins are inputs driven by the second processor. RESET Reset is accomplished whenever the Reset (RS) input is taken to a LOW state with CSA, ENA and ENB HIGH. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The AB and BA FIFO Empty Flags (EFAB, EFBA) and Programmable Almost-Empty flags (PAEAB, PAEBA) will be set to LOW after tRSF. The AB and BA FIFO Full Flags (FFAB, FFBA) and Programmable Almost- Full flags (PAFAB, PAFBA) will be set to HIGH after tRSF. After the reset, the offsets of the Almost-Empty flags and Almost- Full flags for the AB and BA FIFO offset default to 8.
PORT A INTERFACE The SyncBiFIFO is straightforward to use in micro-processor-based systems because each port has a standard microprocessor control set. Port A interfaces with microprocessor through the three address pins (A2-A0) and a Chip Select CSA pins. When CSA is asserted, A2,A1,A0 and R/WA are used to select one of six internal resources (Table 1). With A2=0 and A1=0, A0 determines whether data can be read out of output register or be written into the FIFO (A0=0), or the data can pass through the FIFO through the bypass path (A0=1). With A2=1, four programmable flags (two AB FIFO programmable flags and two BA FIFO programmable flags) can be selected: the AB FIFO Almost-Empty flag Offset (A1=0, A0=0), AB FIFO Almost-Full flag Offset (A1=0, A0=1), BA FIFO Almost-Empty flag Offset (A1=1, A0=0), BA FIFO Almost-Full flag Offset (A1=1, A0=1). Port A is disabled when CSA is deasserted and data A is in high-impedance state. BYPASS PATH The bypass paths provide direct communication between Port A and Port B. There are two full 18-bit bypass paths, one in each direction. During a bypass operation, data is passed directly between the input and output registers, and the FIFO memory is undisturbed. Port A initiates and terminates all bypass operations. The bypass flag, BYPB, is asserted to inform Port B that a bypass operation is beginning. The bypass flag state is controlled by the Port A controls, although the BYPB signal is synchronized to CLKB. So, BYPB is asserted on the next rising edge of CLKB when A2A1A0=001and CSA is LOW. When Port A returns to normal FIFO mode (A2A1A0=000 or CSA is HIGH), BYPB is deasserted on the next CLKB rising edge. Once the SyncBiFIFO is in bypass mode, all data transfers are controlled by the standard Port A (R/WA, CLKA, ENA, OEA) and Port B (R/WB, CLKB, ENB, OEB) interface pins. Each bypass path can be considered as a one word deep FIFO. Data is held in each input register until it is read. Since the controls
IDT SYNCBIFIFO CLK MICROPROCESSOR A DATA ADDR, I/0 RAM A CONTROL LOGIC IDT SYNCBIFIFO DATA A CLKA CONTROL A SYSTEM CLOCK A
NOTES: 1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration. 2. Control A consists of R/WA, ENA, OEA, CSA, A2, A1, A0. Control B consists of R/WB, ENB, OEB.
DATA B DATA A CLKA CLKB CONTROL A CONTROL B
CLK MICROPROCESSOR B DATA CONTROL LOGIC ADDR, I/0 RAM B SYSTEM CLOCK B
DATA B CLKB CONTROL B
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Figure 1. 36- to 36-bit Processor Interface Configuration
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
TABLE 1 PORT A OPERATION CONTROL SIGNALS
CSA 0 R/WA 0 ENA 0 OEA 0 Data A I/O I Port A Operation Data A is written on CLKA . This write cycle immediately following low-impedance cycle is prohibited. Note that even though OEA = 0, a LOW logic level on R/WA, once qualified by a rising edge on CLKA, will put Data A into a high-impedance state. Data A is written on CLKA Data A is ignored Data is read(1) from RAM array to output register on CLKA , Data A is low-impedance Data is read(1) from RAM array to output register on CLKA , Data A is high-impedance Output register does not change(2), Data A is low-impedance Output register does not change(2), Data A is high-impedance Data A is ignored(3) Data A is high-impedance(3)
0 0 0 0 0 0 1 1
0 0 1 1 1 1 0 1
0 1 0 0 1 1 X X
1 X 0 1 0 1 X X
I I O O O O I O
NOTES: 1. When A2A1A0 = 000, the next BA FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and bypass data from the Port B input register is read from the Port A output register. If A2A1A00 = 1XX, a flag offset register is selected and its offset is read out through Port A output register. 2. Regardless of the condition of A2A1A0, the data in the Port A output register does not change and the BA read pointer does not advance. 3. If CSA# is HIGH, then BYPB is HIGH. No bypass occur under this condition.
of each port operate independently, Port A can be reading bypass data at the same time Port B is reading bypass data. When R/WA and ENA is LOW, data on pins DA0-DA17 is written into Port A input register. Following the rising edge of CLKA for this write, the AB Full Flag (FFAB) goes LOW. Subsequent writes into Port A are blocked by internal logic until FFAB goes HIGH again. On the next CLKB rising edge, the AB Empty Flag (EFAB) goes HIGH indicating to Port B that data is available. Once R/WB is HIGH and ENB is LOW, data is read into the Port B output register. OEB still controls whether Port B is in a high-impedance state. When OEB is LOW, the output register data appears at DB0-DB17. EFAB goes LOW following the CLKB rising edge for this read. FFAB goes HIGH on the next CLKA rising edge, letting Port A know that another word can be written through the bypass path. Bypass data transfers from Port B to Port A work in a similar manner with EFBA and FFBA indicating the Port A output register state. When the Port A address changes from bypass mode (A2A1A0=001) to FIFO mode (A2A1A0=000) on the rising edge of CLKA, the data held in the Port B output register may be overwritten. Unless Port A monitors the BYPB pin and waits for Port B to clock out the last bypass word, data from the AB FIFO will overwrite data in the Port B output register. BYPB will go HIGH on the rising edge of CLKB signifying that Port B has finished its last bypass operation. Port B must read any bypass data in the output register on this last CLKB clock or it is lost and the SyncBiFIFO returns to FIFO operations. It is especially important to monitor BYPB when CLKB is much slower than CLKA to avoid this condition. BYPB will also go HIGH after CSA is brought HIGH; in this manner the Port B bypass data may also be lost. Since the Port A processor controls CSA and the bypass mode, this scenario can be handled for BA bypass data. The Port A processor must be set up to read the last bypass word before leaving bypass mode. PORT A CONTROL SIGNALS The Port A control signals pins dictate the various operations shown in Table 2. Port A is accessed when CSA is LOW, and is inactive if CSA is HIGH. R/ WA and ENA lines determine when Data A can be written or read. If R/WA and ENA are LOW, data is written into input register on the LOW-to-HIGH transition of CLKA. If R/WA is HIGH and OEA is LOW, data comes out of bus and is read from output register into three-state buffer. Refer to pin descriptions for more information.
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TABLE 2 ACCESSING PORT A RESOURCES USING CSA, A2, A1, AND A0
CSA 0 0 0 0 0 0 1 A2 0 0 1 1 1 1 X A1 0 0 0 0 1 1 X A0 0 1 0 1 0 1 X Read Write BA FIFO AB FIFO 18-bit Bypass Path AB FIFO Almost-Empty Flag Offset AB FIFO Almost-Full Flag Offset BA FIFO Almost-Empty Flag Offset BA FIFO Almost-Full Flag Offset Port A Disabled
PROGRAMMABLE FLAGS The IDT SyncBiFIFO has eight flags: four flags for AB FIFO (EFAB, PAEAB, PAFAB, FFAB), and four flags for BA FIFO (EFBA, PAEBA, PAFBA, FFBA). The Empty and Full flags are fixed, while the Almost-Empty and AlmostFull offsets can be set to any depth through the Flag Offset Registers (see Table 3). The flags are asserted at the depths shown in the Flag Truth Table (Table 4). After reset, the programmable flag offsets are set to 8. This means the AlmostEmpty flags are asserted at Empty +8 words deep, and the Almost-Full flags are asserted at Full -8 words deep. The PAEAB is synchronized to CLKB, while PAEAB is synchronized to CLKA; and PAEBA is synchronized to CLKA, while PAEBA is synchronized to CLKB. If the minimum time (tSKEW2) between a rising CLKB and a rising CLKA is met, the flag will change state on the current clock; otherwise, the flag may not change state until the next clock rising edge. For the specific flag timings, refer to Figures 12-15. PORT B CONTROL SIGNALS The Port B control signal pins dictate the various operations shown in Table 5. Port B is independent of CSA. R/WB and ENB lines determine when Data
IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
can be written or read in Port B. If R/WB and ENB are LOW, data is written into input register, and on LOW-to-HIGH transition of CLKB data is written into input register and the FIFO memory. If R/WB is HIGH and OEB is LOW, data comes out of bus and is read from output register into three-state buffer. In bypass mode,
if R/WB is LOW, bypass messages are transferred into BA output register. If R/WA is HIGH, bypass messages are transferred into AB output register. Refer to pin descriptions for more information.
TABLE 3 FLAG OFFSET REGISTER FORMAT
17 PAEAB Register X 17 X 17 X 17 X 16 X 16 X 16 X 16 X 15 X 15 X 15 X 15 X 14 X 14 X 14 X 14 X 13 X 13 X 13 X 13 X 12 X 12 X 12 X 12 X 11 X 11 X 11 X 11 X 10 X 10 X 10 X 10 X 9 X 9 X 9 X 9 X 8 7 8 7 6 5 4 3 2 1 0 AB FIFO Almost-Empty Flag Offset 6 5 4 3 2 AB FIFO Almost-Full Flag Offset 1 0
PAFAB Register
8
7
PAEBA Register
6 5 4 3 2 1 BA FIFO Almost-Empty Flag Offset 6 5 4 3 2 BA FIFO Almost-Full Flag Offset 1
0
8
7
0
PAFBA Register
NOTE: 1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.
TABLE 4 INTERNAL FLAG TRUTH TABLE
Number of Words in FIFO From To 0 0 1 n n+1 D-(m+1) D-m D-1 D D EF LOW HIGH HIGH HIGH HIGH PAE LOW LOW HIGH HIGH HIGH PAF HIGH HIGH HIGH LOW LOW FF HIGH HIGH HIGH HIGH LOW
NOTE: 1. n = Programmable Empty Offset (PAEAB Register or PAEBA Register) m = Programmable Full Offset (PAFAB Register or PAFBA Register) D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
TABLE 5 PORT B OPERATION CONTROL SIGNALS
R/WB 0 ENB 0 OEB 0 Data B I/O I Port B Operation Data B is written on CLKB . This write cycle immediately following output low-impedance cycle is prohibited. Note that even though OEB = 0, a LOW logic level on R/WB, once qualified by a rising edge on CLKB, will put Data B into a highimpedance state. Data B is written on CLKB . Data B is ignored Data is read(1) from RAM array to output register on CLKB Data B is low-impedance Data is read(1) from RAM array to output register on CLKB , Data B is high- impedance Output register does not change(2), Data B is low-impedance Output register does not change(2), Data B is high-impedance
0 0 1 1 1 1
0 1 0 0 1 1
1 X 0 1 0 1
I I O O O O
NOTES: 1. When A2A1A0 = 000 or 1XX, the next AB FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and bypass data is read from the Port B output register. 2. Regardless of the condition of A2A1A0, the data in the Port B output register does not change and the AB read pointer does not advance.
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
tRS RS EFAB, PAEAB, EFBA, PAEBA EFAB, PAEAB, EFBA, PAEBA CSA, ENA , ENB tRSF
tRSF
tRSS
tRSR
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Figure 3. Reset Timing
tCLK tCLKH CLKA tCLKL
A0, A1, A2
R/WA
CSA tCS ENA tFF FFAB tDS DA0-DA17 tSKEW1 CLKB READ DATA IN VALID NO READ OPERATION
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tCH NO OPERATION tFF tDH
Figure 4. Port A (AB) Write Timing
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
tCLK tCLKH CLKA tCLKL
A0, A1, A2
R/WA
CSA tCS ENA tEF EFBA tA DA0-DA17 tOLZ tOE OEA tSKEW1 CLKB NO WRITE WRITE
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tCH NO OPERATION tEF
VALID DATA tOHZ
Figure 5. Port A (BA) Read Timing
tCLK tCLKH CLKB tCLKL
R/WB tCS ENB tFF FFBA tDS DB0-DB17 tSKEW1 CLKA READ DATA IN VALID NO READ OPERATION
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tCH NO OPERATION tFF tDH
Figure 6. Port B (BA) Write Timing
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
tCLK tCLKH CLKB tCLKL
INDUSTRIAL TEMPERATURE RANGE
R/WB tCS ENB tEF EFBA tA DB0-DB17 tOLZ tOE OEB tSKEW1 NO WRITE OPERATION WRITE
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tCH NO OPERATION tEF
VALID DATA tOHZ
CLKA
Figure 7. Port B (AB) Read Timing
CLKA
A0, A1, A2
R/WA tCS CSA, ENA tDS DA0-DA17 D0 (First Valid Write) tSKEW1 CLKB
(1)
D1
D2
D3
tFRL
R/WB tCS ENB tEF EFAB tA DB0-DB17 tOLZ tOE OEB
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tA D0 D1
NOTE: 1. When tSKEW1 minimum specification, tFRL(Max.) = tCLK + tSKEW1 tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timing applies only at the Empty Boundary (EF = LOW).
Figure 8. AB First Data Word Latency after Reset for Simultaneous Read and Write
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
CLKB
R/WB tCS ENB tDS DB0-DB17 tSKEW1 CLKA D0 (First valid write) tFRL
(1)
D1
D2
D3
A0, A1, A2
R/WA tCS CSA, ENA tEF EFBA tA DA0-DA17 tOLZ tOE OEA
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tA D0 D1
NOTE: 1. When tSKEW1 minimum specification, tFRL(Max.) = tCLK + tSKEW1 tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 9. BA First Data Word Latency after Reset for Simultaneous Read and Write
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
CLKA tCS A0, A1, A2 A2, A1, A0 = 001
R/WA tCH CSA tCS ENA tFF FFAB tDS DA0-DA17 tSKEW1 CLKB DATA INPUT tSKEW1 tSKEW1 BYPASS FLAG tFF tFF FIFO FLAG tCH
R/WB tCS ENB tEF EFAB FIFO FLAG tEF BYPASS FLAG tEF FIFO FLAG
BYPB tA DB0-DB17 tOLZ tOE OEB tOHZ
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DATA OUTPUT
NOTES: 1. When CSA is brought HIGH, AB Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition. 2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for the next bypass operation. 3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO mode.
Figure 10. AB Bypass Timing
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
CLKB R/WB tCS ENB tFF FFBA BYPB tDS DB0-DB17 tSKEW1 CLKA tCS A0, A1, A2 CSA R/WA tCS ENA tEF EFBA FIFO FLAG BYPASS FLAG tA DA0-DA17 tOLZ tOE OEA tOHZ
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tCH tFF BYPASS FLAG FIFO FLAG tFF tFF
DATA INPUT tSKEW1
tSKEW1 tCS
tSKEW1
A2, A1, A0 = 001 tCS
tEF
tEF
tEF FIFO FLAG DATA OUTPUT
NOTES: 1. When CSA is brought HIGH, AB Bypass mode will switch to FIFO mode on the following CLKA going LOW-to-HIGH. 2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. 3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO mode.
Figure 11. BA Bypass Timing
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
tCLKH CLKA tCS ENA (R/WA = 0) WRITE PAEAB n words in FIFO tSKEW2 (1) n+1 words in FIFO tCH tCLKL
INDUSTRIAL TEMPERATURE RANGE
tPAE
(2)
tPAE
CLKB tCS ENA (R/WB = 1) READ tCH
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NOTES: 1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the rising edge of CLKA and the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge. 2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.
Figure 12. AB Programmable Almost-Empty Flag Timing
tCLKH CLKA
tCLKL tCS tCH
(2)
ENA (R/WA = 0) WRITE PAFAB Full - (m+1) words in FIFO tPAF CLKB tCS ENB (R/WB = 1) READ
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge. 2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Full - m words in FIFO tPAF tCH
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Figure 13. AB Programmable Almost-Full Flag Timing
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IDT72605/72615 CMOS SYNCBiFIFOTM 256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
tCLKH CLKB
tCLKL tCH
tCS ENB (R/WA = 0) WRITE PAEBA n words in FIFO tSKEW2(1)
n+1 words in FIFO tPAE
(2)
tPAE tCS tCH
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CLKA ENA (R/WA = 1) READ
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge. 2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
Figure 14. BA Programmable Almost-Empty Flag Timing
tCLKH CLKB
tCLKL
(2)
tCS ENB (R/WA = 0) WRITE PAFBA
tCH
Full - (m+1) words in FIFO tPAF
Full - m words in FIFO tSKEW2(1) tPAF tCH
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CLKA ENA (R/WA = 1) tCS
READ
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge. 2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 15. BA Programmable Almost-Full Flag Timing
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ORDERING INFORMATION
IDT X XXXXX Device Type Power XX Speed X Package X Process/ Temperature Range Blank J PF 20 25 35 50 L 72605 72615 Industrial (-40C to +85C) Plastic Leaded Chip Carrier (PLCC, J68-1) Thin Quad Flat Pack (TQFP, PN64-1) Clock Cycle Time (tCLK) in Nanoseconds Low Power 256 x 18 Parallel SyncBiFIFO 512 x 18 Parallel SyncBiFIFO
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DATASHEET DOCUMENT HISTORY
11/02/2000 04/08/2003 pgs. 1, 2, 3, 4, 16 pg. 17. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for Tech Support: 408-330-1753 email: FIFOhelp@idt.com

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