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| HM71V832 Series 32768-word x 8-bit Nonvolatile Ferroelectric RAM Preliminary Rev. 0.0 Nov. 20, 1995 Description The HM71V832 is a ferroelectric RAM, or FARM(R) memory, organized as 32k-word x 8-bit. FRAM(R) memory products from Hitachi combine the read/write characteristics of semiconductor RAM with nonvolatile storage. This product is manufactured in a 0.8 micron silicon gate CMOS technology with the addition of integrated thin film ferroelectric storage cells developed. The ferroelectric cells are polarized on each read or write cycle, therefore no special store or recall sequence is required. The memory is always static and nonvolatile. Hitachi's FRAM(R) products operate from a single 3 V power supply and are CMOS compatible on all inputs and outputs. The HM71V832 utilizes the JEDEC standard bytewide SRAM pinout. Features * Single 3 V power supply (2.7 V to 3.6 V) * Fully synchronous operation 150 ns Read access 235 ns Read/write cycle time 1012 Read/write cycle endurance * Low power consumption Active: 20 mA (typ) Standby: 15 A (typ) * JEDEC standard 21-C write protection (Entire memory) and Selectable 4K byte write protection * 10 year data retention * CMOS compatible I/O pins * 28 pin SOP and TSOP packages * 0 to +70C ambient operating temperature range HM71V832 Series Ordering Information Access Type No. HM71V832FP-15 HM71V832T-15 time 150 ns 150 ns Package 450 mil 28-pin plastic SOP (FP-28DA) 8 mm x 13.4 mm 28-pin TSOP (TFP-28DB) 2 HM71V832 Series Pin Arrangement HM71V832FP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 1/05 I/O4 I/O3 OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top View) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 HM71V832T Series Pin Description Pin name A0 to A14 I/O0 to I/O7 CE WE OE VCC VSS Function Address inputs Data input/output Chip enable Write enable Output enable Power supply Ground 3 HM71V832 Series Block Diagram CE A0 to A7, A13, A14 Address Latch Row Decoder 1,024 x 256 FRAM Memory Array Column Decoder A8 to A12 Address Latch I/O0 to I/O7 I/O Latch WE OE Control Logic and Block Project 4 HM71V832 Series Device Operation * Read operation: When CE is low and WE is high a read operation is performed by the FRAM(R) memory. On the falling edge of CE, all address bits (A0 to A14) are latched into the part and the cycle is started. Data will appear on the output pins a maximum access time (tCE ) after the beginning of the cycle. The designer should ensure that there are no address transitions from tAS (setup time) before the falling edge of CE to tAH (hold time) after it. After tAH, the address pins are ignored for the remainder of the cycle. It is equally important that CE be generated such that unwanted glitches or pulses, of any duration, be prevented. After the read has completed, CE should be brought high for the precharge interval (tPC). During this period data is restored in the internal memory cells and the chip is prepared for the next read or write cycle. The HM71V832 will not operate in systems in which CE does not toggle with every access. The OE pin may be used to avoid bus conflicts on the system bus. Only when both CE and OE are low will the FRAM(R) memory drive its outputs. Under all other circumstances, the output drivers are held in a high impedance (High-Z) condition. Note that the internal read operation is performed regardless of the state of the OE pin. * Write operation: When CE falls while WE is low, or WE falls while CE is low, a write operation will be performed by the FRAM(R) memory. On the falling edge of CE, as in the read cycle, the address will be latched into the part with the same setup and hold requirements. As in the read cycle, CE must be held high for a precharge interval (t PC) between each access. Data needs to be set up tDS minimum on the rising edge of WE or CE, whichever occurs first. Write operations take place regardless of the state of OE, however, it may need to be driven high by the system at the beginning of the cycle in order to avoid bus conflicts. Data is immediately nonvolatile and power may be removed from the part upon completion of the precharge interval following the write. For better noise immunity, a 10 ns (typ) glitch protection is built into the WE signal. * Write protection: The HM71V832 FRAM(R) memory uses a superset of JEDEC Standard 21-C for software data protection. The standard allows for the entire memory array to be protected or unprotected via software control. Hitachi enhanced the standard to allow each of the 4K word blocks on the HM71V832 to be individually protected or unprotected. The protection data map is stored in the nonvolatile block protection register. This data can be recalled at any time via the enhanced standard to restore the previously stored block protection map. The configuration data may also be modified via the enhanced standard. 5 HM71V832 Series * Standard JEDEC protection: Upon power up, the entire memory array is write protected as per the JEDEC standard. If desired, the entire memory array can be unprotected by executing the JEDEC disable sequence shown in Table 1. The entire memory array can be write protected by executing the JEDEC enable sequence shown in Table 1. Any time these two sequences are executed, the respective operation will be performed i.e. one should insure that these sequence of addresses is only executed if enabling or disabling write protection. Table 1 Cycle 1 2 3 4 5 6 7 JEDEC Write Protect Sequence Disable Sequence 1823 Hex 1820 Hex 1822 Hex 0418 Hex 041BHex 0419 Hex 041A Hex Enable Sequence 1823 Hex 1820 Hex 1822 Hex 0418 Hex 041B Hex 0419 Hex 040A Hex Mode Read Read Read Read Read Read Read * Enhanced block protection: Hitachi added capability to the HM71V832 to allow any of the eight 4K blocks to be individually protected or unprotected. This feature is enabled by adding one additional unique address to the standard JEDEC disable sequence as shown in Table 1. To write a specific block protect map to the HM71V832, the access to this added address should be a "WRITE" access as shown in Table 2. Each bit of the data word has a one to one correlation with a specific 4K block as shown in Table 4. A data of "1" enables write protection. A data of "0" allows writing to that block. It should be noted that data written on this sequence is written to the block protect register and not to address 040FH. If the previously configured block protection map is to be restored, then the access to 040FH address should be a "READ" cycle as shown in Table 3. The data on the I/O pins after an access time will be the data contained in the block protect register that is being restored, not the data at address 040FH. On the next rising edge of CE after executing the address sequence, in Table 2 or 3 the part will be placed into the write protected mode. The memory blocks that will be write protected will be those either written to the block protect register during that sequence or those restored from the previous contents the block protect register. For example, if the block protect register contained the following data 10011000, addresses 3000H to 4FFFH and 7000H to 7FFFH would be write protected, i.e. Blocks 3, 4 and 7. On a WE controlled write operation where WE rises prior to CE, the data I/O outputs will become active a tWX after WE rises. The data on the outputs mirror the data just written to the addressed location so no bus contention should arise. However, the addition of write protection required that the I/O outputs perform differently if a write to a protected location was attempted. If a write operation is attempted to a protected location, the I/O outputs remain high impedance after WE returns high. This is done to prevent any bus contention that might arise due to the data driven on the I/O lines externally and the data at the accessed memory location being different. The I/O outputs will remain high impedance until the next memory cycle. 6 HM71V832 Series Table 2 Extended Write Protect Sequence Cycle 1 2 3 4 5 6 7 8 Sequence 1823 Hex 1820 Hex 1822 Hex 0418 Hex 041B Hex 0419 Hex 041A Hex 040F Hex I/O Data Data Data Data Data Data Data New block protect data Mode Read Read Read Read Read Read Read Write 7 HM71V832 Series Table 3 Cycle 1 2 3 4 5 6 7 8 Extended Restore Protect Sequence Sequence 1823 Hex 1820 Hex 1822 Hex 0418 Hex 041B Hex 0419 Hex 041A Hex 040F Hex I/O Data Data Data Data Data Data Data Restore block protect data Mode Read Read Read Read Read Read Read Read Table 4 Block Number To I/O Correlation A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 I/O# 0 1 2 3 4 5 6 7 4K Block Number 0 1 2 3 4 5 6 7 Function Truth Table Function (Mode) Standby/Precharge Latch address Output 50 pF* 1.4V CE H 500 WE x x OE x x (*including scope and jig) Read Write L L H L L x Notes: H means logic HIGH. L means logic LOW. x means H or L. 8 HM71V832 Series Absolute Maximum Ratings* Parameter Power supply voltage Voltage on any pin relative to Vss Operating temperature Storage temperature Symbol Vcc VT Topr Tstg Value -0.5 to +5.0 -0.5 to +5.0 0 to +70 -55 to +85 Unit V V C C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9 HM71V832 Series Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC VSS Input voltage VIH VIL Min 2.7 0 0.7VCC -0.3 Typ 3.0 0 - - Max 3.6 0 VCC + 0.3 0.2VCC Unit V V V V D C Characteristics (Ta = 0 to +70C, VC C = 2.7 V to 3.6V, VSS = 0 V, unless otherwise noted.) Parameter Input leakage current Output leakage current Operating power supply current Symbol IILII IILO I ICC Min - - - Typ - - 20 Max 10 10 30 Unit A A mA Test conditions Vin = VSS to VCC Vout = VSS to VCC VCC = Max, CE cycling at minimum cycle time II/O = 0 mA; OE, WE, AX = CMOS input levels VCC = Max, CE = VCC input levels = VCC or GND II/O = 0 mA IOL = 100 A IOL = 2.0 mA IOH = -100 A IOH = -2.0 mA Standby power supply current Output low voltage ISB VOL - - - 15 - - - - 25 0.2 0.4 - - A V v V V Output high voltage VOH VCC -0.2 2.4 Capacitance (Ta = 25C, f = 1.0 MHz, VCC = 3.0 V) Parameter input capacitance input/output capacitance Symbol Cin CI/O Min - - Typ - - Max 6 8 Unit pF pF Test conditions VI/O = 0 V VI/O = 0 V Note 1 1 Note: 1. This parameter is sampled and not 100% tested. 10 HM71V832 Series AC Characteristics (Ta = 0 to +70C, VCC =2.7 V to 3.6 V, VSS = 0 V, unless otherwise noted.) Test Conditions * Input pulse levels: 0 V to 3.0 V * Input rise and fall time: 10 ns * Input and output timing reference levels: 1.5 V Function Truth Table Function (Mode) Standby/Precharge Latch adderss Read Write CE H WE x x OE x x L x L L H L Notes : H means logic HIGH. L means logic LOW. x means H or L. Read Cycle HM71V832-15 Parameter Read cycle time Chip enable active time Precharge time Address setup time Address hold time Chip enable access time Output enable access time Chip enable to output High-Z Output enable to output Hihg-z Symbol tRC tCA tPC tAS tAH tCE tOE tHZ tOHZ JEDEC Symbol tELEL tELEH tEHEL tAVEL tELAX tELQV tOLQV tEHQZ tOHQZ Min 235 150 85 0 15 - - - - Max - 10000 - - - 150 25 25 25 Unit ns ns ns ns ns ns ns ns ns 1 1 Note Note: 1. This parameter is periodically sampled and not 100% tested. 11 HM71V832 Series Read Timing Waveform t RC t CA t PC CE t AS t AH A0 to A14 Valid address OE t OE t OHZ High-Z Valid data VO0 to VO7 t CE t HZ 12 HM71V832 Series Write Cycle HM71V832-15 Parameter Write cycle time Chip enable active time Chip enable to write High Precharge time Address setup time Address hold time Write enable pulse width Data setup time Data hold time Write enable Low to output High-Z Write enable High to output driven Chip enable to output High-Z Write setup Write hold Symbol tWC tCA tCW tPC tAS tAH tWP tDS tDH tWZ tWX tHZ tWS tWH JEDEC Symobl tELEL tELEH tELWH tEHEL tAVEL tELAX tWLWH tDVWH tWHDX tWLQZ tWHQX tEHQZ tCLWL tWHCH Min 235 150 150 85 0 15 50 50 0 - 10 - 0 0 Max - 10000 - - - - - - - 25 - 25 - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 2 2 Notes Notes: 1. This parameter is periodically sampled and not 100% tested. 2. Not a device specification, merely distinguished CE and WE controlled accesses. 13 HM71V832 Series 14 HM71V832 Series Write Timing Waveform (1) (CE Controlled) Write Timing Waveform (1) (CE Controlled) t RC t CA t PC CE tAS Valid address t WS WE t DS t DH t WH t AH A0 to A14 Data in Valid data Note: State of OE does not affect operation to device for this cycle. Write Timing Waveform (2) (WE Controlled) 15 HM71V832 Series Write Timing Waveform (2) (WE Controlled) t RC t CA t PC CE t AS t AH A0 to A14 Valid address t WS t WP t WH WE OE t DH t DS Data in t WZ Valid data t HZ Data out t WX *1 Note: 1. Output remains high impedance after write attempt to a protected memory location 16 HM71V832 Series Power Down/Power Up Conditions Care must be taken during power sequencing to prevent data loss resulting from memory operations during out of spec voltage conditions. This is managed by detecting power failure with sufficient time tPD to disable memory operation prior to V CC dropping below its lower specification, 2.7 V. During power up, the memory operation should be disabled until time t REC after V CC reaches its minimum operating Voltage, 2.7 V. Vcc 2.7V 0.7*V CC 1.9V t PD t REC CE 0V V CE >0.7 Vcc Power Up/Power Down Cycle HM71V832-15 Parameter CE signal stable to power down Power up to operation Symbol tPD tREC Min 85 85 Typ - - Max - - Unit ns ns 17 HM71V832 Series Package Dimensions HM71V832FP Series (FP-28DA) Unit: mm 18.3 18.75 Max 28 15 1 14 8.4 0.895 3.0 Max +0.08 -0.07 11.8 - 0.3 0.17 0 - 10 +0.10 -0.50 1.27-0.10 0.40 0.1 Min 1.0 HM71V832T Series (TFP-28DB) Unit: mm 18 HM71V832 Series 8.0 8.1 Max 21 8 22 7 0.55 0.20 + 0.07 - 0.02 1.0 11.8 M 0 - 10 0.20 Max + 0.08 - 0.07 1.2 Max 0.17 0.5 Min 0.5 - 0.1 0.10 13.4 - 0.3 19 |
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