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| (R) STP40NF03L N - CHANNEL 30V - 0.020 - 40A TO-220 STripFETTM POWER MOSFET TYPE STP40NF03L s s VDSS 30 V R DS(on) < 0.022 ID 40 A TYPICAL RDS(on) = 0.020 LOW THRESHOLD DRIVE DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING s SOLENOID AND RELAY DRIVERS s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC & DC-AC CONVERTERS s 3 1 2 TO-220 INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR VGS ID ID I DM (*) P tot E AS (1) T st g Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) Gate-source Voltage Drain Current (continuous) at T c = 25 o C Drain Current (continuous) at T c = 100 C Drain Current (pulsed) Total Dissipation at T c = 25 o C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature o Value 30 30 20 40 28 160 70 0.46 250 -65 to 175 175 ( 1) starting Tj = 25 oC, ID =20A , VDD = 15V Unit V V V A A A W W/ o C m/J o o C C (*) Pulse width limited by safe operating area October 1999 1/8 STP40NF03L THERMAL DATA R thj-case R thj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 2.1 62.5 300 o o C/W C/W o C ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbol V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Conditions I D = 250 A V GS = 0 Min. 30 1 10 100 Typ. Max. Unit V A A nA Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) V GS = 20 V T c =125 o C ON () Symbol V GS(th) R DS(on) I D(on) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance V GS = 10 V V GS = 4.5 V Test Conditions I D = 250 A I D = 20 A I D = 20 A 40 Min. 1 Typ. 1.7 0.018 0.028 Max. 2.5 0.022 0.035 Unit V A On State Drain Current V DS > I D(on) x R DS(on)max V GS = 10 V DYNAMIC Symbol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions V DS > I D(on) x R DS(on)max V DS = 25 V f = 1 MHz I D =20 A V GS = 0 Min. Typ. 20 830 230 92 Max. Unit S pF pF pF 2/8 STP40NF03L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions V DD = 15 V I D = 20 A R G = 4.7 V GS = 4.5 V (Resistive Load, see fig. 3) V DD = 24 V I D = 40 A V GS = 5 V Min. Typ. 35 205 18 7 8 23 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol t d(of f) tf t d(of f) tf tc Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions V DD = 15 V I D = 20 A R G = 4.7 V GS = 4.5 V (Resistive Load, see fig. 3) Vclamp = 24 V I D = 20 A R G = 4.7 V GS = 4.5 V (Inductive Load, see fig. 5) Min. Typ. 90 240 150 155 340 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 40 A V GS = 0 65 72 2 I SD = 40 A di/dt = 100 A/s V DD = 15 V T j = 150 o C (see test circuit, fig. 5) Test Conditions Min. Typ. Max. 40 160 1.5 Unit A A V ns nC A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STP40NF03L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP40NF03L Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STP40NF03L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP40NF03L TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 F1 D G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/8 STP40NF03L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 8/8 http://www.st.com . |
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