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1M x 64-Bit Dynamic RAM Module
HYM 641010GS-60/-70 HYM 641020GS-60/-70
Preliminary Information
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1 048 576 words by 64-bit organization Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V ( 10 %) supply Low power dissipation max. 9680 mW active (-60 version) max. 8800 mW active (-70 version) CMOS - 451 mW standby TTL - 550 mW standby CAS-before-RAS refresh, RAS-only-refresh 16 decoupling capacitors mounted on substrate
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All inputs, outputs and clock fully TTL compatible 4 Byte interleave enabled, Dual Address inputs (A0/B0) Buffered inputs except RAS and DQ 168 pin, dual read-out, Single in-Line Memory Module Utilizes sixteen 1M x 4 - DRAMs (HYB 514400BJ/BT) and four BiCMOS 8-bit buffers/line drivers 74ABT244 Two version: HYM 641010S with SOJ-components (8.89 mm module thickness HYM 641020GS with TSOPII-components (4.06 mm module thickness) 1024 refresh cycles / 16 ms Gold contact pad double sided module with 25.35 mm (1000 mil) height
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Ordering Information Type HYM 641020GS-60 HYM 641020GS-70 HYM 641010GS-60 HYM 641010GS-70 Ordering Code Q67100 - Q2003 on request Q67100 - Q2002 on request Package L-DIM-168-1 L-DIM-168-1 L-DIM-168-1 L-DIM-168-1 Descriptions 60 ns DRAM module 70 ns DRAM module 60 ns DRAM module 70 ns DRAM module
Semiconductor Group
631
11.94
HYM 641010/20S-60/-70 1M x 64 Module
The HYM 641010/20GS-60/-70 is a 8 M Byte DRAM module organized as 1 048 576 words by 64-bit in a 168-pin, dual read-out, single-in-line package comprising sixteen HYB 514400BJ/BT 1M x 4 DRAMs in 300 mil wide SOJ or TSOPII - packages mounted together with sixteen 0.2 F ceramic decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using four BiCMOS 8-bit buffers/line drivers. Each HYB 514400BJ/BT is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The density and speed of the module can be detected by the use of presence detect pins.
Pin Definitions and Functions Pin No A0-A9,B0 DQ0 - DQ63 RAS0, RAS2 CAS0 - CAS7 WE0, WE2 OE0, OE2 Function Address Input Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Output Enable Power (+ 5 V) Ground Presence Detect Pins Presence Detect Enable ID indentification bit No Connection
Vcc Vss
PD1 - PD8 PDE ID0 , ID1 N.C.
Presence-Detect and ID-pin Thruth Table: Module HYM 641010/20GS-60 HYM 641010/20GS-70 ID0 ID1 PD1 0 0 PD2 0 0 PD3 1 1 PD4 0 0 PD5 0 0 PD6 1 0 PD7 1 1 PD8 1 1
Vss Vss
Vss Vss
Note: 1= high level ( driver output), 0 = low level ( driver output) for PDE active ( ground) . For PDE at a high level all PD terminals are in tri-state.
Semiconductor Group
632
HYM 641010/20S-60/-70 1M x 64 Module
Pin Configuration PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Symbol
Vss DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC Vss DQ8 DQ9 DQ10 DQ11 DQ12 VCC DQ13 DQ14 DQ15 NC Vss NC NC VCC WE0 CAS0 CAS2 RAS0 OE0 Vss A0 A2 A4 A6 A8 NC NC VCC NC NC
PIN #
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Symbol
Vss OE2 RAS2 CAS4 CAS6 WE2 VCC NC NC DQ16 DQ17 Vss DQ18 DQ19 DQ20 DQ21 VCC DQ22 NC NC NC NC DQ23 NC DQ24 Vss DQ25 DQ26 DQ27 DQ28 VCC DQ29 DQ30 DQ31 NC Vss PD1 PD3 PD5 PD7 ID0 VCC
PIN #
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
Symbol
Vss DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 NC Vss DQ40 DQ41 DQ42 DQ43 DQ44 VCC DQ45 DQ46 DQ47 NC Vss NC NC VCC NC CAS1 CAS3 NC NC Vss A1 A3 A5 A7 A9 NC NC VCC NC B0
PIN #
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol
Vss NC NC CAS5 CAS7 PDE VCC NC NC DQ48 DQ49 Vss DQ50 DQ51 DQ52 DQ53 VCC DQ54 NC NC NC NC DQ55 NC DQ55 Vss DQ57 DQ58 DQ59 DQ60 VCC DQ61 DQ62 DQ63 NC Vss PD2 PD4 PD6 PD8 ID1 VCC
Semiconductor Group
633
HYM 641010/20S-60/-70 1M x 64 Module
Block Diagram
Semiconductor Group
634
HYM 641010/20S-60/-70 1M x 64 Module
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 125 C Soldering temperature ............................................................................................................ 260 C Soldering time ............................................................................................................................. 10 s Input/output voltage ........................................................................................................ - 1 to + 7 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation................................................................................................................ 12,32 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics 1) TA = 0 to 70 C; VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Symbol Limit Values min. max. 5.5 0.8 - 0.4 10 10 V V V V A A 2.4 - 1.0 2.4 - - 10 - 10 Unit Test Condition - - - - - -
VIH VIL VOH VOL II(L) IO(L)
ICC1 Average VCC supply current: HYM 641010/20GS-60 HYM 641010/20GS-70
(RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH)
- -
1760 1600
mA mA
2), 3)
ICC2
-
50
mA
-
Average VCC supply current during RAS ICC3 only refresh cycles: HYM 641010/20GS-60 HYM 641010/20GS-70 (RAS cycling, CAS = VIH , tRC = tRC min.)
2)
- -
1760 1600
mA mA
Semiconductor Group
635
HYM 641010/20S-60/-70 1M x 64 Module
DC Characteristics (cont'd) 1) Parameter Symbol Limit Values min. Average VCC supply current during fast ICC4 page mode: HYM 641010/20GS-60 HYM 641010/20GS-70 (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V) max. Unit Test Condition
2), 3)
- -
1120 1120
mA mA
ICC5
-
30
mA
-
Average VCC supply current during ICC6 CAS-before-RAS refresh mode: HYM 641010/20GS-60 HYM 641010/20GS-70 (RAS, CAS cycling, tRC = tRC min.)
1)
- -
1760 1600
mA mA
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9,B0) Input capacitance (RAS0, RAS2) Input capacitance (CAS0-CAS7) Input capacitance (WE0,WE2,OE0,OE2) I/O capacitance (DQ0-DQ63) Symbol min. Limit Values max. 20 80 20 20 20 pF pF pF pF pF - - - - - Unit
CI1 CI2 CI3 CI4 CIO1
Semiconductor Group
636
HYM 641010/20S-60/-70 1M x 64 Module
AC Characteristics 4) 5)14) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol Limit Values HYM 641010/20GS-60 min. Random read or write cycle time Fast page mode cycle time Access time from RAS Access time from CAS
6) 12) 6) 11) 12) 6) 11)
Unit
HYM 641010/20GS-70 min. 130 45 - - - - 0 0 3 50 70 70 40 20 70 20 20 15 5 10 0 10 0 15 max. - - 70 20 35 40 - 20 50 - 10000 200000 - - - 10000 50 35 - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
max. - - 60 15 30 35 - 20 50 - 10000 200000 - - - 10000 45 30 - - - - - -
tRC tPC tRAC tCAC
110 40 - - - - 0 0 3 40 60 60 35 15 60 15 20 15 5 10 0 10 0 15
Access time from column address tAA Access time from CAS prech arge
6)
tCPA tCLZ tOFF tT tRP tRAS tRASP tRHCP tRSH tCSH tCAS
CAS to output in low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS pulse width (fast page mode) CAS precharge to RAS delay RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time CAS precharge time (fast page mode) Row address setup time Row address hold time Column address setup time Column address hold time
6) 7) 5)
11)
tRCD tRAD
12)
tCRP tCP tASR tRAH tASC tCAH
Semiconductor Group
637
HYM 641010/20S-60/-70 1M x 64 Module
AC Characteristics (cont'd) 4) 5)14) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol Limit Values HYM 641010/20GS-60 min. Column address to RAS lead time tRAL Read command setup time Read command hold time Read command hold time ref. to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Refresh period Write command setup time CAS setup time CAS hold time RAS to CAS precharge time CAS precharge time Write to RAS precharge time Write to time ref. to RAS
13) 13) 10) 13) 13) 9) 9) 8)
Unit
HYM 641010/20GS-70 min. 35 0 0 0 15 15 20 20 0 15 - 0 5 15 0 10 10 10 max. - - - - - - - - - - 16 - - - - - - - ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns
max. - - - - - - - - - - 16 - - - - - - -
30 0 0 0 10 10 15 15 0 15 - 0 5 15 0 10 10 10
tRCS tRCH tRRH
8)
tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCP tWRP tWRH
Semiconductor Group
638
HYM 641010/20S-60/-70 1M x 64 Module
Notes 1) All voltages are referenced to VSS . 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles out of which at least one cycle has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalant of 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge. 10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance). 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 13) For CAS-before-RAS cycles only. 14) A 2 ns timing skew has to be added to all values due to the use of the buffers / line drivers
Semiconductor Group
639

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