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| STPC(R) INDUSTRIAL PC Compatible Embedded Microprocessor s s s s s s s s s s POWERFUL X86 PROCESSOR 64-BIT BUS ARCHITECTURE 64-BIT 66MHz DRAM CONTROLLER SVGA GRAPHICS CONTROLLER 135MHz RAMDAC UMA ARCHITECTURE TFT DISPLAY CONTROLLER PCI MASTER / SLAVE / ARBITER LOCAL BUS INTERFACE ISA (MASTER/SLAVE) INTERFACE -INCLUDING THE IPC PC-CARD INTERFACE - PCMCIA - CARDBUS I/O FEATURES - PC/AT+ KEYBOARD CONTROLLER - PS/2 MOUSE CONTROLLER - 2 SERIAL PORTS - 1 PARALLEL PORT IPC - DMA CONTROLLER - INTERRUPT CONTROLLER - TIMER / COUNTERS POWER MANAGEMENT PCI m/s PBGA388 s Figure 1. Logic Diagram s x86 Core Host I/F Serial2 // Port Serial1 TFT Kbd ext Mouse ISA BUS Local Bus I/F ISA I/F IPC 82C206 s s PCI CONTROLLER STPC INDUSTRIAL OVERVIEW The STPC Industrial integrates a fully static x86 processor, fully compatible with standard fifth generation x86 processors, and combines it with powerful chipset, graphics, TFT, PC-Card, Local Bus, keyboard, mouse, serials and parallel interfaces to provide a single Industrial oriented PC compatible subsystem on a single device. The performance of the device is comparable with the performance of a typical P5 generation system. The device is packaged in a 388 Plastic Ball Grid Array (PBGA). PCI BUS PCMCIA CARDBUS GE VGA CRTC DRAM I/F HW Cursor Monitor TFT I/F TFT Output SYNC Output 11/2/02 Issue 2.4 1/69 STPC INDUSTRIAL s s s s s s s s s X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Access up to 4GB of external memory. 8Kbyte unified instruction and data cache with write back capability. Parallel processing integral floating point unit, with automatic power down. Clock core speeds up to 100 MHz. Fully static design for dynamic clock control. Low power and system management modes. Optimized design for 3.3V operation. DRAM Controller Integrated system memory and graphic frame memory. Supports up to 128-MByte system memory in 4 banks and down to as little as 2Mbytes. Supports 4-MByte, 8-MByte, 16-MByte, and 32-MByte single-sided and double-sided DRAM SIMMs. Four quad-word write buffers for CPU to DRAM and PCI to DRAM cycles. Four quad-word read prefetch buffers for PCI masters. Supports Fast Page Mode & EDO DRAMs. Programmable timing for DRAM parameters including CAS pulse width, CAS pre-charge time, and RAS to CAS delay. 60, 70, 80 & 100ns DRAM speeds. Memory hole between 1 MByte & 8 MByte supported for PCI/ISA busses. Hidden refresh. s s s s s s s s CRT Controller Integrated 135MHz triple RAMDAC allowing for 1280 x 1024 x 75Hz display. Requires external frequency synthesizer and reference sources. 8, 16, 24 and 32-bit pixels. Interlaced or non-interlaced output. TFT Interface Programmable panel size up to 1024 by 1024 pixels. Support for 640 x 480, 800 x 600 & 1024 x 768 active matrix TFT flat panels with 9, 12, 18-bit interface. Support 1 & 2 Pixels per Clock. Programmable image positionning. Programmable blank space insertion in text mode. Programmable horizontal and vertical image expansion in graphic mode. A fully programmable PWM (Pulse Width Modulator) signals to adjust the flat panel brightness and contrast. Supports PanelLinkTM high speed serial transmitter externally for high resolution panel interface. PCI Controller Fully compliant with PCI Version 2.1 specification. Integrated PCI arbitration interface. Up to 3 masters can connect directly. External PAL allows for greater than 3 masters. Translation of PCI cycles to ISA bus. Translation of ISA master initiated cycle to PCI. Support for burst read/write from PCI master. 0.33X and 0.5X CPU clock PCI clock. Local Bus interface 66MHz, low latency bus. Asynchronous / synchronous. 22-bit address and 16-bit data busses. 2 Programmable Flash EPROM Chip Select. 4 Programmable I/O Chip Select. Separate memory and I/O address spaces. Memory prefetch (improved performances). s s s s s s s s s s s s s s s s s s s s s To check if your memory device is supported by the STPC, please refer to Table 6-24 in the Programming Manual. s s s s s s s s s s s s s s s s s s s Graphics Controller 64-bit windows accelerator. Complete backward compatibility to VGA and SVGA standards. Hardware acceleration for text (generalized bit map expansion), bitblts, transparent blts and fills. Up to 64 x 64 bit graphics hardware cursor. Up to 4MB long linear frame buffer. 8, 16, 24 and 32 bit pixels. Drivers for Windows and other operating systems. 2/69 Issue 2.4 - February 11, 2002 STPC INDUSTRIAL s s s s s s s s s ISA master/slave Generation of the ISA clock from either 14.318MHz oscillator clock or system clock Programmable extra wait state for ISA cycles Supports I/O recovery time for back to back I/O cycles. Fast Gate A20 and Fast reset. Supports the single ROM that C, D, or E. blocks shares with F block BIOS ROM. Supports flash ROM. Supports ISA hidden refresh. Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI and Host bus. NSP compliant. PC-Card interface Support one PCMCIA 2.0 / JEIDA 4.1 68-pin standard PC Card Socket. Power Management support. Support PCMCIA/ATA specifications. Support I/O PC Card with pulse-mode interrupts. Provides an ExCATM implementation to PCMCIA 2.0 / JEIDA 4.1 standards. DMA support. Keyboard interface Fully PC/AT& compatible Mouse interface Fully PS/2 compatible s s s s s s s s s Serial interface 16550A compatible Programmable word length, stop bits, parity. 16-bit programmable baud rate generator. Interrupt generator. Loop-back mode. 8-bit scratch register. Two 16-bit FIFOs. Two DMA handshake lines. Parallel port Standard Centronics mode supported. Nibble mode supported. Integrated Peripheral Controller Two 8237/AT compatible 7-channel DMA controllers. Two 8259/AT compatible interrupt Controller. 16 interrupt inputs - ISA and PCI. Three 8254 compatible Timer/Counters. Co-processor error support logic. Power Management Four power saving modes: On, Doze, Standby, Suspend. Programmable system activity detector Supports SMM. Supports IO trap & restart. Independent peripheral time-out timer to monitor hard disk, serial & parallel ports. Supports APM Supports RTC, interrupt and DMA wake ups s s s s s s s s s s s s s s s s s s s s s s s s s s s ExCA is a trademark of PCMCIA / JEIDA. PanelLink is a trademark of SiliconImage, Inc Issue 2.4 - February 11, 2002 3/69 STPC INDUSTRIAL 4/69 Issue 2.4 - February 11, 2002 GENERAL DESCRIPTION 1 GENERAL DESCRIPTION At the heart of the STPC Industrial is an advanced 64-bit processor block, dubbed the 5ST86. The 5ST86 includes a powerful x86 processor core along with a 64-bit DRAM controller, advanced 64-bit accelerated graphics and video controller, a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus). The STPC Industrial has in addition to the 5ST86 a TFT output, a Local Bus interface, PC Card and super I/O features. The STPC Industrial makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buffer. This means a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional PCI bus. The 64-bit wide memory array provides the system with 320MB/s peak bandwidth, double that of an equivalent system using 32 bits. This allows for higher resolution screens and greater color depth. The processor bus runs at 66Mhz further increasing "standard" bandwidth by at least a factor of two. The `standard' PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional functions such as communication ports are accessed by the STPC Industrial via an internal ISA bus. The PCI bus is the main data communication link to the STPC Industrial chip. The STPC Industrial translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports the generation of Configuration cycles on the PCI bus. The STPC Industrial, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devices. Graphics functions are controlled through the onchip SVGA controller and the monitor display is produced through the 2D graphics display engine. This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost. It performs limited graphics drawing operations which include hardware acceleration of text, bitblts, transparent blts and fills. The results of these operations change the contents of the on-screen or offscreen frame buffer areas of DRAM memory. The frame buffer can occupy a space up to 4 Mbytes anywhere in the physical main memory. The maximum graphics resolution supported is 1280x1024 in 65536 colours at 75Hz refresh rate and is VGA and SVGA compatible. Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate above display resolution. To generate the TFT output, the STPC Industrial extracts the digital video stream before the RAMDAC and reformats it to the TFT format. The height and width of the flat panel are programmable through configuration registers up to a size of 1024 by 1024. By default, lower resolution images cover only a part of the larger TFT panel. The STPC Industrial allows to expand the image vertically and horizontally in text mode by inserting programmable blank pixels. It allows expantion of the image vertically and horizontally in graphics mode by replicating pixels. The replication of J times every K pixel is independently programmable in the vertical and horizontal directions. PanelLinkTM is a proprietary interconnect protocol defined by Silicon Image, Inc. It consists of a transmitter that takes parallel video/graphics data from the host LCD graphics controller and transmits it serially at high speed to the receiver which controls the TFT panel. The TFT interface is designed to support the connection of this control signal to the PanelLinkTM transmitter. The STPC Industrial CARDBUS / PCMCIA controller has been specifically designed to provide the interface with PC-Cards which contain additional memory or I/O and provides an ExCATM implementation to PCMCIA 2.0 / JEIDA 4.1 standards. The power management control facilities include socket power control, insertion/removal capability, power saving with Windows inactivity, NCS controlled Chip Power Down, together with further controls for 3.3v suspend with Modem Ring Resume Detection. Issue 2.4 - February 11, 2002 5/69 GENERAL DESCRIPTION The need for system configuration jumpers is eliminated by providing address mapping support for PCMCIA 2.0 / JEIDA 4.1 PC-Card memory together with address windowing support for I/O space. Selectable interrupt steering from PC-Card to internal system bus is also provided. The STPC Industrial implements a multi-function parallel port. The standard PC/AT compatible logical address assignments for LPT1, LPT2 and LPT3 are supported. The parallel port can be configured for any of the following 3 modes and supports the IEEE Standard 1284 parallel interface protocol standards as follow: -Compatibility Mode (Forward channel, standard) -Nibble Mode (Reverse channel, PC compatible) -Byte Mode (Reverse channel, PS/2 compatible) The STPC Industrial BGA package has 388 balls, but this is not sufficient for all the integrated functions, therefore some features are sharing the same balls and can not be used at the same time. The STPC Industrial configuration is done by `strap options'. It is a set of pull-up or pull-down resistors on the memory data bus, checked on reset, which auto-configure the STPC Industrial. We can distinguish three main blocks independently configurables : The ISA / Local Bus block, the Serial 1 / TFT block, and the PCI / PC Card block. From the first block, we can activate either the ISA bus and some IPC additionnal features, or the Local bus, the parallel port and the second serial interface. From the second block, we can activate either the first serial port, or the TFT extension to get from 4 bit per colour to 6 bit per colour. From the third block, we can activate either the PCI bus, or the PC Card interface (CardBus/ PCMCIA/ZoomVideo). The STPC Industrial core is compliant with the Advanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal computers. The Power Management Unit module (PMU) controls the power consumption providing a comprehensive set of features that control the power usage and supports compliance with the United States Environmental Protection Agency's Energy Star Computer Program. The PMU provides following hardware structures to assist the software in managing the power consumption by the system. - System Activity Detection. - 3 power-down timers detecting system inactivity: - Doze timer (short durations). - Stand-by timer (medium durations). - Suspend timer (long durations). - House-keeping activity detection. - House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - Peripheral activity detection. - Peripheral timer detecting peripheral inactivity - SUSP# modulation to adjust the system performance in various power down states of the system including full power on state. - Power control outputs to disable power from different planes of the board. Lack of system activity for progressively longer periods of time is detected by the three power down timers. These timers can generate SMI interrupts to CPU so that the SMM software can put the system in decreasing states of power consumption. Alternatively, system activity in a power down state can generate SMI interrupt to allow the software to bring the system back up to full power on state. The chip-set supports up to three power down states described above, these correspond to decreasing levels of power savings. Power down puts the STPC Industrial into suspend mode. The processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. During the suspend mode, internal clocks are stopped. Removing power down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. Because of the static nature of the core, no internal data is lost.. 6/69 Issue 2.4 - February 11, 2002 GENERAL DESCRIPTION Figure 1.1. Functionnal description. x86 Core Host I/F ISA BUS Serial 2 // Port Serial 1 TFT extension Kbd Mouse Local Bus I/F ISA m/s IPC 82C206 PCI m/s PCI m/s PCI BUS PCMCIA CARDBUS GE HW Cursor Monitor VGA CRTC TFT I/F TFT Output DRAM I/F SYNC Output Issue 2.4 - February 11, 2002 7/69 GENERAL DESCRIPTION Figure 1.2. PCI, PCMCIA & CARDBUS modes: PCI m/s PCI BUS PCMCIA CARDBUS PCI m/s PCI BUS PCMCIA CARDBUS PCI m/s PCI BUS PCMCIA CARDBUS 8/69 Issue 2.4 - February 11, 2002 GENERAL DESCRIPTION Figure 1.3. Local Bus and ISA bus modes: Serial 2 // Port ISA BUS Local Bus I/F ISA m/s IPC 82C206 Serial 2 // Port ISA BUS Local Bus I/F ISA m/s IPC 82C206 Figure 1.4. TFT in normal (serial 1 available) and extended modes (serial 1 unavailable). Kbd Mouse Serial 1 TFT extension Kbd Mouse Serial 1 TFT extension TFT I/F 9-bit mode 12-bit mode TFT I/F 18-bit mode 2 x 9-bit mode TFT Output TFT Output Issue 2.4 - February 11, 2002 9/69 GENERAL DESCRIPTION Figure 2. Typical PC oriented Application Super I/O RTC IDE Serial Ports Parallel Port Floppy Flash ISA MUX IRQ MUX Monitor SVGA DMA.REQ TFT STPC Industrial DMA.ACK DMUX Keyboard Mouse PCI 4x 16-bit EDO DRAMs 10/69 Issue 2.4 - February 11, 2002 GENERAL DESCRIPTION Figure 3. Typical Embedded Application STPC Local Bus SRAM I/O Peripheral Flash MUX IRQ Monitor SVGA TFT PC-Card PCMCIA CARDBUS STPC Industrial Keyboard Mouse Serial Ports Parallel Port 4x 16-bit EDO DRAMs Issue 2.4 - February 11, 2002 11/69 PIN DESCRIPTION 2 PIN DESCRIPTION 2.1. INTRODUCTION The STPC Industrial integrates most of the functionalities of the PC architecture. Therefore, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Industrial. This offers improved performance due to the tight coupling of the processor core and it's peripherals. As a result many of the external pin connections are made directly to the on-chip peripheral functions. Figure 2-1 shows the STPC Industrial external interfaces. It defines the main buses and their function. Table 2-1 describes the physical implementation listing signal types and their functionalities. Table 2-2 provides a full pin listing and description. Table 2-4 provides a full listing of the STPC Industrial package pin location physical connection. Please refer to the pin allocation drawing for reference. Due to the number of pins available for the package, and the number of functional I/Os, some pins have several functions, selectable by strap option on Reset. Table 2-3 provides a summary of these pins and their functions. Table 2-1. Signal Description Group name Basic Clocks, Reset & Xtal (SYS) DRAM Controller(DRAM) PCI Controller PC Card Interface Keyboard/Mouse Controller (SIO) Local Bus I/F, Parallel I/F, Serial 2 ISA Interface/IPC extensions Serial 1 (SIO) TFT output VGA Controller (VGA) Grounds VDD Analog specific VCC/VDD Reserved Total Pin Count Qty 13 89 55 64 75 73 8 24 64 4 75 26 10 74 16 16 1 388 Figure 2-1. STPC Industrial External Interfaces x86 core STPC Industrial NORTH BRIDGE PCI SYS SOUTH BRIDGE DRAM VGA PC TFT CARD ISA/ LOCAL BUS SIO 89 10 24 12 55 13 75 38 12/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir BASIC CLOCKS AND RESETS SYSRSTI#* I SYSRSTO#* O XTALI I XTALO O PCI_CLKI* I PCI_CLKO O ISA_CLK, ISA_CLK2X O CLK14M O HCLK* I/O DEV_CLK* O GCLK2X I/O DCLK I/O VDD_xxx_PLL MEMORY INTERFACE MA[11:0] RAS#[3:0] CAS#[7:0] MWE# MD[63:0] Description System Reset / Power good Reset Output to System 14.3 MHz Crystal Input 14.3 MHz Crystal Output 33 MHz PCI/CardBus Input Clock 33 MHz PCI/CardBus Output Clock ISA Clock x1 and x2 (also Multiplexer Select Line For IPC) ISA bus synchronisation clock 33 / 66 MHz Host Clock (Test) 24 MHz Peripheral Clock 80 MHz Graphics Clock 135 MHz Dot Clock Power Supply for PLL Clocks Qty 1 1 1 1 1 1 2 1 1 1 1 1 O O O O I/O Memory Address Row Address Strobe Column Address Strobe Write Enable Memory Data 12 4 8 1 64 LOCAL BUS INTERFACE (COMBINED WITH ISA BUS ) PA[21:0]* O Address Bus [21:0] PD[15:0]* I/O Data Bus [15:0] PRDY#* I Ready PWR#[1:0]* O Memory and I/O Write signals PRD#[1:0]* O Memory and I/O Read signals FCS#[1:0]*, IOCS#[3:0]* O Flash Memory and I/O Chip Select ISA BUS INTERFACE (COMBINED WITH LOCAL BUS, PARALLEL PORT, SERIAL INTERFACE) LA[23:17]* O Unlatched Address SA[19:0]* O Latched Address SD[15:0]* I/O Data Bus IOCHRDY* I I/O Channel Ready ALE* O Address Latch Enable BHE#* O System Bus High Enable MEMR#*, MEMW#* I/O Memory Read & Write SMEMR#*, SMEMW#* O System Memory Read and Write IOR#*, IOW#* I/O I/O Read and Write MASTER#* I Add On Card Owns Bus MCS16#*, IOCS16#* I Memory Chip Select 16, I/O Chip Select 16 REF#* I Refresh Cycle AEN* O Address Enable IOCHCK#* I I/O Channel Check (ISA) RTCRW#* O RTC Read / Write# RTCDS#* O RTC Data Strobe RTCAS#* O RTC Address Strobe 22 16 1 2 2 6 7 20 16 1 1 1 2 2 2 1 2 1 1 1 1 1 1 Issue 2.4 - February 11, 2002 13/69 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name RMRTCCS#* GPIOCS#* IRQ_MUX[3:0]* DACK_ENC[2:0]* DREQ_MUX[1:0]* TC* Dir O I/O I O I O Description ROM / RTC Chip Select General Purpose Chip Select Multiplexed Interrupt Request DMA Acknowledge Multiplexed DMA Request ISA Terminal Count Qty 1 1 4 3 2 1 KEYBOARD & MOUSE INTERFACE KBDATA*, MDATA* I KBCLK*, MCLK* O Keyboard & Mouse Data Line Keyboard & Mouse Clock Line 2 2 SERIAL INTERFACE (SERIAL 1 COMBINED WITH TFT INTERFACE / SERIAL 2 COMBINED WITH IPC ) SIN1*, SIN2* I Serial Data In (Serial 1, 2) SOUT1*, SOUT2* O Serial Data Out (Serial 1, 2) CTS1#*, CTS2#* I Clear To Send (Serial 1, 2) RTS1#*, RTS2#* O Request To Send (Serial 1, 2) DSR1#*, DSR2#* I Data Set Ready (Serial 1, 2) DTR1#*, DTR2#* O Data Terminal Ready (Serial 1,2) DCD1#*, DCD2#* I Data Carrier Detect (Serial 1, 2) RI1#*, RI2#* I Ring Indicator (Serial 1, 2) PARALLEL PORT (COMBINED WITH ISA BUS AND IPC) PE* I Paper End SLCT* I SELECT BUSY#* I BUSY ERR#* I ERROR ACK#* I Acknowledge PDDIR#* O Parallel Device Direction STROBE#* O PCS / STROBE# INIT#* O INIT AUTPFDX#* O Automatic Line Feed SLCTIN#* O SELECT IN PPD[7:0]* I/O Data Bus PCMCIA INTERFACE (COMBINED WITH PCI / CARDBUS) RESET* O Reset A[25:0]* O Address Bus D[15:0]* I/O Data Bus IORD#*, IOWR#* O I/O Read and Write DREQ#* / WP* / IOIS16#* I DMA Request // Write Protect // I/O Size is 16-bit BVD1*, BVD2* I Battery Voltage Detect I Ready / Busy // Interrupt Request READY#*/BUSY#*/IREQ#* WAIT#* I Wait INPACK#* I Input Port Acknowledge OE#* / TCw* O Output Enable // DMA Terminal Count WE#* / TCr* O Write Enable // DMA Terminal Count DACK* / REG#* O DMA Acknowledge // Register CD1#*, CD2#* I Card Detect 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 8 1 26 16 2 1 2 1 1 1 1 1 1 2 14/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name CE1#*, CE2#* VS1#*, VS2#* VCC5_EN* VCC3_EN* VPP_PGM* VPP_VCC* Dir O I O O O O Description Card Enable Voltage Sense Power Switch control Power Switch control Power Switch control Power Switch control Qty 2 2 1 1 1 1 : 5 V power : 3.3 V power : Program power : VCC power CARDBUS INTERFACE (COMBINED WITH PCI / PCMCIA) CCLKRUN* I/O Clock CRST#* O Reset CSTSCHG#* I System Change CAD[31:0]* I/O Address / Data CBE[3:0]* I/O Bus Commands / Byte Enables CFRAME#* I/O Cycle Frame CTRDY#* I/O Target Ready CIRDY#* I/O Initiator Ready CSTOP#* I/O Stop Transaction CDEVSEL#* I/O Device Select CPAR* I/O Parity Signal Transactions CSERR#* I System Error CPERR#* I/O Parity Error CBLOCK#* I/O PCI Lock CCD[2:1]* I Card Detect CINT#* I Interrupt Request CREQ#* I Request CGNT#* O Grant PCI INTERFACE (COMBINED AD[31:0]* BE[3:0]* FRAME#* TRDY#* IRDY#* STOP#* DEVSEL#* PAR* SERR#* LOCK#* PCI_REQ#[2:0]* PCI_GNT#[2:0]* PCI_INT[3:0]* WITH PCMCIA / CARDBUS) I/O Address / Data I/O Bus Commands / Byte Enables I/O Cycle Frame I/O Target Ready I/O Initiator Ready I/O Stop Transaction I/O Device Select I/O Parity Signal Transactions O System Error I PCI Lock I PCI Request O PCI Grant I PCI Interrupt Request 1 1 1 32 4 1 1 1 1 1 1 1 1 1 2 1 1 1 32 4 1 1 1 1 1 1 1 1 3 3 4 Issue 2.4 - February 11, 2002 15/69 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name MONITOR INTERFACE RED, GREEN, BLUE VSYNC* HSYNC* VREF_DAC RSET COMP DDC[1:0]* SCL / DDC[1]* SDA / DDC[0]* Dir O I/O I/O I I I I/O I/O I/O Description Red, Green, Blue Vertical Sync Horizontal Sync DAC Voltage reference Resistor Set Compensation Display Data Channel Serial Link IC Interface - Clock / Can be used for VGA DDC[1] signal IC Interface - Data / Can be used for VGA DDC[0] signal Qty 3 1 1 1 1 1 2 1 1 TFT INTERFACE (COMBINED WITH SERIAL 1) R[5:0], G[5:0], B[5:0] O Red, Green, Blue FPLINE O Horizontal Sync FPFRAME O Vertical Sync DE O Data Enable ENAVDD O Enable Vdd of flat panel ENVCC O Enable Vcc of flat panel PWM O PWM back-light control MISCELLANEOUS SPKRD* SCAN_ENABLE 18 1 1 1 1 1 1 O I Speaker Device Output Test Pin - Reserved 1 1 Note; * denotes that the pin is V5T (see Section 4 ) 16/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION 2.2. SIGNAL DESCRIPTIONS 2.2.2 BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply's power good signal. PWGD is asynchronous to all clocks, and acts as a negative active reset. The reset circuit initiates a hard reset on the rising edge of PWGD. SYSRSTO# Reset Output to System. This is the system reset signal and is used to reset the rest of the components (not on Host bus) in the system. The ISA bus reset is an externally inverted buffered version of this output and the PCI bus reset is an externally buffered version of this output. XTALI 14.3 MHz Crystal Input XTALO 14.3 MHz Crystal Output. These pins are the 14.318 MHz crystal input; This clock is used as the reference clock for the internal frequency synthesizer to generate the HCLK and CLK24M. A 14.318 MHz Series Cut Quartz Crystal should be connected between these two pins. Balance capacitors of 15 pF should also be added. In the event of an external oscillator providing the master clock signal to the STPC Industrial device, the TTL signal should be provided on XTALO. PCI_CLKI 33 MHz PCI Input Clock This signal must be connected to a clock generator and is usually connected to PCI_CLKO. PCI_CLKO 33 MHz PCI Output Clock. This is the master PCI bus clock output ISA_CLK ISA Clock Output (also Multiplexer Select Line For IPC). This pin produces the Clock signal for the ISA bus. It is also used with ISA_CLK2X as the multiplexer control lines for the Interrupt Controller Interrupt input lines. This is a divided down version of the PCICLK or OSC14M. ISA_CLKX2 ISA Clock Output (also Multiplexer Select Line For IPC). This pin produces a signal at twice the frequency of the ISA bus Clock signal. It is also used with ISA_CLK as the multiplexer control lines for the Interrupt Controller Interrupt input lines. CLK14M ISA bus synchronisation clock. This is the buffered 14.318 MHz clock to the ISA bus. This clock also provides the reference clock to the frequency synthesizer that generates GCLK2X and DCLK. HCLK Host Clock. This is the host 1X clock. Its frequency can vary from 50 MHz to 75 MHz. All host transactions and PCI transactions are synchronized to this clock. Host transactions executed by the DRAM controller are also driven by this clock. DEV_CLK 24 MHz Peripheral Clock (floppy drive). This 24 MHZ signal is provided as a convenience for the system integration of a Floppy Disk driver function in an external chip. GCLK2X 80 MHz Graphics Clock. This is the Graphics 2X clock, which drives the graphics engine and the DRAM controller to execute the graphics and display cycles. Normally GCLK2X is generated by the internal frequency synthesizer, and this pin is an output. By setting a bit in Strap Register 2, this pin can be made an input so that an external clock can replace the internal frequency synthesizer. DCLK 135 MHz Dot Clock. This is the dot clock, which drives graphics display cycles. Its frequency can go from 8 MHz (using internal PLL) up to 135 MHz, and it is required to have a worst case duty cycle of 60-40. The direction can be controlled by a strap option or an internal register bit. 2.2.3 MEMORY INTERFACE MA[11:0] Memory Address. These 12 multiplexed memory address pins support external DRAM with up to 4K refresh. These include all 16M x N and some 4M x N DRAM modules. The address signals must be externally buffered to support more than 16 DRAM chips. The timing of these signals can be adjusted by software to match the timings of most DRAM modules. MD[63:0] Memory Data. This is the 64-bit memory data bus. If only half of a bank is populated, MD63-32 is pulled high, data is on MD31-0. MD20-0 are also used as inputs at the rising edge of PWGD to latch in power-up configuration information into the ADPC strap registers. RAS#[3:0] Row Address Strobe. There are four active low row address strobe outputs, one each for each bank of the memory. Each bank contains 4 or 8 bytes of data. The memory controller allows half of a bank (4 bytes) to be populated to enable memory upgrade at finer granularity. The RAS# signals drive the SIMMs directly without any external buffering. These pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the RAS# signals at the pins. Issue 2.4 - February 11, 2002 17/69 PIN DESCRIPTION CAS#[7:0] Column Address Strobe. There are 8 active low column address strobe outputs, one each for each Byte of the memory. The CAS# signals drive the SIMMs either directly or through external buffers. These pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the CAS# signals at the pins. MWE# Write Enable. Write enable specifies whether the memory access is a read (MWE# = H) or a write (MWE# = L). This single write enable controls all DRAMs. It can be externally buffered to boost the maximum number of loads (DRAM chips) supported. The MWE# signals drive the SIMMs directly without any external buffering. 2.2.4 LOCAL BUS INTERFACE (Combined with ISA Bus) PA[21:0] Memory Address. This is the 22-bit Local Bus Address PD[15:0] Data Bus. This is the 16-bit bidirectional Local Bus Data bus. PRDY# Ready. This input signals the Local Bus Ready state. PWR#1 Memory and I/O Write signal for MS Byte PWR#0 Memory and I/O Write signal for LS Byte. PRD#1 Memory and I/O Read signals for MS Byte. PRD#0 Memory and I/O Read signals for LS Byte. FCS#[1:0], IOCS#[3:0] Flash Memory and I/O Chip select. 2.2.5 ISA BUS INTERFACE LA[23:17] Unlatched Address. These unlatched ISA Bus pins address bits 23-17 on 16-bit devices. When the ISA bus is accessed by any cycle initiated from the PCI bus, these pins are in output mode. When an ISA bus master owns the bus, these pins are tristated. SA[19:0] Unlatched Address. These are the 20 low bits of the system address bus of ISA. These pins are used as an input when an ISA bus master owns the bus and are outputs at all other times. SD[15:0] I/O Data Bus (ISA). These are the external ISA data bus pins. IOCHRDY IO Channel Ready. IOCHRDY is the IO channel ready signal of the ISA bus and is driven 18/69 as an output in response to an ISA master cycle targeted to the host bus or an internal register of the STPC Industrial. The STPC Industrial monitors this signal as an input when performing an ISA cycle on behalf of the host CPU, DMA master or refresh. ISA masters which do not monitor IOCHRDY are not guaranteed to work with the STPC Industrial since the access to the system memory can be considerably delayed due to CRT refresh or a write back cycle. ALE Address Latch Enable. This is the address latch enable output of the ISA bus and is asserted by the STPC Industrial to indicate that LA23-17, SA19-0, AEN and SBHE# signals are valid. The ALE is driven high during refresh, DMA master or an ISA master cycles by the STPC Industrial. ALE is driven low after reset. BHE# System Bus High Enable. This signal, when asserted, indicates that a data Byte is being transferred on SD15-8 lines. It is used as an input when an ISA master owns the bus and is an output at all other times. MEMR# Memory Read. This is the memory read command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. The MEMR# signal is active during refresh. MEMW# Memory Write. This is the memory write command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. SMEMR# System Memory Read. The STPC Industrial generates SMEMR# signal of the ISA bus only when the address is below one MByte or the cycle is a refresh cycle. SMEMW# System Memory Write. The STPC Industrial generates SMEMW# signal of the ISA bus only when the address is below one MByte. IOR# I/O Read. This is the IO read command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. IOW# I/O Write. This is the IO write command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. MASTER# Add On Card Owns Bus. This signal is active when an ISA device has been granted bus ownership. MCS16# Memory Chip Select16. This is the decode of LA23-17 address pins of the ISA address Issue 2.4 - February 11, 2002 PIN DESCRIPTION bus without any qualification of the command signal lines. MCS16# is always an input. The STPC Industrial ignores this signal during IO and refresh cycles. IOCS16# IO Chip Select16. This signal is the decode of SA15-0 address pins of the ISA address bus without any qualification of the command signals. The STPC Industrial does not drive IOCS16# (similar to PC-AT design). An ISA master access to an internal register of the STPC Industrial is executed as an extended 8-bit IO cycle. REF# Refresh Cycle. This is the refresh command signal of the ISA bus. It is driven as an output when the STPC Industrial performs a refresh cycle on the ISA bus. It is used as an input when an ISA master owns the bus and is used to trigger a refresh cycle. The STPC Industrial performs a pseudo hidden refresh. It requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. The host bus is then relinquished while the refresh cycle continues on the ISA bus. AEN Address Enable. Address Enable is enabled when the DMA controller is the bus owner to indicate that a DMA transfer will occur. The enabling of the signal indicates to IO devices to ignore the IOR#/IOW# signal during DMA transfers. IOCHCK# IO Channel Check. IO Channel Check is enabled by any ISA device to signal an error condition that can not be corrected. NMI signal becomes active upon seeing IOCHCK# active if the corresponding bit in Port B is enabled. GPIOCS# I/O General Purpose Chip Select 1. This output signal is used by the external latch on ISA bus to latch the data on the SD[7:0] bus. The latch can be use by PMU unit to control the external peripheral devices to power down or any other desired function. RTCRW# Real Time Clock RW#. This pin is used as RTCRW#. This signal is asserted for any I/O write to port 71h. RTCDS# Real Time Clock DS. This pin is used as RTCDS. This signal is asserted for any I/O read to port 71h. RTCAS# Real time clock address strobe. This signal is asserted for any I/O write to port 70h. RMRTCCS# ROM/Real Time clock chip select. This pin is a multi-function pin. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access the ROM. During an IO cycle, this signal is asserted if access to the Real Time Clock (RTC) is decoded. It should be combined with IOR# or IOW# signals to properly access the real time clock. IRQ_MUX[3:0] Multiplexed Interrupt Request. These are the ISA bus interrupt signals. They are to be encoded before connection to the STPC Industrial using ISACLK and ISACLKX2 as the input selection strobes. Note that IRQ8B, which by convention is connected to the RTC, is inverted before being sent to the interrupt controller, so that it may be connected directly to the IRQ# pin of the RTC. 2.2.6 IPC (Combined with Serial Interface) DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Industrial before output and should be decoded externally using ISACLK and ISACLKX2 as the control strobes. DREQ_MUX[1:0] ISA Bus Multiplexed DMA Request. These are the ISA bus DMA request signals. They are to be encoded before connection to the STPC Industrial using ISACLK and ISACLKX2 as the input selection strobes. TC ISA Terminal Count. This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the Byte count expires. 2.2.7 KEYBOARD/MOUSE INTERFACE KBCLK, Keyboard Clock line. Keyboard data is latched by the controller on each negative clock edge produced on this pin. The keyboard can be disabled by pulling this pin low by software control. KBDATA, Keyboard Data Line. 11 bits of data are shifted serially through this line when data is being transferred. Data is synchronised to KBCLK. MCLK, Mouse Clock line. Mouse data is latched by the controller on each negative clock edge produced on this pin. The mouse can be disabled by pulling this pin low by software control. MDATA, Mouse Data Line. 11 bits of data are shifted serially through this line when data is being transferred. Data is synchronised to MCLK. Note: MCLK and MDATA must be pulled when the STPC Mouse interface is not used. 2.2.8 SERIAL INTERFACE (Serial 1 combined with TFT Interface) (Serial 2 combined with IPC) SIN1, SIN2 Input Serial input. Data is clocked in using RCLK/16. 19/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION SOUT1, SOUT2 Serial Output. Data is clocked out using TCLK/16 (TCLK=BAUD#). DCD1#, DCD2# Input Data carrier detect. RI1#, RI2# Input Ring indicator. DSR1#, DSR2# Input Data set ready. CTS1#, CTS2# Input Clear to send. RTS1#, RTS2# Output Request to send. DTR1#, DTR2# Output Data terminal read. 2.2.9 PARALLEL PORT (Combined with ISA Bus an IPC) PE Paper End. Input status signal from printer. SLCT Printer Select. Printer selected input. BUSY# Printer Busy. Input status signal from printer. ERR# Error. Input status signal from printer. ACK# Acknowledge. Input status signal from printer. PDDIR# Parallel Device Direction. Bidirectional control line output. STROBE# PCS/Strobe#. Data transfer strobe line to printer. INIT# Initialize Printer. This output sends an initialize command to the connected printer. AUTPFDX# Automatic Line feed. This output sends a command to the connected printer to automatically generate line feed on received carriage returns. SLCTIN# Select In. Printer select output. PPD[7-0] Printer Data Lines Data transfer lines to printer. Bidirectional depending on modes. Important Note: Where the Parallel Port is not used, PPD[0], connected to device pin C25, must be pulled up to `1'. This is to avoid memory access problems associated with the MCS16 Memory Chip Select line when in the ISA Bus mode. 2.2.10 PCMCIA INTERFACE (Combined with PCI / Cardbus) RESET Card Reset. This output forces a hard reset to a PC Card. D[15:0] I/O Data Bus (PCMCIA). These are the external PCMCIA data bus pins. CA[25-0] Card Address. Used with the lower 11 bits of the ISA Address Bus to generate the Card Address. IORD# I/O Read. This output is used with REG# to gate I/O read data from the PC Card, (only when REG# is asserted). IOWR# I/O Write. This output is used with REG# to gate I/O write data from the PC Card, (only when REG# is asserted). WP Write Protect. This input indicates the status of the Write Protect switch (if fitted) on memory PC Cards (asserted when the switch is set to write protect). BVD1, BVD2 Battery Voltage Detect. These inputs will be generated by memory PC Cards that include batteries and are an indication of the condition of the batteries. BVD1 and BVD2 are kept asserted high when the battery is in good condition. READY#/BUSY#/IREQ# Ready/busy/Interrupt request. This input is driven low by memory PC Cards to signal that their circuits are busy processing a previous write command. WAIT# Bus Cycle Wait. This input is driven by the PC Card to delay completion of the memory or I/O cycle in progress. OE# Output Enable. OE# is an active low output which is driven to the PC Card to gate Memory Read data from memory PC Cards. WE#/PRGM# Write Enable. This output is used by the host for gating Memory Write data. WE# is also used for memory PC Cards that have programmable memory. REG# Attribute Memory Select. This output is inactive (high) for all normal accesses to the Main Memory of the PC Card. I/O PC Cards will only respond to IORD# or IOWR# when REG# is active (low). Also see Section 2.2.6 CD1#, CD2# Card Detect. These inputs provide for the detection of correct card insertion. CD#1 and CD#2 are positioned at opposite ends of the connector to assist in the detection process. These inputs are internally grounded on the PC A[25:0] Address Bus. These are the 25 low bits of the system address bus of the PCMCIA bus. These pins are used as an input when an PCMCIA bus owns the bus and are outputs at all other times. 20/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION Card therefore they will be forced low whenever a card is inserted in a socket. CE1#, CE2# Card Enable. These are active low output signals provided from the PCIC. CE#1 enables even Bytes, CE#2 odd Bytes. ENABLE# Enable. This output is used to activate/ select a PC Card socket. ENABLE# controls the external address buffer logic.C card has been detected (CD#1 and CD#2 = '0'). ENIF# ENIF. This output is used to activate/select a PC Card socket. EXT_DIR EXternal Transceivers Direction Control. This output is high during a read and low during a write. The default power up condition is write (low). Used for both Low and High Bytes of the Data Bus. VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0, VPP2_EN1 Power Control. Five output signals used to control voltages (VPP1, VPP2 and VCC) to a PC Card socket. Also see Section 13.7.5. GPI# General Purpose Input. This signal is hardwired to 1. 2.2.11 CARDBUS INTERFACE (Combined with PCI / PCMCIA) For card bus pinouts, refer to the PCI pinout. 2.2.12 PCI INTERFACE AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data bus of the PCI. This bus is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. BE[3:0]# Bus Commands/Byte Enables. These are the multiplexed command and Byte enable signals of the PCI bus. During the address phase they define the command and during the data phase they carry the Byte enable information. These pins are inputs when a PCI master other than the STPC Industrial owns the bus and outputs when the STPC Industrial owns the bus. FRAME# Cycle Frame. This is the frame signal of the PCI bus. It is an input when a PCI master owns the bus and is an output when STPC Industrial owns the PCI bus. TRDY# Target Ready. This is the target ready signal of the PCI bus. It is driven as an output when the STPC Industrial is the target of the current bus transaction. It is used as an input when STPC Industrial initiates a cycle on the PCI bus. IRDY# Initiator Ready. This is the initiator ready signal of the PCI bus. It is used as an output when the STPC Industrial initiates a bus cycle on the PCI bus. It is used as an input during the PCI cycles targeted to the STPC Industrial to determine when the current PCI master is ready to complete the current transaction. STOP# Stop Transaction. STOP# is used to implement the disconnect, retry and abort protocol of the PCI bus. It is used as an input for the bus cycles initiated by the STPC Industrial and is used as an output when a PCI master cycle is targeted to the STPC Industrial. DEVSEL# I/O Device Select. This signal is used as an input when the STPC Industrial initiates a bus cycle on the PCI bus to determine if a PCI slave device has decoded itself to be the target of the current transaction. It is asserted as an output either when the STPC Industrial is the target of the current PCI transaction or when no other device asserts DEVSEL# prior to the subtractive decode phase of the current PCI transaction. PAR Parity Signal Transactions. This is the parity signal of the PCI bus. This signal is used to guarantee even parity across AD[31:0], CBE[3:0]#, and PAR. This signal is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. (Its assertion is identical to that of the AD bus delayed by one PCI clock cycle) SERR# System Error. This is the system error signal of the PCI bus. It may, if enabled, be asserted for one PCI clock cycle if target aborts a STPC Industrial initiated PCI transaction. Its assertion by either the STPC Industrial or by another PCI bus agent will trigger the assertion of NMI to the host CPU. This is an open drain output. LOCK# PCI Lock. This is the lock signal of the PCI bus and is used to implement the exclusive bus operations when acting as a PCI target agent. PCI_REQ#[2:0] PCI Request. These pins are the three external PCI master request pins. They indicates to the PCI arbiter that the external agents desire use of the bus. PCI_GNT#[2:0] PCI Grant. These pins indicate that the PCI bus has been granted to the master requesting it on its PCI_REQ#. PCI_INT[3:0] PCI Interrupt Request. These are the PCI bus interrupt signals. They are to be encoded before connection to the STPC Industrial using ISACLK and ISACLKX2 as the input selection strobes. Issue 2.4 - February 11, 2002 21/69 PIN DESCRIPTION 2.2.13 MONITOR INTERFACE RED, GREEN, BLUE RGB Video Outputs. These are the three analog color outputs from the RAMDACs. These signals are sensitive to interference, therefore they need to be properly shielded. VSYNC Vertical Synchronisation Pulse. This is the vertical synchronization signal from the VGA controller. HSYNC Horizontal Synchronisation Pulse. This is the horizontal synchronization signal from the VGA controller. VREF_DAC DAC Voltage reference. This pin is an input driving the digital to analog converters. This allows an external voltage reference source to be used. RSET Resistor Current Set. This is the reference current input to the RAMDAC. Used to set the fullscale output of the RAMDAC. COMP Compensation. This is the RAMDAC compensation pin. Normally, an external capacitor (typically 10nF) is connected between this pin and VDD to damp oscillations. DDC[1:0] Direct Data Channel Serial Link. These bidirectional pins are connected to CRTC register 3Fh to implement DDC capabilities. They conform to I2C electrical specifications, they have opencollector output drivers which are internally connected to VDD through pull-up resistors. They can instead be used for accessing IC devices on board. DDC1 and DDC0 correspond to SCL and SDA respectively. 2.2.14 FLAT PANEL INTERFACE SIGNALS (Combined with Serial 1) FPFRAME, Vertical Sync. pulse Output. FPLINE, Horizontal Sync. Pulse Output. DE, Data Enable. R5-0, Red Output. G5-0, Green Output. B5-0, Blue Output. ENAVDD Enable VDD of Flat Panel. ENVCC Enable VCC of Flat Panel. PWM PWM Back-Light Control. 2.2.15 MISCELLANEOUS SPKRD Speaker Drive. This is the output to the speaker and is the AND of the counter 2 output with bit 1 of Port 61h and drives an external speaker driver. This output should be connected to a 7407 type high voltage driver. SCAN_ENABLE Reserved. This pin is reserved for Test and Miscellaneous functions. It has to be set to `0' or connected to ground in normal operation. 22/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION Table 2-3. Signals Sharing the Same Pin ISA BUS / IPC LA[23:22] LA[21:20] LA[19:17] SA[19:1] SA[0] SD[15:0] BHE# MEMR#, MEMW# SMEMR#, SMEMW# GPIOCS# IOCHRDY IOR# IOW# MASTER# MCS16# IOCS16# REF# AEN IOCHCK# RTCRW# RTCDS# RTCAS# RMRTCCS# ALE DACK_ENC[0:2] DREQ_MUX[0:1] TC LOCAL BUS FCS#[0], PRD#[1] PA[21:20] PRD#[0], PWR#[1:0] PA[19:1] PRDY# PD[15:0] FCS#[1] IOCS[3:2] IOCS[1:0] PE SLCT BUSY# ERR# ACK# PDDIR# INIT# AUTPFDX# SLCTIN# PPD[7] PPD[5] PPD[4] PPD[3] PPD[2] PPD[1] DCD2#, DSR2#, SIN2 CTS2#, RTS2# SOUT2 PARALLEL PORT SERIAL INTERFACE TFT INTERFACE B[0,1] G[0,1] R[0,1] SERIAL 1 DCD1#, CTS1# DSR1#, RTS1# SIN1, SOUT1 PCI CARDBUS CCLK CRST# PCMCIA A[16] RESET D[10,9,1,8,0] A[0:6] AD[31:27] AD[26:20] CAD[31:27] CAD[26:20] Issue 2.4 - February 11, 2002 23/69 PIN DESCRIPTION PCI AD[19] AD[18] AD[17] AD[16] AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8:0] BE[3] BE[2] BE[1] BE[0] FRAME# TRDY# IRDY# STOP# DEVSEL# PAR CARDBUS CAD[19] CAD[18] CAD[17] CAD[16] CAD[15] CAD[14] CAD[13] CAD[12] CAD[11] CAD[10] CAD[9] CAD[8:0] CBE[3] CBE[2] CBE[1] CBE[0] CFRAME# CTRDY# CIRDY# CSTOP# CDEVSEL# CPAR PCMCIA A[25] A[7] A[24] A[17] IOWR# A[9] IORD# A[11] OE# / TCw CE[2] A[10] D[15,7,13,6,12,5,11,4,3] DACK/REG# A[12] A[8] CE[1] A[23] A[22] A[15] A[20] A[21] A[13] SERR# LOCK# PCIREQ#[2] PCIREQ#[1] PCIREQ#[0] PCIGNT#[2] PCIGNT#[1] PCIGNT#[0] PCI_INT[3] PCI_INT[2] PCI_INT[1] PCI_INT[0] CSERR# CBLOCK# CREQ# CCD1 CSTSCHG# CGNT# CCD2 WAIT A[19] INPACK# CD1# BVD1 WE# / TCr CD2# BVD2 VCC3_EN VCC5_EN VPP_PGM CINT# CLKRUN READY# DREQ# / WP / IOIS16# 24/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION Table 2-4. Pinout. Pin # C4 A3 AB25 AB23 G25 H23 B20 A20 AC26 H26 J26 AC15 AD16 AE13 AC12 AF13 AD12 AE14 AC14 AF14 AD13 AE15 AD14 AF15 AE16 AD15 AF16 AC17 AE18 AD17 AF18 AE19 AF19 AD18 AE20 AC19 AF20 AD19 AE21 AC20 AF21 AD20 Pin Name Pin # AE22 AF22 AD21 AE23 AC22 AF23 AD22 AE24 AD23 AF24 AE26 AD25 AD26 AC25 AC24 MA[0] MA[1] MA[2] MA[3] MA[4] MA[5] MA[6] MA[7] MA[8] MA[9] MA[10] MA[11] RAS#[0] RAS#[1] RAS#[2] RAS#[3] CAS#[0] CAS#[1] CAS#[2] CAS#[3] CAS#[4] CAS#[5] CAS#[6] CAS#[7] MWE# MD[0] MD[1] MD[2] MD[3] AB24 AB26 AA25 Y23 AA24 AA26 Y25 Y26 Y24 W25 V23 W26 W24 V25 V26 U25 V24 U26 U23 T25 U24 T26 R25 R26 T24 P25 R23 P26 R24 Pin Name MD[4] MD[5] MD[6] MD[7] MD[8] MD[9] MD[10] MD[11] MD[12] MD[13] MD[14] MD[15] MD[16] MD[17] MD[18] MD[19] MD[20] MD[21] MD[22] MD[23] MD[24] MD[25] MD[26] MD[27] MD[28] MD[29] MD[30] MD[31] MD[32] MD[33] MD[34] MD[35] MD[36] MD[37] MD[38] MD[39] MD[40] MD[41] MD[42] MD[43] MD[44] MD[45] MD[46] MD[47] P1 N3 R2 C1 C2 P3 R1 P4 J2 H3 H1 J4 H2 G3 G1 G2 F1 F3 G4 F2 E1 E3 E4 E2 D1 LA[17] / PWR#[0] LA[18] / PWR#[1] LA[19] / PRD#[0] LA[20] / PA[20] LA[21] / PA[21] LA[22] / PRD#[1] LA[23] / FCS#[0] SA[0] / PRDY# SA[1] / PA[1] SA[2] / PA[2] SA[3] / PA[3] SA[4] / PA[4] SA[5] / PA[5] SA[6] / PA[6] SA[7] / PA[7] SA[8] / PA[8] SA[9] / PA[9] SA[10] / PA[10] SA[11] / PA[11] SA[12] / PA[12] SA[13] / PA[13] SA[14] / PA[14] SA[15] / PA[15] SA[16] / PA[16] SA[17] / PA[17] B1 PA[0] Pin # N25 N23 N26 P24 M25 N24 M26 L25 M24 L26 M23 K25 L24 K26 K23 J25 Pin Name MD[48] MD[49] MD[50] MD[51] MD[52] MD[53] MD[54] MD[55] MD[56] MD[57] MD[58] MD[59] MD[60] MD[61] MD[62] MD[63] SYSRSTI# SYSRSTO# XTALI XTALO PCI_CLKI PCI_CLKO ISA_CLK ISA_CLK2X CLK14M HCLK DEV_CLK GCLK2X DCLK Issue 2.4 - February 11, 2002 25/69 PIN DESCRIPTION Pin # D3 D2 P2 M3 N1 M4 N2 L3 M1 M2 L1 K3 L2 K4 K1 J3 K2 J1 T2 R3 T1 R4 U2 AB2 AB1 Y3 AA3 AC2 AB4 AB3 AD2 AC3 E25 E26 F24 D25 E23 D26 E24 C25 AC1 D5 A4 Pin Name SA[18] / PA[18] SA[19] / PA[19] SD[0] / PD[0] SD[1] / PD[1] SD[2] / PD[2] SD[3] / PD[3] SD[4] / PD[4] SD[5] / PD[5] SD[6] / PD[6] SD[7] / PD[7] SD[8] / PD[8] SD[9] / PD[9] SD[10] / PD[10] SD[11] / PD[11] SD[12] / PD[12] SD[13] / PD[13] SD[14] / PD[14] SD[15] / PD[15] BHE# / FCS#[1] MEMR# / IOCS#[3] MEMW# / IOCS#[2] SMEMR# / IOCS#[1] SMEMW# / IOCS#[0] IOCHRDY / SLCT IOR# / BUSY# GPIOCS# / PE IOW# / ERR# MASTER# / ACK# MCS16# / PDDIR# IOCS16# / INIT# REF# / AUTPFDX# AEN / SLCTIN# IOCHCK# / PPD[7] PPD[6] RTCRW# / PPD[5] RTCDS# / PPD[4] RTCAS# / PPD[3] RMRTCCS# / PPD[2] ALE / PPD[1] PPD[0] STROBE# IRQ_MUX[0] IRQ_MUX[1] D18 C18 A17 D17 B16 C17 A16 B15 A15 C16 B14 D15 A14 C15 B13 D13 A13 C14 RESET A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] F25 F26 G24 G23 KBCLK KBDATA MCLK MDATA Y4 AA1 U4 V1 V2 U3 U1 W2 T3 W1 DTR2# RI2# SIN1 / R[0] SOUT1 / R[1] CTS1 / B[1] RTS1# / G[1] DSR1# / G[0] DTR1# DCD1# / B[0] RI1# Pin # C5 B3 AD1 V3 Y2 W4 Y1 W3 AA2 Pin Name IRQ_MUX[2] IRQ_MUX[3] SPKRD DACK_ENC[0]/DCD2# DACK_ENC[1]/DSR2# DACK_ENC[2] / SIN2 DREQ_MUX[0]/CTS2# DREQ_MUX[1]/RTS2# TC / SOUT2 Pin # B12 C13 A12 B11 A11 D12 B10 C11 A10 D10 B9 C10 A9 B8 C9 B7 D8 A7 B6 D7 A6 C7 A5 C6 B4 B22 D22 D24 A18 C26 A21 C19 A25 C22 B18 B19 B24 A24 B23 C23 C20 A19 D20 C21 Pin Name A[17] A[18] A[19] A[20] A[21] A[22] A[23] A[24] A[25] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] IORD# IOWR# WP BVD1 BVD2 READY# WAIT# INPACK# OE# WE# REG# CD1# CD2# CE1# CE2# VS1# VS2# VCC5_EN VCC3_EN 26/69 Issue 2.4 - February 11, 2002 PIN DESCRIPTION Pin # B21 A22 AD4 AF4 AE5 AF3 AE4 AF5 AE6 AF6 AE3 AF2 AE7 AF7 AD7 AE8 AC9 AF8 AD8 AE9 AF9 AE10 AD9 AF10 AC10 AD10 AE11 AF11 AE12 AF12 AD11 C8 AD5 AC5 AE17 AF17 K24 H25 J24 Pin Name VPP_PGM VPP_VCC RED GREEN BLUE VSYNC HSYNC VREF_DAC RSET COMP SDA / DDC[1] SCL / DDC[0] B[2] G[2] R[2] B[3] G[3] R[3] B[4] G[4] R[4] B[5] G[5] R[5] RESERVED FPLINE FPFRAME DE ENAVDD ENVCC PWM SCAN_ENABLE VDD_DAC1 VDD_DAC2 VDD_GCLK_PLL VDD_DCLK_PLL VDD_ZCLK_PLL VDD_DEVCLK_PLL VDD_HCLK_PLL AC7 AD6 G26 H24 A1 A2 A26 B2 B25 B26 C3 C24 D4 D9 D14 D19 D23 H4 J23 L11:16 M11:16 VSS_DAC1 VSS_DAC2 VSS_DLL VSS_DLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D6 D11 D16 D21 F4 F23 L4 L23 T4 T23 AA4 AA23 AC6 AC11 AC16 AC21 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Pin # A8 A23 B5 B17 C12 Pin Name RESERVED RESERVED RESERVED RESERVED RESERVED Pin # N4 N11:16 P11:16 P23 R11:16 T11:16 V4 W23 AC4 AC8 AC13 AC18 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF25 AF26 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Issue 2.4 - February 11, 2002 27/69 PIN DESCRIPTION 28/69 Issue 2.4 - February 11, 2002 STRAP OPTION 3. STRAP OPTION This chapter defines the STPC Industrial Strap Options and their location. Memory Refer to Data Lines MD16 PCI Clock MD17 Host Clock MD18 Graphics Clock MD19 DOT Clock MD20 MD21 MD22 MD23 MD24 HCLK MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD 36 MD 37 MD 38 MD 39 MD 40 MD 41 MD 42 MD 43 MD 44 Serial Port MD 45 MD 46 MD 47 TFT MD 48 MD 49 MD 50 Cardbus Socket MD 51 MD 52 MD 53 MD 56 MD 57 MD 58 CPU MD 59 Designation Reserved PCI_CLKO Divisor HCLK Pad Direction GCLK2x Pad Direction DCLK Pad Direction Reserved Reserved Reserved HCLK PLL Speed Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCMCIA or PCI I/F Local Bus or ISA I/F KeyBoard & Mouse Parallel Port UART1 UART2 Reserved Reserved TFT interface 5V Availability 3.3V Availability x.xV Available y.yV Available Reserved Reserved Reserved Reserved clock speed factor Location Index 4C,bit 0 Index 4C,bit 1 Index 4C,bit 2 Index 4C,bit 3 Index 4C,bit 4 Index 5F,bit 1 Index 5F,bit 2 Index 5F,bit 3 Index 5F,bit 4 Index 5F,bit 5 Actual Settings Pull up User defined Pull up Pull up User defined Pull up Pull up Pull up User defined Pull down Pull down Pull down Pull down Pull down Pull down Pull up Pull down Pull up Pull up Pull up Pull up Pull up User defined User defined User defined User defined User defined User defined Pull down Pull down User defined User defined User defined User defined User defined Pull up Pull up Pull down Pull up User defined Set to '0' Set to '1' HCLK / 2 External External External HCLK / 3 Internal Internal Internal See Section 3.1.6. 3C,bit 3C,bit 3C,bit 3C,bit 3C,bit 3C,bit 3C,bit 3C,bit 3D,bit 3D,bit 3D,bit 3D,bit 3D,bit 0 1 2 3 4 5 6 7 0 1 2 3 4 PCI ISA External External External External PCMCIA Local Bus Internal Internal Internal Internal Disable Unavailable Unavailable Unavailable Unavailable Enable Available Available Available Available X1 X2 Issue 2.4 - February 11, 2002 29/69 STRAP OPTION 3.1. STRAP OPTION REGISTER DESCRIPTION 3.1.1. STRAP REGISTER 0 This register reflect the status of pins MD[7:0] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Strap0 7 MD7 6 MD6 5 MD5 Access = 0022h/0023h 4 MD4 3 MD3 2 MD2 1 Regoffset = 04Ah 0 Rsv This register defaults to the values sampled on MD[7:0] pins after reset Bit Number Sampled Bit 7-2 Bits 1-0 Mnemonic MD[7:2] Rsv Description User defined Reserved. 30/69 Issue 2.4 - February 11, 2002 STRAP OPTION 3.1.2. STRAP REGISTER 1 This register reflect the status of pins MD[15:8] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Strap1 7 MD15 6 MD14 5 MD13 Access = 0022h/0023h 4 MD12 3 MB11 2 MD10 1 Regoffset = 04Bh 0 Rsv This register defaults to the values sampled on MD[15:8] pins after reset Bit Number Sampled Bit 7-2 Bits 1-0 Mnemonic MD[7:2] Rsv Description User defined Reserved. Issue 2.4 - February 11, 2002 31/69 STRAP OPTION 3.1.3. STRAP REGISTER 2 Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the status of pin MD[23]. Bit 4 is writeable, writes to other bits in this register have no effect. Strap2 7 6 Rsv 5 Access = 0022h/0023h 4 MD20 3 MD19 2 MD18 1 MD17 Regoffset = 04Ch 0 Rsv This register defaults to the values sampled on MD[23] and MD[20:16] pins after reset Bit Number Sampled Bits 7-5 Bit 4 Bit 3 Mnemonic Rsv MD20 MD19 Description Reserved. This bit reflects the value sampled on MD[20] pin and controls the Dot clock (DCLK) source. Note This bit is writeable as well as readable. This bit reflects the value sampled on MD[19] pin and controls the Graphics clock source. This bit reflects the value sampled on MD[18] pin and controls the Host/CPU clock source as follows: setting to '0': External. HCLK pin is an input, setting to '1': Internal. HCLK pin is an output and is connected to the internal frequency synthesizer output. This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows: Setting to '0', the PCI clock output = HCLK / 3 Setting to '1', the PCI clock output = HCLK / 2. Reserved. Bit 2 MD18 Bit 1 MD17 Bit 0 Rsv 32/69 Issue 2.4 - February 11, 2002 STRAP OPTION 3.1.4. STRAP REGISTER 3 Bits 7-0 of this register reflect the status of pins MD[47:40] respectively. Strap3 7 Rsv 6 5 MD45 Access = 0022h/0023h 4 MD44 3 MD43 2 MD42 1 MD41 Regoffset = 03Ch 0 MD40 This register defaults to the values sampled on MD[47:40] pins after reset Bit Number Sampled Bits 7-6 Mnemonic Rsv Description Reserved. UART2 internal or external. This bit reflects the value sampled on MD[45] pin and controls the UART2 I/F as follows: Setting to '0', UART2 is external. Setting to '1', UART2 is internal. UART1 internal or external and additional TFT outputs. This bit reflects the value sampled on MD[44] pin and controls the UART1 I/F and the additional TFT I/F as follows: Setting to '0', UART1 is external and an additional 6 TFT outputs (lowest bits - 2 red, 2 green and 2 blue) are enabled. Setting to '1', UART1 is internal. Parallel Port internal or external. This bit reflects the value sampled on MD[43] pin and controls the Parallel Port I/F as follows: Setting to '0', the Parallel Port is external. Setting to '1', the Parallel Port is internal. KB/Mouse internal or external. This bit reflects the value sampled on MD[42] pin and controls the KB/Mouse controller I/F as follows: Setting to '0', the KB/Mouse controller is external. Setting to '1', the KB/Mouse controller is internal. Local Bus I/F or ISA I/F. This bit reflects the value sampled on MD[41] pin and sets whether the Local Bus I/F or the ISA I/F is available at the device I/F as follows: Setting to '0', selects the ISA I/F. Setting to '1', selects the Local Bus I/F. PCMCIA I/F or PCI I/F. This bit reflects the value sampled on MD[40] pin and sets whether the PCMCIA I/F or the PCI I/F is available at the device I/F as follows: Setting to '0', selects the PCI I/F. Setting to '1', selects the PCMCIA I/F. Bit 5 MD45 Bit 4 MD44 Bit 3 MD43 Bit 2 MD42 Bit 1 MD41 Bit 0 MD40 Issue 2.4 - February 11, 2002 33/69 STRAP OPTION 3.1.5. STRAP REGISTER 4 Bits 5-0 of this register reflect the status of pins MD[53:48] respectively. Strap4 7 6 Rsv 5 Access = 0022h/0023h 4 MD52 3 MD51 2 MD50 1 MD49 Regoffset = 03Dh 0 MD48 This register defaults to the values sampled on MD[53:48] pins after reset Bit Number Sampled Bits 7-5 Mnemonic Rsv Description Reserved. y.y V present on board. This bit reflects the value sampled on MD[52] pin and is used to notify the Cardbus socket management unit if the y.y V vcc voltage (where y.y is less than x.x) is present on board as follows Setting to '0', y.y V Vcc voltage is not available. Setting to '1': y.y V Vcc voltage is available. x.x V present on board. This bit reflects the value sampled on MD[51] pin and is used to notify the Cardbus socket management unit if the x.x V vcc voltage (where x.x is less than 3.3) is present on board as follows: Setting to '0', x.x V Vcc voltage is not available. Setting to '1': x.x V Vcc voltage is available. 3.3 V present on board. This bit reflects the value sampled on MD[50] pin and is used to notify the Cardbus socket management unit if the 3.3 V vcc voltage is present on board as follows: Setting to '0', 3.3 V vcc voltage is not available. Setting to '1', 3.3 V vcc voltage is available. 5 V present on board. This bit reflects the value sampled on MD[49] pin and is used to notify the Cardbus socket management unit if the 5 V vcc voltage is present on board as follows: Setting to '0', 5 V vcc voltage is not available. Setting to '1', 5 V vcc voltage is available. This bit reflects the value sampled on MD[48] pin and is used to enable the TFT controller outputs. Bit 4 MD52 Bit 3 MD51 Bit 2 MD50 Bit 1 MD49 Bit 0 MD48 34/69 Issue 2.4 - February 11, 2002 STRAP OPTION 3.1.6. HCLK PLL STRAP REGISTER 0 Bits 5-0 of this register reflect the status of pins MD[26:21] respectively. HCLK_Strap0 7 Rsv 6 5 MD26 Access = 0022h/0023h 4 MD25 3 MD24 2 Rsv 1 Regoffset = 05Fh 0 Rsv This register defaults to the values sampled on pins described below after reset Bit Number Sampled Bits 7-6 Mnemonic Rsv Description Reserved. These pins reflect the value sampled on MD[26:24] pins respectively and control the Host clock Frequency synthesizer: 000 001 010 011 100 101 110 111 25 33 40 50 60 66 75 80 MHz MHz MHz MHz MHz MHz MHz MHz Bits 5-3 MD[26:24] Bits 2-0 Rsv Reserved. Issue 2.4 - February 11, 2002 35/69 STRAP OPTION 36/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS 4 ELECTRICAL SPECIFICATIONS 4.1 INTRODUCTION The electrical specifications in this chapter are valid for the STPC Industrial. 4.2 ELECTRICAL CONNECTIONS 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Industrial, it is necessary to install and test this device using standard high frequency techniques. The high clock frequencies used in the STPC Industrial and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VSS and VDD pins. 4.2.2 Unused Input Pins All inputs not used by the designer and not listed in the table of pin connections in Section 2 should be connected either to VDD or to VSS. Connect active-high inputs to VDD through a 20 k (10%) pull-down resistor and active-low inputs to Table 4-1. Absolute Maximum Ratings Symbol VDDx VI, VO V5T VESD TSTG TOPER PTOT Parameter DC Supply Voltage Digital Input and Output Voltage 5Volt Tolerance ESD Capacity (Human body mode) Storage Temperature Operating Temperature Maximum Power Dissipation Minimum -0.3 -0.3 2.5 -40 -40 Maximum 4.0 VDD + 0.3 5.5 1500 +150 +115 4.8 Units V V V V C C W VSS and connect active-low inputs to VCC through a 20 k (10%) pull-up resistor to prevent spurious operation. 4.2.3 Reserved Designated Pins Pins designated reserved should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 ABSOLUTE MAXIMUM RATINGS The following table lists the absolute maximum ratings for the STPC Industrial device. Stresses beyond those listed under Table 4-1 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those specified in section "Operating Conditions". Exposure to conditions beyond those outlined in Table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 4-1) may also result in reduced useful life and reliability. Issue 2.4 - February 11, 2002 37/69 ELECTRICAL SPECIFICATIONS 4.3.1 5V Tolerance The STPC is capable of running with I/O systems that operate at 5V such as PCI and ISA devices. Certain pins of the STPC tolerate inputs up to 4.4 DC CHARACTERISTICS Table 4-2. DC Characteristics Recommended Operating conditions: VDD = 3.3V 0.3V, Tcase = 0 to 100C unless otherwise specified Symbol VDD PDD HCLK VDAC VOL VOH VILD VIHD ILK CIN COUT CCLK Parameter Operating Voltage Supply Power Internal Clock DAC Voltage Reference Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Output Capacitance Clock Capacitance Test conditions VDD = 3.3V, HCLK = 66Mhz (Note 1) 1.215 I Load =1.5 to 8mA depending of the pin ILoad =-0.5 to -8mA depending of the pin Except XTALI XTALI Except XTALI XTALI Input, I/O (Note 2) (Note 2) (Note 2) 2.4 -0.3 -0.3 2.1 2.35 -5 Min 3.0 Typ 3.3 3.2 1.235 Unit V W MHz V V V 0.8 V 0.5 V VDD+0.3 V VDD+0.3 V 5 A pF pF pF Max 3.6 3.9 80 1.255 0.5 5.5V. Above this limit the component is likely to sustain permanent damage. All the pin that are V5T have been denoted with a * besides the Signal Name in Table 2-1 . Notes: 1. MHz ratings refer to CPU clock frequency. 2. Not yet released. Table 4-3. RAMDAC DC Specification Symbol Vref INL DNL FS FSR LSB Zero Compare Parameter Voltage Reference Integrated Non Linear Error Differentiated Non Linear Error Full Scale Full Scale Range Least Significant Byte Size Zero Scale @ 7.5IRE Mode DAC to DAC matching Min 1.00V 14.00 mA 54uA 0.95mA Nom 1.12V 16.50mA 63uA 1.44mA Max 1.24V 2 lsb 1lsb 20mA 19.00 mA 72uA 1.90mA +/- 5% 38/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS 4.5 AC CHARACTERISTICS Table 4-5 through Table 4-22 list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1. The rising clock edge reference level VREF, and other reference levels are shown in Table 4-4 below for the STPC Industrial. Input or output signals must cross these levels during testing. Figure 4-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. Table 4-4. Drive Level and Measurement Points for Switching Characteristics Symbol VREF VIHD VILD Value 1.5 3.0 0.0 Units V V V Note: Refer to Figure 4-1. Figure 4-1. Drive Level and Measurement Points for Switching Characteristics Tx VIHD CLK: A B MIN VRef Valid Output n+1 MAX VRef VILD OUTPUTS: Valid Output n C D VIHD Valid Input INPUTS: VRef VILD LEGEND: A B C D - Maximum Output Delay Specification - Minimum Output Delay Specification - Minimum Input Setup Specification - Minimum Input Hold Specification Issue 2.4 - February 11, 2002 39/69 ELECTRICAL SPECIFICATIONS 4.5.1 POWER ON SEQUENCE 3.3V Supply 14M H z > 10 us SY S R S TI# 1.6V Strap O ptions V ALID C O N F IG U R A TIO N H C LK PC I_C LK SY S R S TO # 2.3 m s FR A M E # SYSRSTI# has no constraint on its rising time but needs to be set to high at least 10s after power supply is stable. Strap Options are continuously sampled during SYSRSTI# low and should be stable. Once SYSRSTI# is high, they MUST NOT CHANGE until SYSRSTO# is high. 40/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS 4.5.2 PCI AC Timing characteristics Table 4-5. PCI Bus AC Timing Name t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 Parameter PCI_CLKI to AD[31:0] valid PCI_CLKI to FRAME# valid PCI_CLKI to CBE#[3:0] valid PCI_CLKI to PAR valid PCI_CLKI to TRDY# valid PCI_CLKI to IRDY# valid PCI_CLKI to STOP# valid PCI_CLKI to DEVSEL# valid PCI_CLKI to PCI_GNT# valid AD[31:0] bus setup to PCI_CLKI AD[31:0] bus hold from PCI_CLKI PCI_REQ#[2:0] setup to PCI_CLKI PCI_REQ#[2:0] hold from PCI_CLKI CBE#[3:0] setup to PCI_CLKI CBE#[3:0] hold to PCI_CLKI IRDY# setup to PCI_CLKI IRDY# hold to PCI_CLKI FRAME# setup to PCI_CLKI FRAME# hold from PCI_CLKI Min 2 2 2 2 2 2 2 2 2 7 3 10 1 7 5 7 4 7 3 Max 13 11 12 12 13 11 14 11 14 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4.5.3 DRAM CONTROLLER AC TIMING CHARACTERISTICS Figure 4-2 EDO Write Mode (ref table Table 4-6) tCRAS CLK tCMA tCCAS tRC tWCR tCSH tRAS tDHR tAR tRP tWRP tCRP RAS# tCPN tCWL tDS tWRH tWCS CAS# MA MWE# MD Valid data Row Column Row tWCH tCAH tCPN tRCD tRAH tRAD tRWL tRAL tCRW tWCH Issue 2.4 - February 11, 2002 41/69 ELECTRICAL SPECIFICATIONS Figure 4-3 Memory Early Write Mode (ref table Table 4-6) tCRAS tCMA CLK tRC tDHR tWCR tCHR tRAS tRCD tRAH tRAL tRWL tCRP RAS# tCPN tCWL tRCS tWCS tWRH tCHR tDS CAS# MA MWE# MD Data Valid ROW Column tRAD tCRW tRP tCCAS tWCH tCPN tCAH tRCH Figure 4-4 EDO Read Mode (ref table Table 4-6) tCRAS tCMA CLK tRC tRAH tCCAS tCMWE tCMD tRP tCRP RAS# tCPN tRAD tCHR tRAS tAR tCSR tRCD tRAL tRCH tCOH tRCS CAS# MA MWE# MD OPEN Valid data OPEN Row Column Row tCAH tCPN 42/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS Figure 4-5 Fast Page Mode Read (ref table Table 4-6) tCRAS tCMA tCCAS CLK tCRP tRAH tRAD tAR tCSH tRCD RAS# tCMD tCCAS tCMA tCCAS tCMA tCRAS tCMD tCMD tRAL tCRP tRP tCPN tCPN CAS# MA MWE# MD Dout 1 Dout 2 Dout N ROW Column 1 Column 2 Column N tCAH tCOH tCPN tCOH tCAH tCOH tCAH Figure 4-6 Fast Page Mode Write (ref table Table 4-6) tCRAS tCMA CLK tRAH tRAD tWCR tRAS tAR tCRP tDHR tCSH tRCD RAS# tWCS tDS tRC tCPN CAS# MA MWE# OE MD Dout 1 Dout 2 Dout N ROW Column 1 Column 2 Column N tCAH tCWL tCPN tDS tCAH tRWL tRAL tCRW tCRP tRP tCMD tCCAS tCPN tRAL tCAH tDS tRCH Issue 2.4 - February 11, 2002 43/69 ELECTRICAL SPECIFICATIONS Figure 4-7 Refresh Cycle (ref table Table 4-6) tCCAS tCRAS CLK MA[11:0] tRP tRPC RAS#[3:0] tCPN CAS#[7:0] tCPN tCSR tCRS tRAS tCHR tRPC tRP tCSR Table 4-6. AC Memory Timing Characteristics tCRAS tCCAS tCMA tCMWE tCMD tGCMD tMDG tCAH tCHR tCOH tCPN tCRP tCRW tCSR tDS tRAH tRAS tRC tRCD Note 1; TCycle Parameter HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3) HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3) HCLK (or GCLK2X) to MA[11:0] bus valid (see Note 3) HCLK (or GCLK2X) to MWE# valid (see Note 3) HCLK to MD[63:0] bus valid (see Note 3) GCLK2X to MD[63:0] bus valid (see Note 3) MD[63:0] Generic hold Column Address Hold Time CAS Hold Time Data Hold TIme from CAS Low CAS Precharge Time CAS to RAS Precharge Time CAS Low to RAS HIGH (Write only) CAS Setup Time Data In Setup Time Row Address Hold Time RAS Pulse Width Random Read or Write Time Cycle RAS to CAS Delay Time x nCAS + (tData off - tCAS out) Min Max 17 17 17 17 25 23 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 1TCycles 1TCycles Note 1 1TCycles 1TCycles 1TCycles 1TCycles 1TCycles 3TCycles 6TCycles 1TCycles 1TCycles Where T Cycle is the number of clock cycles. nCAS is the number of CAS Cycles (see Section 6.7.) TDataoff is the Generic Datahold tCAS Out the CLK (either HCLK or GCLK2X) to CAS Low. TDataoff and tCAS Out are used to refine the timing programming. Note 2; Value to be derived from CAS pulse width which is programmable (see Section 6.7.). Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X 44/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS Table 4-6. AC Memory Timing Characteristics tRCH tRCS tRP tWCH tWCS tWRH tWRP tAR tRAD tRAL tWCR tRWL tCWL tDHR tRPC tCRS tCHR tCSH Note 1; TCycle Parameter Read Command Hold Time Read Command Setup Time RAS Precharge Time Write Command Hold Time WE Command Setup Time WE Hold Time WE Setup Time Column Address Hold Time from RAS RAS to valid Column Address Delay Column Address to RAS Setup Time Write Command Hold Reference to RAS Write Command to RAS Setup Time (Note 2) Write Command to CAS Setup Time (Note 2) Data Hold Reference to RAS RAS High to CAS Low Precharge CAS Before RAS Setup Time CAS Before RAS Hold Time CAS Hold Time after RAS x nCAS + (tData off - tCAS out) Min 1TCycles 1TCycles 2TCycles 1TCycles 1TCycles Note 2 1TCycles 1TCycles 1TCycles 2TCycles 1TCycles 1TCycles 1TCycles 3TCycles 1TCycles 1TCycles 1TCycles 1TCycles Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Where T Cycle is the number of clock cycles. nCAS is the number of CAS Cycles (see Section 6.7.) TDataoff is the Generic Datahold tCAS Out the CLK (either HCLK or GCLK2X) to CAS Low. TDataoff and tCAS Out are used to refine the timing programming. Note 2; Value to be derived from CAS pulse width which is programmable (see Section 6.7.). Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X Table 4-7. Graphics Adapter (VGA) AC Timing Name t18 t19 Parameter DCLK to VSYNC valid DCLK to HSYNC valid Min Max 27 27 Unit ns ns Issue 2.4 - February 11, 2002 45/69 ELECTRICAL SPECIFICATIONS 4.5.4 ISA INTERFACE AC TIMING CHARACTERISTICS Figure 4-8 ISA Cycle (ref table Table 4-8) 2 15 38 37 14 13 12 9 18 ALE 22 AEN Valid AENx 34 33 3 LA [23:17] Valid Address 42 11 24 41 10 SA [19:0] Valid Address, SBHE* 26 23 55 48 47 61 CONTROL (Note 1) IOCS16# MCS16# 54 IOCHRDY READ DATA WRITE DATA VALID DATA V.Data 64 58 59 28 57 27 25 56 29 Note 1; Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#. Note; The clock has not been represented as it cannot be accurately represented depending on the ISA Slave mode. Table 4-8. ISA Bus AC Timing Parameter LA[23:17] valid before ALE# negated LA[23:17] valid before MEMR#, MEMW# asserted 3a Memory access to 16 bit ISA Slave 3b Memory access to 8 bit ISA Slave 9 SA[19:0] & SBHE valid before ALE# negated 10 SA[19:0] & SBHE valid before MEMR#, MEMW# asserted 10a Memory access to 16 bit ISA Slave 10b Memory access to 8 bit ISA Slave 10 SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted 10c Memory access to 16 bit ISA Slave 10d Memory access to 8 bit ISA Slave 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 11 XTALO to IOW# valid Note; The signal numbering refers to Table 4-8 Name 2 3 Min 5T 5T 5T 1T 2T 2T 2T 2T 2T Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycle Cycle Cycles 46/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Parameter Min 11a Memory access to 16 bit ISA Slave - 2BCLK 2T 11b Memory access to 16 bit ISA Slave - Standard 3BCLK 2T 11c Memory access to 16 bit ISA Slave - 4BCLK 2T 11d Memory access to 8 bit ISA Slave - 2BCLK 2T 11e Memory access to 8 bit ISA Slave - Standard 3BCLK 2T 12 ALE# asserted before ALE# negated 1T 13 ALE# asserted before MEMR#, MEMW# asserted 13a Memory Access to 16 bit ISA Slave 2T 13b Memory Access to 8 bit ISA Slave 2T 13 ALE# asserted before SMEMR#, SMEMW# asserted 13c Memory Access to 16 bit ISA Slave 2T 13d Memory Access to 8 bit ISA Slave 2T 13e ALE# asserted before IOR#, IOW# asserted 2T 14 ALE# asserted before AL[23:17] 14a Non compressed 15T 14b Compressed 15T 15 ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated 15a Memory Access to 16 bit ISA Slave- 4 BCLK 11T 15e Memory Access to 8 bit ISA Slave- Standard Cycle 11T 18a ALE# negated before LA[23:17] invalid (non compressed) 14T 18a ALE# negated before LA[23:17] invalid (compressed) 14T 22 MEMR#, MEMW# asserted before LA[23:17] 22a Memory access to 16 bit ISA Slave. 13T 22b Memory access to 8 bit ISA Slave. 13T 23 MEMR#, MEMW# asserted before MEMR#, MEMW# negated 23b Memory access to 16 bit ISA Slave Standard cycle 9T 23e Memory access to 8 bit ISA Slave Standard cycle 9T 23 SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated 23h Memory access to 16 bit ISA Slave Standard cycle 9T 23l Memory access to 16 bit ISA Slave Standard cycle 9T 23 IOR#, IOW# asserted before IOR#, IOW# negated 23o Memory access to 16 bit ISA Slave Standard cycle 9T 23r Memory access to 8 bit ISA Slave Standard cycle 9T 24 MEMR#, MEMW# asserted before SA[19:0] 24b Memory access to 16 bit ISA Slave Standard cycle 10T 24d Memory access to 8 bit ISA Slave - 3BLCK 10T 24e Memory access to 8 bit ISA Slave Standard cycle 10T 24f Memory access to 8 bit ISA Slave - 7BCLK 10T 24 SMEMR#, SMEMW# asserted before SA[19:0] 24h Memory access to 16 bit ISA Slave Standard cycle 10T 24i Memory access to 16 bit ISA Slave - 4BCLK 10T 24k Memory access to 8 bit ISA Slave - 3BCLK 10T 24l Memory access to 8 bit ISA Slave Standard cycle 10T 24 IOR#, IOW# asserted before SA[19:0] 24o I/O access to 16 bit ISA Slave Standard cycle 19T 24r I/O access to 16 bit ISA Slave Standard cycle 19T Note; The signal numbering refers to Table 4-8 Name Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Issue 2.4 - February 11, 2002 47/69 ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Parameter Min MEMR#, MEMW# asserted before next ALE# asserted 25b Memory access to 16 bit ISA Slave Standard cycle 10T 25d Memory access to 8 bit ISA Slave Standard cycle 10T 25 SMEMR#, SMEMW# asserted before next ALE# asserted 25e Memory access to 16 bit ISA Slave - 2BCLK 10T 25f Memory access to 16 bit ISA Slave Standard cycle 10T 25h Memory access to 8 bit ISA Slave Standard cycle 10T 25 IOR#, IOW# asserted before next ALE# asserted 25i I/O access to 16 bit ISA Slave Standard cycle 10T 25k I/O access to 16 bit ISA Slave Standard cycle 10T 26 MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted 26b Memory access to 16 bit ISA Slave Standard cycle 12T 26d Memory access to 8 bit ISA Slave Standard cycle 12T 26 SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted 26f Memory access to 16 bit ISA Slave Standard cycle 12T 26h Memory access to 8 bit ISA Slave Standard cycle 12T 26 IOR#, IOW# asserted before next IOR#, IOW# asserted 26i I/O access to 16 bit ISA Slave Standard cycle 12T 26k I/O access to 8 bit ISA Slave Standard cycle 12T 28 Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted 28a Memory access to 16 bit ISA Slave 3T 28b Memory access to 8 bit ISA Slave 3T 28 Any command negated to IOR#, IOW# asserted 28c I/O access to ISA Slave 3T 29a MEMR#, MEMW# negated before next ALE# asserted 1T 29b SMEMR#, SMEMW# negated before next ALE# asserted 1T 29c IOR#, IOW# negated before next ALE# asserted 1T 33 LA[23:17] valid to IOCHRDY negated 33a Memory access to 16 bit ISA Slave - 4 BCLK 8T 33b Memory access to 8 bit ISA Slave - 7 BCLK 14T 34 LA[23:17] valid to read data valid 34b Memory access to 16 bit ISA Slave Standard cycle 8T 34e Memory access to 8 bit ISA Slave Standard cycle 14T 37 ALE# asserted to IOCHRDY# negated 37a Memory access to 16 bit ISA Slave - 4 BCLK 6T 37b Memory access to 8 bit ISA Slave - 7 BCLK 12T 37c I/O access to 16 bit ISA Slave - 4 BCLK 6T 37d I/O access to 8 bit ISA Slave - 7 BCLK 12T 38 ALE# asserted to read data valid 38b Memory access to 16 bit ISA Slave Standard Cycle 4T 38e Memory access to 8 bit ISA Slave Standard Cycle 10T 38h I/O access to 16 bit ISA Slave Standard Cycle 4T 38l I/O access to 8 bit ISA Slave Standard Cycle 10T 41 SA[19:0] SBHE valid to IOCHRDY negated 41a Memory access to 16 bit ISA Slave 6T 41b Memory access to 8 bit ISA Slave 12T Note; The signal numbering refers to Table 4-8 Name 25 Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles 48/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Parameter Min Max 41c I/O access to 16 bit ISA Slave 6T 41d I/O access to 8 bit ISA Slave 12T 42 SA[19:0] SBHE valid to read data valid 42b Memory access to 16 bit ISA Slave Standard cycle 4T 42e Memory access to 8 bit ISA Slave Standard cycle 10T 42h I/O access to 16 bit ISA Slave Standard cycle 4T 42l I/O access to 8 bit ISA Slave Standard cycle 10T 47 MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated 47a Memory access to 16 bit ISA Slave 2T 47b Memory access to 8 bit ISA Slave 5T 47c I/O access to 16 bit ISA Slave 2T 47d I/O access to 8 bit ISA Slave 5T 48 MEMR#, SMEMR#, IOR# asserted to read data valid 48b Memory access to 16 bit ISA Slave Standard Cycle 2T 48e Memory access to 8 bit ISA Slave Standard Cycle 5T 48h I/O access to 16 bit ISA Slave Standard Cycle 2T 48l I/O access to 8 bit ISA Slave Standard Cycle 5T 54 IOCHRDY asserted to read data valid 54a Memory access to 16 bit ISA Slave 1T(R)/2T(W) 54b Memory access to 8 bit ISA Slave 1T(R)/2T(W) 54c I/O access to 16 bit ISA Slave 1T(R)/2T(W) 54d I/O access to 8 bit ISA Slave 1T(R)/2T(W) IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, 55a 1T SMEMW#, IOR#, IOW# negated 55b IOCHRY asserted to MEMR#, SMEMR# negated (refresh) 1T 56 IOCHRDY asserted to next ALE# asserted 2T 57 IOCHRDY asserted to SA[19:0], SBHE invalid 2T 58 MEMR#, IOR#, SMEMR# negated to read data invalid 0T 59 MEMR#, IOR#, SMEMR# negated to databus float 0T 61 Write data before MEMW# asserted 61a Memory access to 16 bit ISA Slave 2T Memory access to 8 bit ISA Slave (Byte copy at end of 61b 2T start) 61 Write data before SMEMW# asserted 61c Memory access to 16 bit ISA Slave 2T 61d Memory access to 8 bit ISA Slave 2T 61 Write Data valid before IOW# asserted 61e I/O access to 16 bit ISA Slave 2T 61f I/O access to 8 bit ISA Slave 2T 64a MEMW# negated to write data invalid - 16 bit 1T 64b MEMW# negated to write data invalid - 8 bit 1T 64c SMEMW# negated to write data invalid - 16 bit 1T 64d SMEMW# negated to write data invalid - 8 bit 1T 64e IOW# negated to write data invalid 1T Note; The signal numbering refers to Table 4-8 Name Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Issue 2.4 - February 11, 2002 49/69 ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Parameter MEMW# negated to copy data float, 8 bit ISA Slave, odd Byte 64f by ISA Master IOW# negated to copy data float, 8 bit ISA Slave, odd Byte by 64g ISA Master Note; The signal numbering refers to Table 4-8 Name Min 1T 1T Max Units Cycles Cycles 4.5.5 IPC INTERFACE AC TIMING CHARACTERISTICS Table 4-9. IPC Interface AC Timings Name t20 t21 t22 t23 Parameter XTALO to DACK_EN[2:0] valid XTALO to TC valid IRQ_MUX Input setup to ISACLK2X DREQ_MUX[1:0] Input setup to ISACLK2X Min Max 71 68 Unit nS nS nS nS 0 0 4.5.6 PCMCIA INTERFACE AC TIMING CHARACTERISTICS Table 4-10. PCMCIA Interface AC Timing Name t24 t25 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 Parameters Input setup to ISACLK2X Input hold from ISACLK2X ISACLK2X to IORD ISACLK2X to IORW ISACLK2X to AD[25:0] ISACLK2X to OE# ISACLK2X to WE# ISACLK2X to DATA[15:0] ISACLK2X to INPACK ISACLK2X to CE1# ISACLK2X to CE2# ISACLK2X to RESET Min 24 5 2 2 0 2 7 7 2 Max Units nS nS nS nS nS nS nS nS nS nS nS nS 55 55 25 55 55 35 55 65 65 55 4.5.7 PARALLEL INTERFACE AC TIMING CHARACTERISTICS Table 4-11. Parallel Interface AC Timing Name t37 t38 t39 Parameters STROBE# to BUSY setup PD bus to AUTPFD# hold PB bus to BUSY setup Min 0 0 0 Max Units nS nS nS 50/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS 4.5.8 KEYBOARD INTERFACE AC TIMING CHARACTERISTICS Table 4-12. Keyboard Interface AC Timing Name t40 t41 t42 Parameters Input setup to KBCLK Input hold to KBCLK KBCLK to KBDATA Min 5 1 Max 12 Units nS nS nS 4.5.9 MOUSE INTERFACE AC TIMING CHARACTERISTICS Table 4-13. Mouse Interface AC Timing Name t43 t44 t45 Parameters Input setup to MCLK Input hold to MCLK MCLK to MDATA Min 5 1 Max 12 Units nS nS nS Issue 2.4 - February 11, 2002 51/69 ELECTRICAL SPECIFICATIONS 4.5.10 LOCAL BUS INTERFACE AC TIMING CHARACTERISTICS Table 4-14. 16 bit Memory Write t58 HCLK PA PD Setup* IOCS#[3:0] t52 t53 t51 t50 @ Data Hold* Active* PWR#0 PWR#1 PRD#0 PRD#1 Table 4-15. 16 bit Memory Read t58 HCLK PA PD Setup* IOCS#[3:0] PWR#0 PWR#1 t54 t55 t51 t50 @ Data Hold* Active* PRD#0 PRD#1 Table 4-16. 16 bit I/O Write t58 HCLK PA PD Setup* IOCS#[3:0] t52 t53 t51 t50 @ Data Hold* Active* PWR#0 PWR#1 PRD#0 PRD#1 52/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS Table 4-17. 16 bit I/O Read t58 HCLK PA PD Setup* IOCS#[3:0] PWR#0 PWR#1 t54 t55 t51 t50 @ Data Hold* Active* PRD#0 PRD#1 Table 4-18. 8 bit I/O Write at even addresses with IOWIDTH=0 or 1 t50 t51 t58 HCLK PA PD[7:0] PD[15:8] Setup* IOCS#[3:0] t52 @ Data Hold* Active* PWR#0 PWR#1 PRD#0 PRD#1 Table 4-19. 8 bit I/O Write at odd addresses with IOWIDTH=0 (8 bit Peripheral) t58 HCLK PA PD[7:0] PD[15:8] Setup* IOCS#[3:0] PWR#0 t53 t50 t51 @ Data Hold* Active* PWR#1 PRD#0 PRD#1 Issue 2.4 - February 11, 2002 53/69 ELECTRICAL SPECIFICATIONS Table 4-20. 8 bit I/O Write at odd addresses with IOWIDTH=1 (16 bit Peripheral) t58 HCLK PA PD[7:0] PD[15:8] Setup* IOCS#[3:0] PWR#0 t53 t50 t51 @ Data Hold* Active* PWR#1 PRD#0 PRD#1 Table 4-21. Local Bus Interface AC Timing Name Parameters Min t46 PRDY# Input hold to HCLK 2 t47 PD[15:0] Input hold to HCLK 2 t48 PRDY# Input setup to HCLK 1 t49 PD[15:0] Input setup to HCLK 2 t50 HCLK to PA bus t51 HCLK to PD bus t52 HCLK to PWR0# t53 HCLK to PWR1# t54 HCLK to PRD0# t55 HCLK to PRD1# t56 HCLK to FCS0# t57 HCLK to FCS1# t58 HCLK to IOCS#[3:0] Note; To program the values of Setup, Active and Hold timings, refer to Section 14.4.3. Max Units nS nS nS nS nS nS nS nS nS nS nS nS nS 4 15 15 15 15 15 15 15 15 15 4.5.11 TFT INTERFACE AC TIMING CHARACTERISTICS Table 4-22. TFT Interface Timing Name t59 t60 t61 t62 t63 t64 t65 t66 t67 t68 t68 t69 Parameters DCLK to FPLINE DCLK to R[2] DCLK to R[3] DCLK to R[4] DCLK to R[5] DCLK to G[2] DCLK to G[3] DCLK to G[4] DCLK to G[5] DCLK to B[2] DCLK to B[3] DCLK to B[4] Min Max 15 15 15 15 15 15 15 15 15 15 15 15 Units nS nS nS nS nS nS nS nS nS nS nS nS 54/69 Issue 2.4 - February 11, 2002 ELECTRICAL SPECIFICATIONS Table 4-22. TFT Interface Timing Name t70 t71 Parameters DCLK to B[5] DCLK to FPFRAME Min Max 15 15 Units nS nS Issue 2.4 - February 11, 2002 55/69 ELECTRICAL SPECIFICATIONS 56/69 Issue 2.4 - February 11, 2002 MECHANICAL DATA 5. MECHANICAL DATA 5.1. 388-PIN PACKAGE DIMENSION The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View Dimensions are shown in Figure 5-2, Table 5-1 and Figure 5-3, Table 5-2. 1 2 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Issue 2.4 - February 11, 2002 57/69 MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A B A E F D Detail CG Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols A B C D E F G Min 34.95 1.22 0.58 1.57 0.15 0.05 0.75 mm Typ 35.00 1.27 0.63 1.62 0.20 0.10 0.80 Max 35.05 1.32 0.68 1.67 0.25 0.15 0.85 Min 1.375 0.048 0.023 0.062 0.006 0.002 0.030 inches Typ 1.378 0.050 0.025 0.064 0.008 0.004 0.032 Max 1.380 0.052 0.027 0.066 0.001 0.006 0.034 58/69 Issue 2.4 - February 11, 2002 MECHANICAL DATA Figure 5-3. 388-pin PBGA Package - Dimensions C F D E Solderball Solderball after collapse B A G Table 5-2. 388-pin PBGA Package - Dimensions Symbols A B C D E F G Min 0.50 1.12 0.60 0.52 0.63 0.60 mm Typ 0.56 1.17 0.76 0.53 0.78 0.63 30.0 Max 0.62 1.22 0.92 0.54 0.93 0.66 Min 0.020 0.044 0.024 0.020 0.025 0.024 inches Typ 0.022 0.046 0.030 0.021 0.031 0.025 11.8 Max 0.024 0.048 0.036 0.022 0.037 0.026 Issue 2.4 - February 11, 2002 59/69 MECHANICAL DATA 5.2. 388-PIN PACKAGE THERMAL DATA The 388-pin PBGA package has a Power Dissipation Capability of 4.5W. This increases to 6W when used with a Heatsink. The structure in shown in Figure 5-4. Thermal dissipation options are illustrated in Figure 5-5 and Figure 5-6. Figure 5-4. 388-Pin PBGA structure Signal layers Power & Ground layers Thermal balls Figure 5-5. Thermal Dissipation Without Heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 6 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 125 The PBGA is centred on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17m for internal layers - 34m for external layers Airflow = 0 Board temperature taken at the centrecentre ba Ambient Rja = 13 C/W 60/69 Issue 2.4 - February 11, 2002 MECHANICAL DATA Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 3 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 50 The PBGA is centred on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17m for internal layers - 34m for external layers Airflow = 0 Board temperature taken at the centre balls Heat sink is 11.1C/W Ambient Rja = 9.5 C/W Issue 2.4 - February 11, 2002 61/69 MECHANICAL DATA 5.3. SOLDERING RECOMMENDATIONS High quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. The heating and cooling rise rates must be compatible with the solder paste and components. A typical profile consists of a preheat, dryout, reflow and cooling sections. The most critical parameter in the preheat section is to minimize the rate of temperature rise to less than 2C / second, in order to minimize thermal shock on the semi-conductor components. Dryout section is used primarily to ensure that the solder paste is fully dried before hitting reflow temperatures. Solder reflow is accomplished in the reflow zone, where the solder paste is elevated to a temperature greater than the melting point of the solder. Melting temperature must be exceeded by approximately 20C to ensure quality reflow. In reality the profile is not a line, but rather a range of temperatures all solder joints must be exposed. The total temperature deviation from component thermal mismatch, oven loading and oven uniformity must be within the band. Figure 5-7. Reflow soldering temperature range Temperature ( C ) 250 200 150 100 50 PREHEAT 0 DRYOUT REFLOW 240 COOLING 0 Time ( s ) 62/69 Issue 2.4 - February 11, 2002 BOARD LAYOUT 6. BOARD LAYOUT 6.1. THERMAL DISSIPATION Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at 3.3 V, it may be beneficial to reduce the voltage to, for example, 3.15 V. This may save a few 100's of mW. A further area to consider is unused interfaces and functions. Depending on the application, some input signals can be grounded, some blocks left un- powered, other blocks shutdown. Clock speed dynamic adjustment offers a further solution, together with the integrated power management unit. The standard way to route the thermal balls to the internal ground layer uses one via for each ball pad, connected using 8-mil wire. With such a configuration, the Plastic BGA 388 package provides 90% of the thermal dissipation through the ground balls, in particular the central thermal balls, as these are directly connected to the die. The remaining 10% of heat is dissipated through the case. Adding a heat sink can reduce this value by 85%. To avoid thermal problems when routing to the STPC, some basic rules must be applied. Firstly, the ground balls must be directly connected to the ground layer, which acts as a heat sink. This is illustrated in Figure 6-1. If one ground layer is not enough, a second ground plane may be added on the solder side. Figure 6-1. Ground Routing Pad for ground ball Thru hole to ground layer To pL aye r: Sig nal Gr s ou nd lay er Po we r la yer Bo tto m La yer : si gn als + lo ca l gr ou nd lay er (if ne ed ed ) Note: For better visibility, ground balls are not all routed. Issue 2.4 - February 11, 2002 63/69 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. BOARD LAYOUT When considering thermal dissipation, the most important - if not the most obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The use of 8-mil wire results in a thermal resistance of 105C/W assuming copper is used (418 W/m.K). This high value is due to the thickness (34 m) of the copper on the external side of the PCB. Considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9C/W. This can be improved by using four 10 mil wires to connect to the four vias around the ground pad link, as in Figure 6-3. This gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.6C/W. The use of a ground plane, as shown in Figure 64, is even better. To avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (NSMD pad). This gives a diameter of 33 mil for a 25 mil ground pad. To obtain the optimum ground layout, place the vias directly under the ball pads. In this case, no local board distortion can be tolerated. The thickness of the copper on PCB layers is typically 34 m for external layers and 17 m for internal layers. The resulting thermal dissipation is not good, with areas of high temperature being concentrated around the devices, falling off quickly with increased distance. Where possible, place a metal layer inside the PCB. This will improve dramatically the spread of heat and hence improve the thermal dissipation of the board.. Figure 6-2. Recommended 1-wire Ground Pad Layout Pad for ground ball (diameter = 25 mil) Solder Mask (4 mil) Connection Wire (width = 10 mil) Via (diameter = 24 mil) il .5 34 m Hole to ground layer (diameter = 12 mil) 1 mil = 0.0254 mm Figure 6-3. Recommended 4-wire Ground Pad Layout 4 via pads for each ground ball 64/69 Issue 2.4 - February 11, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. BOARD LAYOUT Figure 6-4. Optimum Layout for Central Ground Ball Clearance = 6mil External diameter = 37 mil Via to Ground layer hole diameter = 14 mil Solder mask diameter = 33 mil Pad for ground ball diameter = 25 mil connections = 10 mil The PBGA Package also dissipates heat through the peripheral ground balls. When a heat sink is placed on the device, heat is more uniformly spread throughout the moulding, increasing the dissipation of heat through the peripheral ground balls. The higher the number of via pads connected to each ground ball, the higher the amount of heat dissipated. The only limitation is the risk of losing routing channels. Figure 6-1 shows a routing with a good trade off between thermal dissipation and the number of routing channels. A local ground plane on the opposite side of the board, as shown in Figure 6-2, improves thermal dissipation. It is used to connect decoupling capacitors but can also be used for connection to a heat sink or to the system metal box for better dissipation. This possibility of using the whole system box for thermal dissipation can be very useful in cases of high internal temperature and low external temperature. In such cases, both sides of the PBGA should be thermally connected to the metal chassis in order to propagate the heat flow through the metal. Figure 6-3 illustrates a typical example. Issue 2.4 - February 11, 2002 65/69 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. BOARD LAYOUT Figure 6-1. Global Ground Layout for Good Thermal Dissipation Via to ground layer Ground pad Figure 6-2. Bottom Side Layout and Decoupling Ground plane for thermal dissipation Via to ground layer 66/69 Issue 2.4 - February 11, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. BOARD LAYOUT Figure 6-3. Use of Metal Plate for Thermal Dissipation Die Board Metal planes Thermal conductor Issue 2.4 - February 11, 2002 67/69 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. BOARD LAYOUT 6.2. HIGH SPEED SIGNALS As some STPC interfaces (listed below in decreasing speed order) run at high speeds, they must be carefully routed or even shielded. 1) Memory interface. 2) Graphics and video interfaces. 3) PCI bus. Figure 6-5. Shielding Signals 4) 14 MHz oscillator stage. All clock signals must be routed first and shielded for speeds of 27 MHz or higher. All high-speed signals, such as memory control signals and PCI control signals, require the same constraints. All analog noise-sensitive signals should be routed in a separate area and hence can be routed indepedently. ground ring shielded signal line ground pad ground pad shielded signal lines 68/69 Issue 2.4 - February 11, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ORDERING DATA 7 ORDERING DATA 7.1 ORDERING CODES ST STMicroelectronics Prefix Product Family PC: PC Compatible Product ID I01: Industrial Core Speed 66: 66MHz 80: 80MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial Tcase = 0 to +100C I: Industrial Tcase = -40 to +100C Operating Voltage 3 : 3.3V 0.3V PC I01 66 BT C 3 Issue 2.4 - February 11, 2002 69/69 ORDERING DATA 7.2 AVAILABLE PART NUMBERS Part Number STPCI0166BTC3 STPCI0180BTC3 STPCI0166BTI3 STPCI0180BTI3 Core Frequency (MHz) 66 80 66 80 CPU Mode DX DX DX DX Tcase Range (C) 0C to +100C 3.3V 0.3V -40C to +100C Operating Voltage (V) 70/69 Issue 2.4 - February 11, 2002 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 71 Issue 2.4 |
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