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HM62P1321 Series
32768-word x 32-bit Synchronous Fast Static RAM with Burst Counter and Pipelined Data Output
ADE-203-753 (Z) Preliminary Rev.0.0 Mar. 6, 1997 Features
* * * * * * * * * * * * * * 3.3 V core power supply 2.5 V I/O power supply Fast clock access time: 8.0 ns (max) Clock cycle times: 15 ns (min) Address data pipeline capability Internal input registers (Address, Data, Control) Internal data output registers Internal self-timed write cycle ADSP, ADSC and ADV burst control pins (Supports interleaving) Asynchronous output enable controlled three-state outputs Individual byte write control and global write Power down state via ZZ Common data inputs and data outputs High board density 100-lead LQFP package
Ordering Information
Type No. HM62P1321FP-15 Access time 8 ns CPU clock rate 66 MHz Package LQFP 100-pin (FP-100H)
Preliminary:The specification of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specification.
HM62P1321 Series
Pin Arrangement
HM62P1321FP Series
A6 A7 CE1 CE2 BW3 BW2 BW1 BW0 CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
2
NC A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC DQ16 DQ17 VDDQ VSS DQ18 DQ19 DQ20 DQ21 VSS VDDQ DQ22 DQ23 NC VDD NC VSS DQ24 DQ25 VDDQ VSS DQ26 DQ27 DQ28 DQ29 VSS VDDQ DQ30 DQ31 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC DQ15 DQ14 V DDQ V SS DQ13 DQ12 DQ11 DQ10 V SS V DDQ DQ9 DQ8 V SS NC V DD ZZ DQ7 DQ6 V DDQ V SS DQ5 DQ4 DQ3 DQ2 V SS V DDQ DQ1 DQ0 NC
(Top view)
HM62P1321 Series
Pin Description (See Detailed Pin Description)
Pin name A0 to A14 BW0, BW1, BW2, BW3 Type Input Input Function Address inputs Byte write enables BW0 controls DQ0 to DQ7 BW1 controls DQ8 to DQ15 BW2 controls DQ16 to DQ23 BW3 controls DQ24 to DQ31
GW BWE CLK CE1 CE2, CE2 OE ADV ADSP ADSC NC DQ0 to DQ31 VDD VDDQ VSS ZZ
Input Input Input Input Input Input Input Input Input -- Input/Output Supply I/O Supply Supply Input
Global write Byte write enable Clock Enable Chip enable Output enable Address advance Address status processor Address status controller No connection
Power supply I/O power supply Ground Power down (Snooze)
3
HM62P1321 Series
Block Diagram
ADV CLK A0 to A14 ADSC
CLR
15 Address Registers
Binary Counter 15
A0
A0'
A1 13
A1' 15
GW BWE BW0
Byte 0 Write Register
Byte 0 Write Driver
8
BW1
Byte 1 Write Register
Byte 1 Write Driver
8
32K x 8 x 4 Memory Array
BW2
Byte 2 Write Register
Byte 2 Write Driver
8
BW3 CE2 CE2 CE1
Byte 3 Write Register 4 32 4 Enable Delay Register
Byte 3 Write Driver
8
Enable Register
32
Output Registers
OE ADSP Input Registers
32
DQ0 to DQ31 Note: The functional block diagram illustrates simplified device operation. See truth table, detailed pin descriptions and timing diagrams for detailed information.
4
HM62P1321 Series
Synchronous Truth Table
Operation Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down READ cycle, begin burst READ cycle, begin burst WRITE cycle, begin burst READ cycle, begin burst READ cycle, begin burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst WRITE cycle, continue burst WRITE cycle, continue burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst WRITE cycle, suspend burst WRITE cycle, suspend burst Address CE1 CE2 CE2 ADSP ADSC ADV Write OE None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L L L L L L x x H H x H x x H H x H x x H x H L L L L L x x x x x x x x x x x x x L x L x H H H H H x x x x x x x x x x x x x L L H H L L H H H H H x x H x H H x x H x L x x L L x x L L L H H H H H H H H H H H H x x x x x x x x x x L L L L L L H H H H H H x x x x x x x L H H H H H H L L H H H H L L x x x x x L H x L H L H L H x x L H L H x x CLK DQ L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Notes: 1. H means logic HIGH, L means logic LOW. x means H or L. Write = L means any one or more byte write enable signals (BW0, BW1, BW2 or BW3) and BWE are LOW or GW is LOW. Write = H means all byte write enable signals and GW are HIGH. 2. BW0 enables write to Byte0 (DQ0 to DQ7). BW1 enables write to Byte1 (DQ8 to DQ15). BW2 enables write to Byte2 (DQ16 to DQ23). BW3 enables write to Byte3 (DQ24 to DQ31). 3. All inputs except OE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Wait states are inserted by suspending burst. 5. For a write operation following a read operation, OE must be HIGH before the input data required setup time and hold HIGH throughout the input data hold time. 6. ADSP = LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent LH edge of CLK. Refer to WRITE timing diagram for clarification.
5
HM62P1321 Series
Asynchronous Truth Table
Operation Read Read Write Deselect Power down (Snooze) ZZ L L L L H OE L H x x x I/O status Data out High-Z High-Z, Data in High-Z HIgh-Z
Note: H means logic HIGH. L means logic LOW. x means H or L.
Partial Truth Table for Writes
Operation Read Read Write byte 0 Write all bytes Write all bytes GW H H H H L BWE H x L L x BW0 x H L L x BW1 x H H L x BW2 x H H L x BW3 x H H L x
Note: H means logic HIGH. L means logic LOW. x means H or L.
Interleave Sequence Table
Parameter External address 1st internal address 2nd internal address 3rd internal address A14 to A2 A14 to A2 A14 to A2 A14 to A2 A14 to A2 Sequence 1 (A1, A0) 00 01 10 11 Sequence 2 (A1, A0) 01 00 11 10 Sequence 3 (A1, A0) 10 11 00 01 Sequence 4 (A1, A0) 11 10 01 00
Note: Each Sequence wraps around to its initial state upon completion.
6
HM62P1321 Series
Absolute Maximum Ratings
Parameter Core Supply voltage I/O supply voltage Voltage on any pins relative to VSS (Except VDD) Power dissipation Operating temperature Storage temperature range (with bias) Storage temperature range Symbol VDD VDDQ VT PT Topr Tstg (bias) Tstg Value -0.5 to +4.6 -0.5 to VDD -0.5 to VDD +0.5 1.2 0 to +70 -10 to +85 -55 to +125 Unit V V V W C C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Core Supply voltage (Operating voltage range) I/O Supply voltage (Operating voltage range) Supply voltage to VSS Input high voltage Input low voltage Symbol VDD VDDQ VSS VIH VIL Min 3.135 2.375 0.0 1.7 -0.3 Max 3.465 2.900 0.0 Unit V V V 1 2 Notes
VDDQ +0.3 V 0.7 V
Notes: 1. VDDQ + 1.9 V for overshoot pulse width tCYC min/2. 2. -1.9 V for undershoot pulse width tCYC min/2.
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HM62P1321 Series
DC Characteristics (Ta = 0 to +70C, VDD = 3.3 V 5 %, V DDQ = 2.375 V to 2.9V, unless otherwise noted.)
Parameter Input leakage current Output leakage current Supply current Symbol ILI ILO IDD Min -2 -2 -- Max 2 2 140 Unit A A mA Test conditions All inputs Vin = VSS to VDDQ OE = VIH, Vout = V SS to VDDQ Device selected Iout = 0 mA, all inputs = V IH or VIL, Cycle time = t CYC min. VDD = Max Device deselected lout = 0 mA, all inputs = fixed and all inputs VDDQ - 0.2 V or 0.2 V, Cycle time = t CYC min. Device deselected, Output disabled all inputs = fixed and all inputs VDDQ - 0.2 V or 0.2 V, VDD = Max, Cycle time = (Frequency = 0 MHz) ZZ VDDQ - 0.2 V IOL = 1 mA IOH = -1 mA
Standby current
ISB
--
30
mA
ISB1
--
5
mA
ISBzz Output low voltage Output high voltage VOL VOH
-- -- 2.0
5 0.4 --
mA V V
Capacitance (Ta = 25C, f = 1.0 MHz, VDD = 3.3 V, VDDQ = 2.5 V)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min 2 4 Typ 4 7 Max 5 8 Unit pF pF Note 1 1
1. This parameter is sampled and not 100% tested.
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HM62P1321 Series
AC Characteristics (Ta = 0 to +70C, VDD = 3.3 V 5 %, VDDQ = 2.375 V to 2.9V, unless otherwise noted.)
Test Conditions * * * * * Input timing measurement reference level: V DDQ / 2 Input pulse levels: 0 V to V DDQ Input rise and fall edge rate: 1.5ns (20 % to 80 %) Output timing reference level: VDDQ / 2 Output load: See figure A unless otherwise noted
Z o = 50 Output RL = 50 30 pF ** Output
50 V DDQ /2 5 pF *
V L= VDDQ /2 Figure A **(including the capacitance of tester and jig) Figure B *(including SCOPE and jig)
9
HM62P1321 Series
Symbol Parameter Cycle time Clock access time Output enable to output valid Clock high to output active Clock high to output change Output enable to output active Output disable to Q High-Z Clock high to Q High-Z Clock high pulse width Clock low pulse width Setup Times: Address Address Status Input Data Write Address Advance Chip Enable Hold Times: Address Address Status Input Data Write Address Advance Chip Enable ZZ standby ZZ Recovery Standard tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQZ tGHQZ tKHQZ tKHKL tKLKH tAVKH tADSVKH tDVKH tWVKH tADVVK tEVKH tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX Alternate tCYC tACK tOE tCLZ tCOH tOLZ tOHZ tCHZ tCH tCL tSA tSADS tSD tSW tSADV tSCE 0.5 tHA tHADS tHD tHW tHADV tHCE tzzs tzzrec 6.0 6.0 -- -- ns ns 5, 6 5 -- ns 2, 3 HM62P1321-15 Min 15 -- -- 1.5 2.0 0 -- -- 5.0 5.0 2.5 Max -- 8.0 5.0 -- -- -- 6.0 6.0 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 2, 3 1 1 4 Notes
Notes: 1. Transition is measured 200mV from steady-state voltage with load of FigureB. This parameter is sampled. 2. A READ cycle is defined by byte write enables all HIGH or ADSP LOW for the required setup and hold times. A WRITE cycle is defined by at least one byte write enable LOW and ADSP HIGH for the required setup and hold times. 3. This is a synchronous device. All address must meet the specified setup and hold times for all rising edges of CLK when either ADSP or ADSC is LOW and chip enabled. All other Synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when chip is enabled. Chip enable must be valid at each rising edge of CLK (when either ADSP or ADSC is LOW) to remain enabled. 4. OE is a " H or L " when a byte write enable is sampled LOW. 5. During the cycle when transition of ZZ from high to low or from low to high occurs, ADSP,ADSC,BWE,GW Bwi must be high at its rising edge of CLK. 6. Data-output is not guaranteed during the cycle when transition of ZZ from low to high occurs.
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HM62P1321 Series
Timing Waveforms
0*
" , $ + , ' & 0
. & ' !
Example of Read Timing
tCYC CLK ADSP t CH t CL t SADS t HADS ADSC t SADS t HADS t SA t HA A1 Address A2 BW0 to BW3 BWE, GW CE1 t SW t HW A3 Burst continues with new base address t SCE t HCE
Deselect cycle *3 *2
, , , , ,,,, ,, , , , ,, ,
t SADV t HADV ADV ADV suspends burst OE t OE tOHZ t OLZ tACK tCLZ t COH t CHZ *3 Q Q (A1)
Q (A2)*1
Q (A2+1)
Q (A2+2)
Q (A2+3)
Q (A2)
tACK
Q (A3) Burst wraps around to its initial state.
Q (A2+1)
Single READ
BURST READ
H or L Undefined
Notes: 1. Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from next internal burst address following A2. 2. CE2 and CE2 have timing identical to CE1. On this diagram, when CE1 is LOW, CE2 is LOW and CE2 is HIGH. When CE1 is HIGH, CE2 is HIGH and CE2 is LOW. 3. Outputs are disabled within one clock cycle after deselect. 4. ZZ is LOW
11
! & , " 0, + * . $ ' "* .
0'
+ $ , &
HM62P1321 Series
Example of Write Timing
tCYC CLK ADSP tCH t CL tSADS tHADS tSADS tHADS ADSC ADSC extends burst tSADS tHADS tSA tHA A1 Address BW0 to BW3 BWE A2 BYTE WRITE signals are ignored for first cycle when ADSP initiates burst A3 tSW tHW GW
*4
, ,,, , ,, , ,, ,, ,, , , , , ,,, ,
tSCE tHCE CE1 *1 tSADV tHADV ADV
*3 *3
ADV suspends burst
OE
*2
tSD tHD
D
High-Z
D (A1) tOHZ
D (A2)
D (A2+1)
D (A2+1)
D (A2+2)
D (A2+3)
D (A3)
D (A3+1)
D (A3+2)
Q
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE H or L Undefined
Notes: 1. CE2 and CE2 have timing identical to CE1. On this diagram, when CE1 is LOW, CE2 is LOW and CE2 is HIGH. When CE1 is HIGH, CE2 is HIGH and CE2 is LOW. 2. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 3. ADV must be HIGH to permit a WRITE to the loaded address. 4. Full width WRITE can be initiated by GW is LOW or GW is HIGH and BWE, BW0 to BW3 are LOW. 5. ZZ is LOW.
12
0 " , !, +
* $ & . ' " ! , + $
HM62P1321 Series
Example of Read/Write Timing
t CYC
, , , ,, ,,,, , , , , ,,,,, , , ,
CLK ADSP
t CH t CL t SADS t HADS
ADSC
t SA t HA
Address
A1
A2
A3
t SW t HW
BW0 to BW3 BWE CE1 *2 ADV
t SCE t HCE
OE
*3
t ACK
t SD t HD
D
High-Z
D (A2)
t OHZ
t OLZ
t CLZ
t ACK
Q
High-Z
*3
Q (A1)
Q (A3)*1
Q (A3+1)
Q (A3+2)
Single READ
Single WRITE
BURST READ
H or L Undefined
Notes: 1. Q (A3) refers to output from address A3. Q (A3 + 1) refers to output from next internal burst address following A3. 2. CE2 and CE2 have timing identical to CE1. On this diagram, when CE1 is LOW, CE2 is LOW and CE2 is HIGH. When CE1 is HIGH, CE2 is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge. 4. GW is HIGH. ZZ is LOW.
13
!,
0 $ "+ * , & ' + $ 0 . , & !
HM62P1321 Series
Example of Power-down State Timing
tCYC CLK ADSP tCH tCL tSADS tHADS ADSC tSA tHA A1 Address A2 BW0 to BW3 BWE CE1 *1 tSW tHW tSCE tHCE ADV OE tOE tOHZ tCLZ Q Q (A1)
*3 *4
, , ,, , , , ,, , , , , ,,,, ,
Q (A2) tACK tZZS tZZREC
*3
ZZ
Single READ
Power-down State with Data retention
BURST READ
H or L Undefined
Notes: 1. CE2 and CE2 have timing identical to CE1. On this diagram, when CE1 is LOW, CE2 is LOW and CE2 is HIGH. When CE1 is HIGH, CE2 is HIGH and CE2 is LOW. 2. GW is HIGH. 3. During the cycle when transition of ZZ from high to low or from low to high occurs, ADSP, ADSC, BWE, GW and BWi must be high at its rising edge of CLK. 4. Data-output is not guaranteed during the cycle when transition of ZZ from low to high occurs.
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HM62P1321 Series
Detailed Pin Description
LQFP pin number(s) Symbol Type Input Description Synchronous Address Inputs: These inputs are registered and must meet setup and hold times around the rising edge of CLK. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BW0 controls DQ0 to DQ7. BW1 controls DQ8 to DQ15. BW2 controls DQ16 to DQ23. BW3 controls DQ24 to DQ31. Data I/O are tri-stated if any of these four inputs are LOW. Synchronous Global Write: This active LOW input allows a full 32 bit Write to occur independent of the BWE and BWi lines and must meet the setup and hold times around the rising edge of CLK. System must connect pin to VDD when not used. Synchronous Byte Write Enable: This active LOW input permits byte write operations and must meet the setup and hold times around the rising edge of CLK. System must connect pin to VSS when not used. Clock: This signal latches the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enables: This active LOW input is used to enable the device and conditions internal use of ADSP. This input is sampled only when a new external address is load. Synchronous Chip Enable: This active LOW input is used to enable the device. This input is sampled only when a external address is loaded. This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable the device. This input sampled only when a new external address is load. This input can be used for memory depth expansion. Output Enable: This active LOW asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait status to be generated (no address advance). This pin must be HIGH at the rising edge of the first clock after an ADSP cycle is initiated if a write cycle is desired (to ensure use of correct address). 37, 36, 35, 34, 33, 32, 100, A0 to A14 99, 82, 81, 44, 45, 46, 47, 48 93, 94, 95, 96 BW0, BW1 BW2, BW3
Input
88
GW
Input
87
BWE
Input
89
CLK
Input
98
CE1
Input
92
CE2
Input
97
CE2
Input
86 83
OE ADV
Input Input
15
HM62P1321 Series
Detailed Pin Description (cont)
LQFP pin number(s) 84 Symbol ADSP Type Input Description Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be latched. A READ performed using the new address, independent of the byte write enables and ADSC but dependent upon CE2 and CE2. ADSP is ignored if CE1 is HIGH. Power-down state is entered if CE2 is HIGH or CE2 is LOW. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst and causes a new external address to be latched. A READ or WRITE is performed using the new address if all chip enables are active. Powerdown state is entered if one or more chip enabled are inactive. No Connect: These signals are internally not connected.
85
ADSC
Input
1, 14, 16, 30, 31, 38, 39, 42, 43,49, 50, 51, 64, 66, 80
NC
--
52, 53, 56, 57, 58, 59, 62, DQ0 to 63, 68, 69, 72, 73, 74, 75, DQ31 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 15, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 64 VDD VDDQ VSS ZZ
Input/ SRAM Data I/O: Byte 0 is DQ0 to DQ7; Byte 1 is DQ8 to Output DQ15; Byte 2 is DQ16 to DQ23; Byte 3 is DQ24 to DQ31. Input data must meet setup and hold times around the rising edge of CLK. Supply Power Supply: +3.3 V 5 % Supply I/O Power Supply: +2.375V to VDD Supply Ground: GND Input Asynchronous Power down (Snooze):This active HIGH input enables SRAM to enter a Power down (Snooze) state with data retention. During Snooze state, data retention is guranteed. At this time, internal state of the SRAM must be initiated with ADSP or ADSC using a new external address. Must be connected to VSS in systems that do not use ZZ feature.
16
HM62P1321 Series
Package Dimensions
HM62P1321FP Series (FP-100H)
Unit: mm
22.00 0.10 20.00 80 81 16.00 0.10 14.00 51 50
100 1 0.32 0.08 0.30 0.06 0.575 30 0.10 M
31 1.40 0.05
0.17 0.05 0.15 0.04
1.60 Max
0.825
1.00 0 - 10
0.10 0.05
0.1
0.50 0.10
Hitachi Code JEDEC Code EIAJ Code Weight FP-100H MO-136 -- 0.95 g
17
HM62P1321 Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
18
HM62P1321 Series
Revision Record
Rev. 0.0 Date Mar. 6, 1997 Contents of Modification Initial issue Drawn by Approved by
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