View 56UW464E_968908.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HB56UW464EJ-6B/7B/8B
4,194,304-word x 64-bit High Density Dynamic RAM Module 168-pin JEDEC Standard Outline Buffered 8 byte DIMM
ADE-203-562(Z) Preliminary Rev. 0.0 Apr. 16, 1996
Description
The HB56UW464EJ belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56UW464EJ is a 4M x 64 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM51W16405BS) sealed in SOJ package,1 piece of 16-bit CMOS line driver (74ALVCH16244) sealed in TSSOP package and 1 piece of 20-bit CMOS line driver (74ALVCH16827) sealed in TSSOP package. The HB56UW464EJ offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56UW464EJ is 168-pin socket type package (dual lead out). Therefore, the HB56UW464EJ makes high density mounting possible without surface mount technology. The HB56UW464EJ provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ on the module board.
Features
* * * 168-pin socket type package (Dual lead out) Lead pitch: 1.27 mm Single 3.3 V (0.3 V) supply High speed Access time: tRAC = 60/70/80 ns (max) Access time: tCAC = 20/23/25 ns (max) Low power dissipation Active mode: 4.62/4.04/3.75 W (max) Standby mode (TTL): 123 mW (max) Standby mode (CMOS): 64.8 mW (max) Buffered input except RAS and DQ 4 byte interleave enabled, dual address input (A0/B0) EDO page mode capability 4,096 refresh cycle: 64 ms 2 variations of refresh RAS-only refresh CAS-before-RAS refresh
*
* * * * *
HB56UW464EJ-6B/7B/8B
Ordering Information
Type No. HB56UW464EJ-6B HB56UW464EJ-7B HB56UW464EJ-8B Access time 60 ns 70 ns 80 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 10 pin 11 pin 85 pin 94 pin 95 pin
40 pin 41 pin 124 pin 125 pin
84 pin 168 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12
Pin Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VSS
Pin No. 13 14 15 16 17 18 19 20 21 22 23 24
Pin Name DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 NC VSS NC
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36
Pin Name NC VCC WE0 CE0 CE2 RE0 OE0 VSS A0 A2 A4 A6
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48
Pin Name A8 A10 NC VCC NC NC VSS OE2 RE2 CE4 CE6 WE2
2
HB56UW464EJ-6B/7B/8B
Pin Arrangement (cont)
Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin Name VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 NC DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 NC VSS Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name PD1 PD3 PD5 PD7 ID0 (VSS) VCC VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 NC VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 NC VSS NC Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin Name NC VCC NC CE1 CE3 NC NC VSS A1 A3 A5 A7 A9 A11 NC VCC NC B0 VSS NC NC CE5 CE7 PDE VCC NC NC DQ54 DQ55 VSS Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Name DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 NC DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 NC VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC
3
HB56UW464EJ-6B/7B/8B
Pin Description
Pin Name A0 to A11, B0 Function Address Input Row Address Column Address Refresh Address Data-in/Data-out : : : : A0 to A11, B0 A0 to A11, B0 A0 to A9, B0 A0 to A11, B0
DQ0 to DQ7, DQ9 to DQ16, DQ18 to DQ25, DQ27 to DQ34, DQ36 to DQ43, DQ45 to DQ52, DQ54 to DQ61, DQ63 to DQ70 RE0, RE2 CE0 to CE7 WE0, WE2 OE0, OE2 VCC VSS PD1 to PD8 ID0, ID1 PDE NC
Row Address Strobe Column Address Strobe Read/Write Enable Output Enable Power Supply Ground Presence Detect ID bit Presence Detect Enable No Connection
Presence Detect Pin Assignment
PDE = Low Pin Name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Pin No. 79 163 80 164 81 165 82 166 60 ns 1 1 0 1 1 1 1 1 70 ns 1 1 0 1 1 0 1 1 80 ns 1 1 0 1 1 1 0 1 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
1: High Level (Driver Output) 0: Low Level (Driver Output)
4
HB56UW464EJ-6B/7B/8B
Block Diagram
RE0 CE0 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 CE2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 CE3 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D6 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D4 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D2 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D0 RE2 CE4 WE2 OE2 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 CE5 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 CE6 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 CE7 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D14 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D12 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D10 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D8
RAS WE OE D1
RAS WE OE D9
RAS WE OE D3
RAS WE OE D11
RAS WE OE D5
RAS WE OE D13
RAS WE OE D7
RAS WE OE D15
PD1 to PD8 A0 B0 A1 to A11 VCC VSS 0.22 F D0 to D7 D8 to D15 D0 to D15 D0 to D15, 74ALVCH16827, 74ALVCH16244 18 pcs D0 to D15, 74ALVCH16827, 74ALVCH16244 D0 to D15 : HM51W16405 : 74ALVCH16827, 74ALVCH16244 VCC VCC VSS VCC VCC VCC VSS VCC VSS VCC PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
5
HB56UW464EJ-6B/7B/8B
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 18 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Condition (Ta = 0 to +70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referenced to V SS . VIH VIL Min 0 3.0 2.0 -0.3 Typ 0 3.3 -- -- Max 0 3.6 VCC + 0.3 0.8 Unit V V V V 1 1 1 Note
6
HB56UW464EJ-6B/7B/8B
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
60 ns Parameter Operating current Standby current Symbol Min I CC1 I CC2 -- -- 70 ns Max Min 1282 -- 34 -- 80 ns Max Min 1122 -- 34 -- Max Unit Test conditions 1042 mA 34 mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin VCC 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Note 1, 2
--
18
--
18
--
18
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current Input leakage current
I CC3 I CC5 I CC6 I CC7 I LI
-- -- -- -- -10 -10 2.4 0
1282 -- 82 --
1122 -- 82 --
1042 mA 82 mA
1282 -- 1602 -- 10 10 VCC 0.4 -10 -10 2.4 0
1122 -- 1442 -- 10 10 VCC 0.4 -10 -10 2.4 0
1042 mA 1282 mA 10 10 VCC 0.4 A A V V
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (CAS, WE, OE) Input capacitance (RAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 20 20 71 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
7
HB56UW464EJ-6B/7B/8B
AC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3 V, VSS = 0 V)*1, *2, *18, *19
Test Conditions * * * * * Input rise and fall times: 2 ns Input level: VIL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference level: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
60 ns Parameter RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period (4,096 cycles) Symbol Min 104 40 10 60 10 0 10 0 10 20 15 20 48 10 20 0 0 2 -- Max -- -- -- 70 ns Min 124 50 13 Max -- -- -- 80 ns Min 144 60 15 Max -- -- -- Unit Notes ns ns ns
Random read or write cycle time t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT t REF
10000 70 10000 13 -- -- -- -- 40 25 -- -- -- -- -- -- 50 64 0 10 0 13 20 15 23 58 10 23 0 0 2 --
10000 80 10000 15 -- -- -- -- 47 30 -- -- -- -- -- -- 50 64 0 10 0 15 20 15 25 68 10 25 0 0 2 --
10000 ns 10000 ns -- -- -- -- 55 35 -- -- -- -- -- -- 50 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5 6 6 7 3 4
8
HB56UW464EJ-6B/7B/8B
Read Cycle
60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD -- -- -- -- 0 0 60 0 35 18 2 3 3 -- -- 20 3 -- -- 20 15 Max 60 20 35 20 -- -- -- -- -- -- -- -- -- 20 20 -- -- 15 20 -- -- 70 ns Min -- -- -- -- 0 0 70 0 40 23 2 3 3 -- -- 23 3 -- -- 23 18 Max 70 23 40 23 -- -- -- -- -- -- -- -- -- 20 20 -- -- 15 20 -- -- 80 ns Min -- -- -- -- 0 0 80 0 45 28 2 3 3 -- -- 25 3 -- -- 25 20 Max 80 25 45 25 -- -- -- -- -- -- -- -- -- 20 20 -- -- 15 20 -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 8, 9 9, 10, 17 9, 11, 17 9
Output data hold time from RAS t OHR t OFR t WEZ t WED t RDD
9
HB56UW464EJ-6B/7B/8B
Write Cycle
60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 15 10 0 15 Max -- -- -- -- -- -- -- 70 ns Min 0 13 10 18 13 0 18 Max -- -- -- -- -- -- -- 80 ns Min 0 15 10 20 15 0 20 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 15 15 14
Read-Modify-Write Cycle
60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 149 87 37 52 15 Max -- -- -- -- -- 70 ns Min 175 100 43 60 18 Max -- -- -- -- -- 80 ns Min 199 112 47 67 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14
Refresh Cycle
60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min t CSR t CHR t WRP t WRH t RPC 10 10 5 10 0 Max -- -- -- -- -- 70 ns Min 10 10 5 10 0 Max -- -- -- -- -- 80 ns Min 10 10 5 10 0 Max -- -- -- -- -- Unit Notes ns ns ns ns ns
10
HB56UW464EJ-6B/7B/8B
EDO Page Mode Cycle
60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol Min t HPC t RASP t CPA t CPRH 25 -- -- 40 3 10 5 35 Max -- 70 ns Min 30 Max -- 80 ns Min 35 Max -- Unit Notes ns 20 16 9, 17
100000 -- 40 -- -- -- -- -- -- 45 3 13 5 40
100000 -- 45 -- -- -- -- -- -- 50 3 15 5 45
100000 ns 50 -- -- -- -- -- ns ns ns ns ns ns
Output data hold time from CAS t DOH low CAS hold time refferrd OE CAS to OE setup time Read command hold time from CAS precharge t COL t COP t RCHC
9, 17
EDO Page Mode Read-Modify-Write Cycle
60 ns Parameter EDO page mode read-modifywrite cycle time WE delay time from CAS precharge Symbol Min t PRWC t CPW 79 54 Max -- -- 70 ns Min 90 62 Max -- -- 80 ns Min 99 69 Max -- -- Unit Notes ns ns 14
11
HB56UW464EJ-6B/7B/8B
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA or tCAC or tCPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); t OEH tCWL, invalid data will be out at each DQ. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / V SS line noise, which causes to degrade V IH min / V IL max level.
12
HB56UW464EJ-6B/7B/8B
Timing Waveform *22
Read Cycle
tRC tRAS RAS tCSH tRCD tT CAS tRAD tASR Address tRAH tASC tRAL tCAL tCAH tRSH tCAS tCRP tRP
Row
Column tRCHR tRCS tRCH tRRH
WE tWED tDZC High-Z tCDD tRDD
Din tDZO
tOEA
tOED
OE tOEZ tOHO tOFF tOH tOFR tOHR tWEZ Dout Dout
tCAC tAA tRAC tCLZ
Note : 22
: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) Invalid Dout
:
13
HB56UW464EJ-6B/7B/8B
Early Write Cycle
tRC tRAS RAS tRP
tCSH tRCD tT CAS tCAS tRSH
tCRP
tASR
tRAH
tASC
tCAH
Address
Row
Column
tWCS
tWCH
WE
tDS
tDH
Din
Din
Dout
High-Z * OE : H or L WCS
WCS(min)
14
HB56UW464EJ-6B/7B/8B
Delayd Write Cycle
tRC tRAS RAS tCSH tRCD tT CAS tASR tRAH tASC tCAH tRSH tCAS tCRP tRP
Address
Row
Column tCWL tRCS tRWL tWP
WE tDZC High-Z Din tCLZ tDZO tOED tOEH High-Z tDH tDS Din
Dout
Dout tOEZ
OE
15
HB56UW464EJ-6B/7B/8B
Read-Modify-Write Cycle
tRWC tRAS RAS tRCD tT CAS tRAD tASR tRAH tASC tCAH tCAS tCRP
tRP
Address
Row tRCS
Column tCWD tAWD tRWD tCWL tRWL tWP
WE tDZC High-Z Din tCAC tAA tRAC tCLZ Dout tOEA tDZO tOED tOEZ tOHO tOEH Dout High-Z tDH tDS Din
OE
16
HB56UW464EJ-6B/7B/8B
RAS-Only Refresh Cycle
tRC tRAS RAS tRP
tT tCRP tRPC tCRP
CAS
tASR
tRAH
Address tOFR tOFF Dout
Row
High-Z
* WE, OE : H or L
17
HB56UW464EJ-6B/7B/8B
CAS-Before-RAS Refresh Cycle
tRC tRP RAS tRPC tCP tT tCSR tCHR tCP tRPC tCRP tRAS tRP
CAS tWRP tWRH
WE
Address tOFR tOFF High-Z * OE : H or L
Dout
18
HB56UW464EJ-6B/7B/8B
EDO Page Mode Read Cycle
tRP RAS tT tCSH CAS tCAS tRCHR tRCS WE
tWP
tRASP tHPC tCP tCAS tCP tCAS
tRCHC
tHPC
tHPC
tCPRH tCP tRSH tCAS
tCRP
tRCH
tRCS
tRRH tRCH
tRAL
tASC
tRAH tASR Address
Row tASC
tCAH
tASC
tASC tCAH tCAH
Column 4
tWED
tCAH
Column 1
Column 2
Column 3
tRDD tDZC tCAL tCAL tCAL tCAL tCDD
Din tDZO
High-Z
tCOL
tCOP
tOED tOFR tOHR
OE
tOEA tCAC tAA tCPA tCPA tOEZ tOEA tCAC tOHO Dout 2 tCPA tOEZ tOHO Dout 3 tOEZ
tAA tWEZ
tAA
tCAC tDOH
tAA
tCAC tOEA
tRAC Dout
tOFF tOHO
tOH Dout 4
Dout 1
Dout 2
19
HB56UW464EJ-6B/7B/8B
EDO Page Mode Eary Write Cycle
tRASP tRP RAS tCSH tRCD tT CAS tCAS tCP tHPC tCAS tCP
tRSH tCAS
tCRP
tASR Address
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
Row
Column 1 tWP tWCS tWCH
Column 2 tWP tWCS tWCH
Column N tWP tWCS tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
Din
Din 1
Din 2
Din N
Dout
High-Z * OE : H or L > ** tWCS = tWCS(min)
20
HB56UW464EJ-6B/7B/8B
EDO Page Mode Delayed Write Cycle
tRASP RAS tCSH tRCD tT CAS tRAD tRAH tASR Address Row tASC tCAH Column 1 tCWL tRCS WE
tWP tWP tWP
tRP
tHPC tCAS tCP tCAS tCP
tRSH tCRP tCAS
tASC tCAH Column 2 tCWL tRCS
tASC tCAH Column N tCWL tRCS tRWL
tDZC
tDS tDH
tDZC tDS
Din 2
tDZC tDS tDH
Din N
tDH
Din tDZO tCLZ
Din 1
tDZO tOEH tCLZ tOEH
tDZO tCLZ tOEH High-Z
Dout Invalid Dout tOED tOEZ OE Invalid Dout tOED tOEZ Invalid Dout tOED tOEZ
21
HB56UW464EJ-6B/7B/8B
EDO Page Mode Read-Modify-Write Cycle
tRASP RAS tHPRWC tT tRCD CAS tRAD tASC tCAH tCWL
Column 1
tRP
tRSH tCP tCAS
tCRP
tCAS
tCP
tCAS
tASC tCAH tCWL
Column 2
tASC
tRWL tCAH tCWL
tASR Address
tRAH
Row
Column N
tRWD tRCS WE tDZC tWP tDS
tDH
tCPW
tRCS
tCPW tRCS tAWD
tCWD
tAWD
tCWD
tAWD
tCWD
tDZC
tDS
tWP
tDH Din 2
tDZC
tWP
tDS tDH
Din
tCLZ
Din 1
tCLZ
tCLZ
Din N
tCAC tAA tRAC
tOEA
tCAC tAA tCPA tOEH
tOEA Dout 2
tCAC tAA tCPA tOEH
tOEA Dout N
tOEH
High-Z
Dout tDZO
Dout 1
tOHO
tDZO
tOEZ
tOHO
tDZO
tOEZ
tOHO
tOEZ
OE
tOED
tOED
tOED
22
HB56UW464EJ-6B/7B/8B
EDO Page Mode Mix Cycle (1)
tRP RAS tT tCSH CAS tRCD tWCS WE tRAH tASR Address
Row tASC Column 1
tRASP tCRP tCP tCAS tCP tCAS tCP tRSH tCAS
tCAS
tWP tWCH tCPW t WP
tAWD
tRCS
tRRH tRCH
tCAH tASC tCAH
Column 2 tASC
tASC tCAH
tRAL tCAH
Column 4
Column 3
tCAL tDS Din tDH
tCAL
tCAL tDS tDH
Din 3
tCAL
tRDD tCDD
Din 1
High-Z
tWED
tOFR
tOED OE tCPA tAA tOEA tCAC Dout
tCPA tAA tCAC
tWEZ
tOEZ
tOHO
tCPA tAA tCAC
tDOH
Dout 2 Dout 3
tOEA
tOFF
tOH Dout 4
tOEZ tOHO
23
HB56UW464EJ-6B/7B/8B
EDO Page Mode Mix Cycle (2)
tRP RAS tT tCSH CAS tRCD tRCS WE tWP tRAH tCAH tASR Address
Row tASC Column 1
tRASP tCRP tCP tCAS tCP tCAS tCP tRSH tCAS
tCAS tRCHR tRCH
tWCS tWCH
tRCS tCPW
tWP
tRRH tRCH
tRAL tASC tCAH
Column 3
tASC tCAH
Column 2
tASC tCAH
Column 4
tCAL tDS Din High-Z
tCAL tDH
Din 2
tCAL tDS tDH
Din 3
tCAL
tRDD tCDD
tWED tCOP tOED OE
tAA tOEA tOFR
tOED tCOL tOEA tCPA tAA tCAC tOEA
Dout 3
tWEZ
tRAC Dout
tCAC
tOEZ
tOHO
tCPA
tOEZ
tOHO
tOEZ
tOFF tOH Dout 4
tAA tCAC
tOHO
Dout 1
24
HB56UW464EJ-6B/7B/8B
Physical Outline
133.35 5.250 3.00 0.118 127.35 5.014 9.00 Max 0.354 Max
Unit: mm/inch
1
84
4.00 Min 0.157 Min 3.00 0.118
A 8.89 11.43 C 0.350 0.450 2 - 3.00 2 - 0.118
85
A 36.83 1.450 B 54.61 2.150
1.27 0.10 0.050 0.004
Detail A
2.54 Min 0.100 Min
1.00 0.05 0.039 0.002
Detail B and C
0.25 Max 0.010 Max
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
1.27 0.050
4.00 0.157 17.78 0.700 25.40 1.000
168
25
HB56UW464EJ-6B/7B/8B
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
26

▲Up To Search▲

Price & Availability of 56UW464E

	To Download 56UW464E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .