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HB56UW1672EJN Series HB56UW1664EJN Series
16777216-word x 72-bit High Density Dynamic RAM Module 16777216-word x 64-bit High Density Dynamic RAM Module
ADE-203-643 (Z) Preliminary Rev. 0.0 Aug. 31, 1996 Description
The HB56UW1672EJN Series, HB56UW1664EJN Series belong to 8-byte DIMM (Dual in-line Memory Module) family , and have been developed an optimized main memory solution for 4 and 8-byte processor applications. The HB56UW1672EJN Series is a 16 M x 72 Dynamic RAM Module, mounted 18 pieces of 64-Mbit DRAM (HM5164405AJ) sealed in SOJ package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). The HB56UW1664EJN Series is a 16 M x 64 Dynamic RAM Module, mounted 16 pieces of 64-Mbit DRAM (HM5164405AJ) sealed in SOJ package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). The HB56UW1672EJN Series, HB56UW1664EJN Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56UW1672EJN Series, HB56UW1664EJN Series are 168-pin socket type package (dual lead out). Therefore, the HB56UW1672EJN Series, HB56UW1664EJN Series make high density mounting possible without surface mount technology. The HB56UW1672EJN Series, HB56UW1664EJN Series provide common data inputs and outputs. Decoupling capacitors are mounted beside each SOJ on the its module board.
Features
* 168-pin socket type package (Dual lead out) Outline: 133.35 mm (Length) x 25.40 mm (Height) x 9.00 mm (Thickness) Lead pitch : 1.27 mm * Single 3.3 V (0.3 V) * High speed Access time: tRAC = 60 ns/70 ns (max) Access time: tCAC = 15 ns/18 ns (max)
Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice.
HB56UW1672EJN Series, HB56UW1664EJN Series
* Low power dissipation Active mode: 8.42 W/7.13W (max) (HB56UW1672EJN Series) Active mode: 7.45 W/6.34W (max) (HB56UW1664EJN Series) Standby mode (TTL): 129.6 mW (max) (HB56UW1672EJN Series) Standby mode (TTL): 115.2 mW (max) (HB56UW1664EJN Series) Standby mode (CMOS): 64.8 mW (max) (HB56UW1672EJN Series) Standby mode (CMOS): 57.6 mW (max) (HB56UW1664EJN Series) * JEDEC standard outline unbuffered 8-byte DIMM * EDO page mode capability * 8192 refresh cycles: 64 ms * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible
Ordering Information
Type No. HB56UW1672EJN-6A HB56UW1672EJN-7A HB56UW1664EJN-6A HB56UW1664EJN-7A Access time 60 ns 70 ns 60 ns 70 ns Package 168-pin dual lead out socket type Contact pad Gold
2
HB56UW1672EJN Series, HB56UW1664EJN Series
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Signal name Pin No. VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 (NC)* CB1 (NC)* VSS NC NC
1 2
Signal name Pin No. VSS OE2 RAS2 CAS2 CAS3 WE2 VCC NC NC CB2 (NC)*
3
Signal name Pin No. VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 (NC)* CB5 (NC)* VSS NC NC
5 6
Signal name VSS NC NC CAS6 CAS7 NC VCC NC NC CB6 (NC)*7 CB7 (NC)*8 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
85 86 87 88 89 90 91 92 93 94
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151
CB3 (NC)*4 95 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 96 97 98 99 100 101 102 103 104 105 106 107 108 109
3
HB56UW1672EJN Series, HB56UW1664EJN Series
Pin Arrangement (cont)
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Notes: 1. 2. 3. 4. 5. 6. 7. 8. Signal name Pin No. VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC NC CB0: CB1: CB2: CB3: CB4: CB5: CB6: CB7: 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal name Pin No. VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Signal name Pin No. VCC NC CAS4 CAS5 NC NC VSS A1 A3 A5 A7 A9 A11 NC VCC NC NC 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Signal name VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC
HB56UW1672EJN, NC: HB56UW1672EJN, NC: HB56UW1672EJN, NC: HB56UW1672EJN, NC: HB56UW1672EJN, NC: HB56UW1672EJN, NC: HB56UW1672EJN, NC: HB56UW1672EJN, NC:
HB56UW1664EJN HB56UW1664EJN HB56UW1664EJN HB56UW1664EJN HB56UW1664EJN HB56UW1664EJN HB56UW1664EJN HB56UW1664EJN
4
HB56UW1672EJN Series, HB56UW1664EJN Series
Pin Description
Pin name A0 to A12 Function Address input Row address Column address Refresh address DQ0 to DQ63 RAS0, RAS2 CAS0 to CAS7 WE0, WE2 OE0, OE2 SDA SCL SA0 to SA2 CB0 to CB7* VCC VSS NC Note:
1
A0 to A12 A0 to A10 A0 to A12
Data input/output Row address strobe Column address strobe Read/Write enable Output enable Serial data out (bit0 to bit7) Clock for presence detect Serial address input Check bit Power supply Ground No connection
1. This function is supported only HB56UW1672EJN Series.
5
HB56UW1672EJN Series, HB56UW1664EJN Series
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 Number serial PD bytes Serial memory Fundamental memory type Number of row addresses Number of column addresses Number of banks Module data width HB56UW1672EJN HB56UW1664EJN 7 8 9 Module data width (continued) Module supply voltage/interface levels RAS access time 60 ns 70 ns 10 CAS access time 15 ns 18 ns 11 Error detection/corraction HB56UW1672EJN HB56UW1664EJN 12 Note: Refresh rate/type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 13 256byte EDO 13 11 1 72 64 0 (+) 3.3 V
0 0 0 0 0 0 0
0 1 0 0 0 0 0
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 1 1 0 0 0 0
0 1 1 1 1 0 1
0 0 1 0 0 0 0 ECC None Reduced (7.8 s)
1. 0: Serial data, "driven Low", 1: Serial data, "driven High" Serial PD data are not protected.
6
HB56UW1672EJN Series, HB56UW1664EJN Series
Block Diagram (HB56UW1672EJN)
RAS0 CAS0 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 to A12 VCC VSS 0.22 F x 36 pcs CAS RAS WE OE I/O I/O D7 I/O I/O CAS RAS WE OE I/O I/O D8 I/O I/O D0 to D17 D0 to D17, U0 D0 to D17, U0 A0 SCL SCL SDA SDA CAS RAS WE OE I/O I/O D5 I/O I/O CAS RAS WE OE I/O I/O D6 I/O I/O CAS RAS WE OE I/O I/O D2 I/O I/O CAS RAS WE OE I/O I/O D3 I/O I/O CAS RAS WE OE I/O I/O D4 I/O I/O CAS RAS WE OE I/O I/O D0 I/O I/O CAS RAS WE OE I/O I/O D1 I/O I/O RAS2 CAS4 WE2 OE2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CAS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CB4 CB5 CB6 CB7 CAS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CAS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CAS RAS WE OE I/O I/O D16 I/O I/O CAS RAS WE OE I/O I/O D17 I/O I/O Serial PD CAS RAS WE OE I/O I/O D14 I/O I/O CAS RAS WE OE I/O I/O D15 I/O I/O CAS RAS WE OE I/O I/O D11 I/O I/O CAS RAS WE OE I/O I/O D12 I/O I/O CAS RAS WE OE I/O I/O D13 I/O I/O CAS RAS WE OE I/O I/O D9 I/O I/O CAS RAS WE OE I/O I/O D10 I/O I/O
U0
A1 A2
*D0 to D17: HM5164405 U0: 24C02
SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
7
HB56UW1672EJN Series, HB56UW1664EJN Series
Block Diagram (HB56UW1664EJN)
RAS0 CAS0 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CAS RAS WE OE I/O I/O D6 I/O I/O CAS RAS WE OE I/O I/O D7 I/O I/O CAS RAS WE OE I/O I/O D4 I/O I/O CAS RAS WE OE I/O I/O D5 I/O I/O CAS RAS WE OE I/O I/O D2 I/O I/O CAS RAS WE OE I/O I/O D3 I/O I/O CAS RAS WE OE I/O I/O D0 I/O I/O CAS RAS WE OE I/O I/O D1 I/O I/O RAS2 CAS4 WE2 OE2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CAS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CAS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CAS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CAS RAS WE OE I/O I/O D14 I/O I/O CAS RAS WE OE I/O I/O D15 I/O I/O Serial PD A0 to A12 VCC VSS 0.22 F x 32 pcs D0 to D15 D0 to D15, U0 D0 to D15, U0 A0 SCL SCL SDA SDA CAS RAS WE OE I/O I/O D12 I/O I/O CAS RAS WE OE I/O I/O D13 I/O I/O CAS RAS WE OE I/O I/O D10 I/O I/O CAS RAS WE OE I/O I/O D11 I/O I/O CAS RAS WE OE I/O I/O D8 I/O I/O CAS RAS WE OE I/O I/O D9 I/O I/O
U0
A1 A2
*D0 to D15: HM5164405 U0: 24C02
SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
8
HB56UW1672EJN Series, HB56UW1664EJN Series
Absolute Maximum Ratings (HB56UW1672EJN)
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 18 0 to +70 -55 to +125 Unit V V mA W C C
Absolute Maximum Ratings (HB56UW1664EJN)
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 16 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Note: Symbol VCC VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 -- -- Max 3.6 VCC + 0.3 0.8 Unit V V V Notes 1, 2 1 1
1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
9
HB56UW1672EJN Series, HB56UW1664EJN Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HB56UW1672EJN)
HB56UW1672EJN 60 ns Parameter Operating current* , * 2
1
70 ns Max 2340 36 Min -- -- Max 1980 36 Unit Test conditions mA mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin 4.6 0 V Vin 4.6 Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC1 I CC2 -- --
Standby current
--
18
--
18
mA
RAS-only refresh current*2 Standby current*
1
I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL
-- -- -- -- -10 -10 2.4 0
2340 90 2700 2520 10 10 VCC 0.4
-- -- -- -- -10 -10 2.4 0
1980 90 2340 2160 10 10 VCC 0.4
mA mA mA mA A A V V
CAS-before-RAS refresh current EDO page mode current*1, * 3 Input leakage current Output leakage current Output high voltage Output low voltage
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle t HPC .
10
HB56UW1672EJN Series, HB56UW1664EJN Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HB56UW1664EJN)
HB56UW1664EJN 60 ns Parameter Operating current* , * 2
1
70 ns Max 2080 32 Min -- -- Max 1960 32 Unit Test conditions mA mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin 4.6 V 0 V Vin 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC1 I CC2 -- --
Standby current
--
16
--
16
mA
RAS-only refresh current*2 Standby current*
1
I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL
-- -- -- -- -10 -10 2.4 0
2080 80 2400 2240 10 10 VCC 0.4
-- -- -- -- -10 -10 2.4 0
1960 80 2080 1920 10 10 VCC 0.4
mA mA mA mA A A V V
CAS-before-RAS refresh current EDO page mode current*1, * 3 Input leakage current Output leakage current Output high voltage Output low voltage
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC .
11
HB56UW1672EJN Series, HB56UW1664EJN Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB56UW1672EJN)
Parameter Input capacitance (Address) Input capacitance (CAS) Input capacitance (RAS, WE, OE) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 110 41 83 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB56UW1664EJN)
Parameter Input capacitance (Address) Input capacitance (CAS) Input capacitance (RAS, WE, OE) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 100 34 76 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
12
HB56UW1672EJN Series, HB56UW1664EJN Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *3,*18
Test Conditions * * * * * Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HB56UW1672EJN/HB56UW1664EJN 60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 104 40 10 60 10 0 10 0 10 20 15 15 48 5 15 0 0 2 Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 70 ns Min 124 50 13 70 13 0 10 0 13 20 15 18 58 5 18 0 0 2 Max -- -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 20 3 4 Notes
13
HB56UW1672EJN Series, HB56UW1664EJN Series
Read Cycle
HB56UW1672EJN/ H B56UW1664EJN 60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- 70 ns Min -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 13, 20 13 5 12 12 Notes 8, 9 9, 10, 16 9, 11, 16 9
14
HB56UW1672EJN Series, HB56UW1664EJN Series
Write Cycle
HB56UW1672EJN/ H B56UW1664EJN 60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- 70 ns Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns Notes 14
Read-Modify-Write Cycle
HB56UW1672EJN/ H B56UW1664EJN 60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 149 78 33 48 15 Max -- -- -- -- -- 70 ns Min 175 91 39 56 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
HB56UW1672EJN/ H B56UW1664EJN 60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min t CSR t CHR t WRP t WRH t RPC 5 10 0 10 0 Max -- -- -- -- -- 70 ns Min 5 10 0 10 0 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
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HB56UW1672EJN Series, HB56UW1664EJN Series
EDO Page Mode Cycle
HB56UW1672EJN/ H B56UW1664EJN 60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Symbol Min t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC 25 -- -- 35 3 10 10 35 10 10 Max -- 70 ns Min 30 Max -- Unit ns Notes 19 15 9, 16
100000 -- 35 -- -- -- -- -- -- -- -- 40 3 13 10 40 10 10
100000 ns 40 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns
9, 16
Write pulse width during CAS precharge t WPE OE precharge time t OEP
EDO Page Mode Read-Modify-Write Cycle
HB56UW1672EJN/ H B56UW1664EJN 60 ns Parameter EDO page mode read- modify-write cycle time WE delay time from CAS precharge Symbol Min t HPRWC t CPW 68 54 Max -- -- 70 ns Min 79 62 Max -- -- Unit ns ns 14 Notes
Refresh
Parameter Refresh period Symbol t REF Max 64 Unit ms Notes 8192 cycles
16
HB56UW1672EJN Series, HB56UW1664EJN Series
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t RASP defines RAS pulse width in EDO page mode cycles. 16. Access time is determined by the longest among t AA , t CAC and t CPA. 17. All the V CC and VSS pins shall be supplied with the same voltages. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 20. Output is disable after both RAS and CAS go to high. 21. t CSH (min) can be achieved when tRCD tCSH (min) - tCAS (min). 22. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
Timing Waveforms*22
Refer to the HB56UW3273 Series.
17
HB56UW1672EJN Series, HB56UW1664EJN Series
Physical Outline
HB56UW1672EJN Series, HB56UW1664EJN Series
Unit: mm/inch
Front side 133.35 5.250 3.00 0.118 127.35 5.014 9.00 max 0.354 max
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
C B 36.83 1.450 54.61 2.150 A 11.43 0.450
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
8.89 0.350
3.00 0.118
1.27 0.10 0.050 0.004
Back side 2 - 3.00 2 - 0.118
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
168 85
4.00 0.157
17.78 0.700
Detail A
2.54 min 0.100 min
Detail B 1.27 0.050
0.25 max 0.010 max
Detail C 3.175 0.125 6.35 0.250 2.00 0.10 0.079 0.004 1.00 0.039
3.125 0.125 0.123 0.005
1.00 0.05 0.039 0.002
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3.125 0.125 0.123 0.005
6.35 0.250 3.175 0.125 2.00 0.10 0.079 0.004
25.40 1.000
4.00 min 0.157 min
HB56UW1672EJN Series, HB56UW1664EJN Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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HB56UW1672EJN Series, HB56UW1664EJN Series
Revision Record
Rev. 0.0 Date Contents of Modification Drawn by Approved by Aug. 31, 1996 Initial issue
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