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HB56H232 Series, HB56H132 Series
2,097,152-word x 32-bit High Density Dynamic RAM Module 1,048,576-word x 32-bit High Density Dynamic RAM Module
ADE-203-700B (Z) Rev.2.0 May. 16, 1997 Description
The HB56H232 is a 2M x 32 dynamic RAM module, mounted 4 pieces of 16-Mbit DRAM (HM5118165) sealed in SOJ package. The HB56H132 is a 1M x 32 dynamic RAM module, mounted 2 pieces of 16-Mbit DRAM (HM5118165) sealed in SOJ package. The HB56H232, HB56H132 offer Extended Data Out (EDO) Page Mode as a high speed access time. An outline of the HB56H232, HB56H132 is 72-pin single in-line package. Therefore, the HB56H232, HB56H132 make high density mounting possible without surface mount technology. The HB56H232, HB56H132 provide common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
* 72-pin single in-line package Outline: 107.95 mm (Length) x 25.40 mm (Height) x 9.14/5.28 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 50 /60 /70ns (max) * Low power dissipation Active mode: 2.15 /1.84 /1.63 W (max) (HB56H232 Series) 2.10 /1.79 /1.58 W (max) (HB56H132 Series) Standby mode (TTL): 42 mW (max) (HB56H232 Series) (TTL): 21 mW (max) (HB56H132 Series) (CMOS): 3.15 mW (max) (L-version) (HB56H232 Series) (CMOS): 1.58 mW (max) (L-version) (HB56H132 Series) * EDO page mode capability * Refresh period 1024 refresh cycles: 16 ms 128 ms (L-version)
HB56H232 Series, HB56H132 Series
* 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible
Ordering Information
Type No. HB56H232B-5N HB56H232B-6N HB56H232B-7N HB56H232B-5NL HB56H232B-6NL HB56H232B-7NL HB56H132B-5N HB56H132B-6N HB56H132B-7N HB56H132B-5NL HB56H132B-6NL HB56H132B-7NL HB56H232SB-5N HB56H232SB-6N HB56H232SB-7N HB56H232SB-5NL HB56H232SB-6NL HB56H232SB-7NL HB56H132SB-5N HB56H132SB-6N HB56H132SB-7N HB56H132SB-5NL HB56H132SB-6NL HB56H132SB-7NL Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 72-pin SIP socket type Solder Package 72-pin SIP socket type Contact pad Gold
2
HB56H232 Series, HB56H132 Series
Pin Arrangement
1Pin
36Pin
37Pin
72Pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Pin name VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6
Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin name NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 (NC)* RAS2 NC NC
1
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
Pin name NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 (NC)* NC WE NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26
2
Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Pin name DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
Notes: 1. RAS3: HB56H232, NC: HB56H132 2. RAS1: HB56H232, NC: HB56H132
3
HB56H232 Series, HB56H132 Series
Pin Description
Pin name A0 to A9 Function Address inputs: Row address: Column address: Refresh address: DQ0 to DQ31 CAS0 to CAS3 RAS0 to RAS3 WE VCC VSS PD1 to PD4 NC Data-in/Data-out Column address strobe Row address strobe Read/Write enable Power supply Ground Presence detect pin No connection A0 to A9 A0 to A9 A0 to A9
Presence Detect Pin Arrangement (HB56H232)
Function Pin No. 67 68 69 70 Pin name PD1 PD2 PD3 PD4 50 ns NC NC VSS VSS 60 ns NC NC NC NC 70 ns NC NC VSS NC
Presence Detect Pin Arrangement (HB56H132)
Function Pin No. 67 68 69 70 Pin name PD1 PD2 PD3 PD4 50 ns VSS VSS VSS VSS 60 ns VSS VSS NC NC 70 ns VSS VSS VSS NC
4
HB56H232 Series, HB56H132 Series
Block Diagram (HB56H232)
RAS0 CAS0 CAS1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OE LCAS UCAS RAS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OE LCAS UCAS RAS RAS1
D0
D2
RAS2 CAS2 CAS3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LCAS UCAS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OE RAS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OE LCAS UCAS RAS
RAS3
D1
D3
A0 - A9 WE VCC C0 - C9 VSS
A0 - A9(D0 - D3) WE(D0 - D3) VCC(D0 - D3) VSS(D0 - D3) *D0 - D3 : HM5118165
5
HB56H232 Series, HB56H132 Series
Block Diagram (HB56H132)
RAS0 CAS0 CAS1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OE LCAS UCAS RAS
D0
RAS2 CAS2 CAS3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OE LCAS UCAS RAS
D1
A0 - A9 WE VCC C0-C7 VSS
A0 - A9(D0, D1) WE(D0, D1) VCC(D0, D1) VSS(D0, D1) *D0, D1 : HM5118165
6
HB56H232 Series, HB56H132 Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 2 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.75 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
7
HB56H232 Series, HB56H132 Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56H232)
50 ns Parameter Operating current Standby current 60 ns 70 ns Notes 1, 2 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 410 -- 8 -- 350 -- 8 -- 310 mA t RC = min 8 mA TTL interface, RAS, CAS = VIH, Dout = High-Z mA CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z mA CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z 2 1
--
4
--
4
--
4
Standby current (L-version) I CC2
--
0.6
--
0.6 --
0.6
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
410 -- 20 --
350 -- 20 --
310 mA t RC = min 20 mA RAS = VIH, CAS = VIL, Dout = enable
390 -- 380 -- 2 --
350 -- 340 -- 2 --
310 mA t RC = min 300 mA t HPC = min 2 mA CMOS interface, Dout = High-Z, CBR refresh: t RC = 125 s, t RAS 0.3 s A A 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 4
Battery backup current I CC10 (Standby with CBR refresh) (L-version)
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
-10 10 -10 10
-10 10 -10 10
-10 10 -10 10
2.4 VCC 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 0 0.4 V
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
8
HB56H232 Series, HB56H132 Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56H132)
50 ns Parameter Operating current Standby current 60 ns 70 ns Notes 1, 2 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 400 -- 4 -- 340 -- 4 -- 300 mA t RC = min 4 mA TTL interface, RAS, CAS = VIH, Dout = High-Z mA CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z mA CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z 2 1
--
2
--
2
--
2
Standby current (L-version) I CC2
--
0.3
--
0.3 --
0.3
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
400 -- 10 --
340 -- 10 --
300 mA t RC = min 10 mA RAS = VIH, CAS = VIL, Dout = enable
380 -- 370 -- 1 --
340 -- 330 -- 1 --
300 mA t RC = min 290 mA t HPC = min 1 mA CMOS interface, Dout = High-Z, CBR refresh: t RC = 125 s, t RAS 0.3 s A A 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 4
Battery backup current I CC10 (Standby with CBR refresh) (L-version)
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
-10 10 -10 10
-10 10 -10 10
-10 10 -10 10
2.4 VCC 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 0 0.4 V
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
9
HB56H232 Series, HB56H132 Series
Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56H232)
Parameter Input capacitance (Address) Input capacitance (WE) Input capacitance (RAS) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 40 48 27 34 34 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56H132)
Parameter Input capacitance (Address) Input capacitance (WE) Input capacitance (RAS) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 30 34 27 27 27 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
10
HB56H232 Series, HB56H132 Series
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) *1, *2 , *18
Test Conditions * * * * * Input rise and fall times: 2 ns Input level: 0 V, 3.0V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, and Refresh Cycles (Common parameters)
50 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time CAS delay time from Din Transition time (rise and fall) Refresh period (1,024 cycles) Refresh period (1,024 cycles) (L-version) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t DZC tT t REF t REF 84 30 7 50 7 0 7 0 7 11 9 10 35 5 0 2 -- -- Max -- -- -- 60 ns Min 104 40 10 Max -- -- -- 70 ns Min 124 50 13 Max -- -- -- Unit ns ns ns Notes
10000 60 10000 10 -- -- -- -- 37 25 -- -- -- -- 50 16 128 0 10 0 10 14 12 13 40 5 0 2 -- --
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- 50 16 128 0 10 0 13 14 12 13 45 5 0 2 -- --
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- 50 16 128 ns ns ns ns ns ns ns ns ns ns ns ms ms 5 3 4
11
HB56H232 Series, HB56H132 Series
Read Cycle
50 ns Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output buffer turn-off time CAS to Din delay time Output data hold time from RAS Output buffer turn-off time to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS to next CAS delay time Symbol Min t RAC t CAC t AA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OFF t CDD t OHR t OFR t WEZ t WED t RDD t RNCD -- -- -- 0 0 50 5 25 15 0 3 -- 13 3 -- -- 13 13 50 Max 50 13 25 -- -- -- -- -- -- -- -- 13 -- -- 13 13 -- -- -- 60 ns Min -- -- -- 0 0 60 5 30 18 0 3 -- 15 3 -- -- 15 15 60 Max 60 15 30 -- -- -- -- -- -- -- -- 15 -- -- 15 15 -- -- -- 70 ns Min -- -- -- 0 0 70 5 35 23 0 3 -- 18 3 -- -- 18 18 70 Max 70 18 35 -- -- -- -- -- -- -- -- 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19 19 19 11, 19 10 10 Notes 6, 7 7, 8, 15 7, 9, 15
Write Cycle
50 ns Parameter Write command setup time Write command hold time Write command pulse width Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t DS t DH 0 7 7 0 7 Max -- -- -- -- -- 60 ns Min 0 10 10 0 10 Max -- -- -- -- -- 70 ns Min 0 13 10 0 13 Max -- -- -- -- -- Unit ns ns ns ns ns 13 13 Notes 12
12
HB56H232 Series, HB56H132 Series
Refresh Cycle
50 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min t CSR t CHR t RPC 5 7 5 Max -- -- -- 60 ns Min 5 10 5 Max -- -- -- 70 ns Min 5 10 5 Max -- -- -- Unit ns ns ns Notes
EDO Page Mode Cycle
50 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low Symbol Min t HPC t RASP t CPA t CPRH t DOH 20 -- -- 28 3 28 Max -- 60 ns Min 25 Max -- 70 ns Min 30 Max -- Unit Notes ns 16 14 7, 15
100000 -- 28 -- -- -- -- 35 3 35
100000 -- 35 -- -- -- -- 40 3 40
100000 ns 40 -- -- -- ns ns ns ns
7, 15
Read command hold time from CAS t RCHC precharge
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD tRCD (max) + tAA (max) - tCAC (max), then access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 8. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 9. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. Early write cycle only (tWCS tWCS (min)). 13. These parameters are referred to CAS leading edge in early write cycles. 14. t RASP defines RAS pulse width in EDO page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA.
13
HB56H232 Series, HB56H132 Series
16. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. 17. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF. 20. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
14
HB56H232 Series, HB56H132 Series
Notes concerning 2CAS control
1. In one memory cycle, activate both of 2CASs (CAS0 and CAS1 (or CAS2 and CAS3)) or only one of them or neither of them. 2. If the different CASs are activated in the consecutive page cycles, t UL the period that both CASs are high, should be keep tCP spec (tCP min tUL).
Example RAS
CAS0 (CAS2)
CAS1 (CAS3)
1st cycle
tUL
2st cycle
15
HB56H232 Series, HB56H132 Series
Timing Waveforms*20
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z t CAC t AA t RAC t CLZ
t OFF t OH t OFR t OHR t WEZ
Dout
Dout
16
HB56H232 Series, HB56H132 Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column t WP t WCS t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
17
HB56H232 Series, HB56H132 Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP t RPC t CRP t RP
CAS
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
18
HB56H232 Series, HB56H132 Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR

Address t OFR t OFF Dout High-Z 19
CAS
HB56H232 Series, HB56H132 Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD t CHR t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t RAL t CAH
Column
, *
WE t DZC t WED High-Z t CDD t RDD Din t CAC t AA t WEZ t RAC t CLZ t OFF t OH Dout Dout t OFR t OHR
t RCS
t RRH t RCH
20
HB56H232 Series, HB56H132 Series
EDO Page Mode Read Cycle
t RP t RASP tT CAS t RCS
WE
t RNCD
RAS
t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP
t CSH t CAS t RCHR
t CP
t HPC t CAS
t CP
RSH
tCAS t RRH t RCH
t RCH t RCS
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z
" !
tCAC tAA tAA tCAC tWEZ tCPA tAA tCAC t AA t CAC tRAC tDOH tDOH tOFF tOH
Dout
tCPA
tCPA
tOFR tOHR
Dout 1
Dout 2
Dout 3
Dout 4
21
HB56H232 Series, HB56H132 Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1 t WP t WCS t WCH
Column 2 t WP t WCS t WCH
Column N t WP t WCS t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
22
HB56H232 Series, HB56H132 Series
Physical Outline
HB56H232B/SB Series
Unit: mm inch Front side 107.95 4.25 101.19 3.98 2-O 3.175 0.125 R1.57 R0.062 6.35 0.25 2.03 0.08 6.35 0.25 9.14 max 0.36
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
1 72 A 1.27 typ. 0.05 44.45 1.75 R1.57 R0.062 6.35 0.25 44.45 1.75
,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,
10.16 0.40 25.40 1.00
2.54 min. 0.10
+ 0.10 1.27 - 0.08 + 0.004 0.05 - 0.003
Back side 1
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Deteil A
2.54 min 0.10 1.04 0.03 0.041 0.001
0.25 max 0.01
3.17 min 0.125
5.72 min 0.225
72
23
HB56H232 Series, HB56H132 Series
HB56H132B/SB Series
Unit: mm inch Front side 107.95 4.25 101.19 3.98 2-O 3.175 0.125 R1.57 R0.062 6.35 0.25 2.03 0.08 6.35 0.25 5.28 max 0.208
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 72
A 1.27 typ. 0.05 44.45 1.75 R1.57 R0.062 72 1 6.35 0.25 44.45 1.75
2.54 min. 0.10
10.16 0.40 25.40 1.00
,, ,, ,, ,, ,, ,, ,,
+ 0.10 1.27 - 0.08 + 0.004 0.05 - 0.003
Back side
Deteil A
2.54 min 0.10 1.04 0.03 0.041 0.001
0.25 max 0.01
24
3.17 min 0.125
HB56H232 Series, HB56H132 Series
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Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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HB56H232 Series, HB56H132 Series
Revision Record
Rev. 1.0 2.0 Date Contents of Modification Drawn by Approved by S. Tsukui K. Tsuneda Dec. 27, 1996 Initial issue May. 16, 1997 (referred to HM5118165 rev 3.0) Addition of Access time 50 ns DC Characteristics I CC7 Max : 380/ 340 mA to 340/ 300 mA (HB56H232) I CC7 Max : 370/ 330 mA to 330/ 290 mA (HB56H132) AC Characteristics t RCD Min : 20/ 20 ns to 14/ 14 ns t RAD Min : 15/ 15 ns to 12/ 12 ns t RSH Min : 15/ 18 ns to 13/ 13 ns t RPC Min : 0/ 0 ns to 5/ 5 ns
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