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CDB5394 CDB5396/7
Evaluation Board for CS5394 and CS5396/7
Features General Description
The CDB5394, CDB5396 and CDB5397 evaluation boards are an excellent means for quickly evaluating the CS5394, CS5396 and CS5397 24-bit, stereo A/D converters. Evaluation requires a digital signal processor, a low distortion analog signal source and a power supply. Analog inputs are provided via XLR connectors for both channels. Also included is a CS8404A digital audio interface transmitter which generates AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The digital audio data is available via RCA phono and optical connectors. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development. ORDERING INFORMATION: CDB5394, CDB5396, CDB5397
l Demonstrates recommended layout and
grounding arrangements l CS8404A generates AES/EBU and/or IEC 958 compatible digital audio l Buffered serial output interface l Digital and analog patch areas l On-board or externally supplied system timing
Preliminary Product Information
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
MAR `98 DS258DB2 1
CDB5394 CDB5396/7
OVERVIEW CDB5394/96/97 System
The CDB5394/96/97 evaluation boards are an excellent means of quickly evaluating the CS5394, CS5396 or CS5397. The CS8404A digital audio interface transmitter provides an easy interface to digital audio signal processors, including the majority of digital audio test equipment. The evaluation board has been designed to accept an analog input and provide optical and coaxial digital outputs. The evaluation board also allows the user to access clocks and data through a 10-pin header for system development. The CDB5394/96/97 schematic has been partitioned into 7 schematics shown in Figures 2 through 8. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the connections between the partitioned schematics. leased when the PDN switch is released. A calibration sequence should be manually initiated by depressing the CAL switch (S2) following powerdown.
Power-Down and Calibration - Control Port Mode for CDB5396/97 Only
Power-down and calibration are available only through the control port. The calibration and power-down buttons on the evaluation board are ignored when configured in the Control Port mode.
Supplied Control Port Commands for CDB5396/97
The evaluation board includes a set of DOS files which allow communication through a PC parallel port to the evaluation board. The supplied commands include: cal64x.bat - Performs a calibration and initialization sequence and sets the CS5396/97 into the 64X oversampling mode. cal128x.bat - Performs a calibration and initialization sequence and sets the CS5396/97 into the 128X oversampling mode. rdi2c.exe - This routine returns the value located in the register pointed to by . The value is in hex and the value returned is in hex. wri2c.exe - This routine writes the value of into the register pointed to by . Both values are in hex. rst.exe - Sends a reset command to the device. mode128x.bat - Sets the device into the 128X oversampling mode. The cal128x.bat command includes this sequence. mode64x.bat - Sets the device into the 64X oversampling mode. The cal64x.bat command includes this sequence.
Power Supply Circuitry and Grounding
Power is supplied to the evaluation board by six binding posts as shown in Figure 8. +5VA provides 5 Volt power to the converter, VCOM buffer and the crystal oscillator. The +/-12V binding posts provide power to the analog input buffer. +5VD supplies 5 Volt power to the digital section of the board. Z1-Z4 are transient suppression diodes which also provide protection from incorrectly connected power supply leads.
Configuration for Stand-Alone or Control Port Mode
Refer to Tables 2-4 for the jumper settings required to configure the evaluation board.
Power-Down and Calibration - Stand alone Mode
The CS5394 and CS5396/97 in Stand-Alone mode are placed into the power-down mode simply by depressing the PDN switch (S1). Power-down is re-
2
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CDB5394 CDB5396/7
gnd.bat - Disconnects the analog modulators from the input pins and attaches the modulator inputs to the internal common mode voltage. ungnd.bat - Disconnects the analog modulators from the internal common mode voltage and attaches the modulator inputs to the input pins. The CS5394/96/97 are able to withstand input currents of 100 mA maximum, as stated in the CS5394 and CS5396/7 data sheets. The OPA627 op-amp is not able to deliver 100 mA, so input protection diodes are not required. However, protection diodes are recommended if there is a possibility that overrange signals could be applied at the ADC inputs which exceed 100 mA. Refer to the Crystal application note, "AN10: A/D Converter Input Protection Techniques."
General Comments on the Parallel Port
The evaluation board will be partially powered through the PC cable when the supplies to the evaluation board are off. This will affect the RC timing circuit which places the CS5396/97 into the Control Port mode. It is required that the evaluation board go through the power-up sequence without the cable to the PC connected.
CS5394 and CS5396/7 A/D Converters
The CS5394/96/97 A/D converters are shown in Figure 2. A description of these devices is included in the CS5394 and CS5396/7 datasheets.
Input Buffer
The differential input circuit shown in Figure 4 is well-suited for the CS5394/96/7 in professional applications. The circuit will accept a differential or single-ended signal of either polarity and provide a differential signal with the proper DC offset to the CS5394 or CS5396/97. The circuit also incorporates 6 dB of attenuation to scale down professional input levels to the input voltage range of the CS5394/96/97. A nominal input level of 13 Volts rms to the evaluation board will achieve a full scale digital output from the CS5394/96/97. The common mode rejection of the system is limited by the passive component matching of the input buffer circuit. The analog input connector is a standard female XLR with Pin 2 positive, Pin 3 return, and Pin 1 shield. R1, R5, R16 and C65 form an RC network which provides anti-alias filtering and the optimum source impedance for the CS5394/96/97 right channel inputs. R2, R3, R15 and C66 duplicate this function for the left channel. Notice that this circuit also provides approximately 13.25 dB attenuation to lower the noise contributed from the analog input buffer.
CS8404A Digital Audio Interface
Figure 4 shows the circuitry for the CS8404A digital audio interface transmitter. The CS8404A can implement AES/EBU, S/PDIF, and EIAJ-340 interface standards. The Digital Interface Format for the transmitter must be set to match the format chosen for the CS5394 or CS5396/7 as defined in Tables 2-4. SW2 provides 8 DIP switches to select various modes and bits for the CS8404A; switch definitions and the default settings for SW2 are listed in Tables 5-6. Digital outputs are provided on an RCA connector via an isolation transformer and on an optical transmitter. For more detailed information on the CS8404A and the digital audio standards, see the CS8403A/CS8404A data sheet.
I/O Port for Clocks and Data
A serial output interface is provided on I/O Port_1, as shown in Figure 6. When I/O Port is set to the MASTER position, MCLK, SCLK, LRCK and SDATA are outputs from I/O Port. When I/O Port is in the SLAVE position, MCLK and SDATA are outputs, while SCLK and LRCK become inputs. Hence, in SLAVE mode, the SCLK and LRCK signals must be externally derived from MCLK to run the ADC. All signals are buffered in order to isolate the converter from external circuitry. Note that the
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CDB5394 CDB5396/7
CS5394/96/97 must also be properly configured for Slave or Master mode. MCLK must be divided by either 2 or 4 depending on the mode of operation. Refer to Tables 4-6 for the proper jumper selection.
CS8404A Format Configuration
The CS5394/96/97 supports two Digital Interface Formats for both master and slave configurations. Format 0 has valid data on the rising edge of SCLK and the CS8404A has no corresponding mode. However, inverting SCLK so that data is valid on the falling edge of SCLK will make Format 0 of the CS5394/96/97 match Format 1 of the CS8404A. Jumpers are available to configure the CS8404A to Format 1 and perform inversion of SCLK. See Tables 4-6. Digital Interface Format 1 is the I2S compatible mode and matches Format 4 of the transmitter. Refer to Tables 4-6 for jumper positions.
Grounding and Power Supply Decoupling
The CS5394/96/97 require careful attention to power supply and grounding arrangements to optimize performance. The CS5394/96/97 is positioned over the analog ground plane. This layout technique is used to minimize digital noise and to insure proper power supply matching/sequencing. The decoupling capacitors are located as close to the ADC as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise effects. The evaluation board uses separate analog and digital ground planes which are joined at the converter. This arrangement isolates the analog circuitry from the digital logic.
CS8404A MCLK Generation
The crystal oscillator (U5) is either 256x for the 64x oversampling mode or 512x for the 128x oversampling mode. However, the CS8404A requires a master clock frequency of 128x Fs. Therefore, the
4
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CDB5394 CDB5396/7
CONNECTOR +5VA +5VD 12V AGND DGND AINL AINR LRCK, SCLK MCLK SDATA coaxial output optical output
INPUT/OUTPUT input input input input input input input input/output output output output output
SIGNAL PRESENT +5 Volts for analog section +5 Volts for digital section 12 Volts for analog input Analog ground connection from power source Digital ground connection from power source Left channel differential/single ended analog input Right channel differential/single ended analog input I/O for serial and left/right clocks Master clock output Serial data output CS8404A digital output via transformer CS8404A digital output via optical transmitter
Table 1. System Connections Jumper HDR1 HDR7 HDR8 HDR10 HDR11 SDATA I/O Port 8404A Mode 1 Mode 2 Mode 3 CS8404A CS5396/97 Purpose Sets the proper pull-up for the parallel port Sets the proper pull-up for the parallel port Sets the proper pull-up for the parallel port Selects Stand-Alone or Control Port mode Selects I2C or SPI mode for CS5396/97 control port Selection of data source for output from the SPDIF and I/O port I/O port Slave or Master selection Sets CS8404A data format selection for CS5396/97 compatibility. All jumpers must be set to either I2S or LJ and be compatible with the CS5396/97 data format. MCLK divide for CS8404 and CS5396/97 compatibility Supports a future function of the CS5396/97 Position High Low High Low High Low High Low High Low 1 2 Slave Master I2S LJ Function Selected Selects a 2k pull-up for I2C compliance Invalid selection for uC mode Selects a 2k pull-up for I2C compliance Invalid selection for uC mode Selects a 2k pull-up for I2C compliance Invalid selection for Control Port mode Selects Control Port Mode Invalid selection for Control Port Mode Selects I2C mode Selects SPI Mode Selects SDATA1 Selects SDATA2 LRCK and SDATA are inputs to the port. LRCK and SDATA are outputs from the port I2S data format selected Left Justified data format selected
128 x 64 x High Low
Divide MCLK by 4 for 128x oversampling mode Divide MCLK by 2 for 64x oversampling mode Invalid selection Should be set LOW
Bold indicates default settings
Table 2. CDB5396 and CDB5397 Control Port Mode jumper Setting
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5
CDB5394 CDB5396/7
Jumper HDR1 HDR7 HDR8 HDR10 HDR11 SDATA I/O Port 8404A Mode 1 Mode 2 Mode 3 CS8404A CS5396/97 Purpose Secondary effect on power-down implementation CS5396/97 digital data format selection CS5396/97 Master or Slave mode selection Selects Stand-alone or Control Port mode Selects polarity of power-down Selection of Data source for output from the SPDIF and I/O port I/O port Slave or Master selection Position High Low High Low High Low High Low High Low 1 2 Slave Master I2S LJ Function Selected Invalid selection for Stand-alone Mode Must be set low for operation Selects I2S data format Selects Left justified data format Selects Slave Mode Selects Master Mode Selects Control Port Mode Selects Stand-alone Mode Must be set High Invalid selection, CDB will not function Selects SDATA1 Selects SDATA2 LRCK and SDATA are inputs to the port LRCK and SDATA are outputs from the port I2S data format selected Left Justified data format selected
Sets CS8404A data format selection for CS5396/97 compatibility. All jumpers must be set to either I2S or LJ and be compatible with the CS5396/97 data format (HDR7) MCLK divide for CS8404 and 128 x Divide MCLK by 4 for 128x oversampling mode CS5396/97 compatibility 64 x Divide MCLK by 2 for 64x oversampling mode Supports a future function of the High Invalid selection CS5396/97 Low Should be set LOW Table 3. CDB5396 and CDB5397 Stand-Alone Mode Jumper Settings Purpose Secondary effect on power-down implementation CS5394 digital data format selection CS5394 Master or Slave mode selection Selects Stand-alone or Control Port mode Selects polarity of power-down Selection of Data source for output from the SPDIF and I/O port I/O port Slave or Master selection Sets CS8404A data format selection for CS5394 compatibility. All jumpers must be set to either I2S or LJ and be compatible with the CS5394 data format (HDR7) MCLK divide for CS8404 and CS5394 compatibility Supports a future function of the CS5396/97 Position High Low High Low High Low High Low High Low 1 2 Slave Master I2S LJ Function Selected Invalid selection for Stand-alone Mode Must be set low for operation Selects I2S data format Selects Left justified data format Selects Slave Mode Selects Master Mode Invalid selection for CS5394 Selects Stand-alone Mode Must be set High Invalid selection, CDB will not function Selects SDATA1 Invalid selection for CS5394 LRCK and SDATA are inputs to the port LRCK and SDATA are outputs from the port I2S data format selected Left Justified data format selected
Jumper HDR1 HDR7 HDR8 HDR10 HDR11 SDATA I/O Port 8404A Mode 1 Mode 2 Mode 3 CS8404A CS5396/97
128 x 64 x High Low
Invalid selection for CS5394 Divide MCLK by 2 for 64x oversampling mode Invalid selection Should be set LOW
Bold indicates default settings Table 4. CDB5394 Jumper Settings
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CDB5394 CDB5396/7
Switch# 6
8, 5
7
4
3
1, 2
0=Closed, 1=Open PRO=0 FC1, FC0 00 *0 1 10 11 C3 *1 0 C2 *1 0 C15 *1 0 C8, C9 11 10 01 *0 0
Comment Consumer Mode (C0=0) C24,C25,C26,C27 - Sample Frequency 0000 - 44.1 kHz 0100 - 48 kHz 1100 - 32 kHz 0000 - 44.1 kHz, CD Mode C3,C4,C5 - Emphasis (1 of 3 bits) 000 - None 100 - 50/15 s C2 - Copy/Copyright 0 - Copy Inhibited/Copyright Asserted 1 - Copy Permitted/Copyright Not Asserted C15 - Generation Status 0 - Definition is based on category code 1 - See CS8402A Data Sheet, App. A C8-C14 - Category Code (2 of 7 bits) 0000000 - General 0100000 - PCM encoder/decoder 1000000 - Compact Disk - CD 1100000 - Digital Audio Tape - DAT
Table 5. CS8404A Switch Definitions - Consumer Mode
Switch# 6 8
7, 4
5
3
1, 2
0=Closed, 1=Open PRO=1 CRE 0 1 C6, C7 11 10 01 00 C1 1 0 C9 1 0 EM1, EM0 11 10 01 00
Comment Professional Mode (C0=1) Local Sample Address Counter & Reliability Flags Disabled Internally Generated C6,C7 - Sample Frequency 00 - Not Indicated - Default to 48 kHz 01 - 48 kHz 10 - 44.1 kHz 11 - 32 kHz C1 - Audio 0 - Normal Audio 1 - Non-Audio C8,C9,C10,C11 - Channel Mode (1 of 4 bits) 0000 - Not indicated - Default to 2-channel 0100 - Stereophonic C2,C3,C4 - Emphasis (2 of 3 bits) 000 - Not Indicated - Default to none 100 - No Emphasis 110 - 50/15 s 111 - CCITT J.17
Table 6. CS8404A Switch Definitions - Professional Mode
DS258DB2
7
CDB5394 CDB5396/7
Fig. 5
Fig. 4
Fig. 2
Fig. 7
Fig. 6
Figure 1. System Block Diagram and Signal Flow
Fig. 3
8
DS258DB2
DS258DB2
MCLK
U? C64 100UF
AGND
4
C18 .1UF X7R
1 2 AINL+ AINL-
1 2 3 4 5
6
6 7 8 9 10 11
V+
5
AGND
CAL
VBIAS1
R18
1K
7
12
6
OPA2132U U15
VBIAS2
C8 10UF
C19 .1UF X7R
LRCK SCLK +5VD
13 14
VREF VCOM AGND AINL+ AINLADCTL MCLKA TST01 DACTL CAL VD+ DGND LRCK SCLK
AGND AINR+ AINRAGND VA+ VL+ LGND TST02 MCLKD PDN DFS S/\M SDATA1 SDATA2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
+5VA2 AINR+ AINR23
R17 C17 .1UF X7R
4.7
+5VA2
C61 .1UF X7R
C42 .01UF X7R
CS/PDN AGND CDIN/DFS CCLK/SMB SDATA2 SDATA1 +VD2
CS5396 +
3
R26
1K
1
2 8
AGND
C47 .01UF
X7R
C62 .1UF X7R
L4 FERRITE_BEAD
AGND
L6 FERRITE_BEAD R11 47K SN74HC125N
1
V+
GND +5VA SDATA
C28 X7R .1UF
AGND
HDR10
1
SDATA
HI LO
R13
+5VD
1
LO HI
HDR2
6
5
U12
4
+VD2
47K
R21 100K D1 BAT85 C67 100UF 25V
GND2
R6 47K
GND2
CDB5394 CDB5396/7
Figure 2. CS5394 and CS5396/7 Connections
9
FSYNC
C37 10UF
GND
C22 .1UF X7R TP11 TP1
VD+ GND
SDATA
19
SCK
C
*
TP6
GND
TP5 11
21
EM0/C9 EM1/C8
14 13
U U14 M0
+5VD
16 XFR_PE_67129600 TR1
5
SW_DIP_8
/RST CS8404A_CS TXP
MCK
OPEN
10
+5VD
C23 .01UF VCC
1 14
U11
2
GND
SN74HC04N GND
7
GND SCLK
8404_MODE_3
1
LEFT JUSTIFIED I2S
LRCK
7
SDATA
8 6
+5VD
24 1
+5VD
RN4 47K
CRE/FC1 C7/C3 PRO
2 3 4 12
18
15
TP2
CBL C1/FC0 V C6/C2 C9/C15
SW2
9
TP3
TP4 10
8 7 6 5 4 3 2 1
GND
20
22
M1 M2
C50
.1UF R50 X7R
374 R56 90.9
J3
4 1 3 2 4
3
23
HI
8404_MODE_2
1
+5VD
TXN
17
NC
HI
8404_MODE_1
1
1
6 2
5
CON_RCA_RA
M0 LO GND LO
M2 GND +5VD
4 3
TOTX173
5
GND GND
GND
GND
CDB5394 CDB5396/7
R20
8.2K
2 1 6
+5VD
GND
OPT1
GND
U1 74HC74A C27 X7R .1UF
GND +5VD
4
128X
5 HDR3
1
U1 74HC74A
10
+5VD
3 2
S C1
+5VD
11 12
S C1
9
1D
1
6
64X +5VD
1D
13
8
R
R
MCLK
DS258DB2
Figure 3. CS8404A Digital Audio Transmitter and Connections
CDB5394 CDB5396/7
+12V +12V
C53 V+
2 7
XR7 .1UF
AGND ANALOG
R28 1M
ANALOG
3
U2 OPA627AP
6
R5
187
AINR+
R47
ANALOG
7.77K
0.1%
+ V4 15
-12V
C52 C9 100UF 25V C14 100PF NPO R46 7.77K
0.1%
XR7 .1UF
R45 10K 0.1%
C12 100PF NPO
AGND
C4 R7
10PF NPO 1M
+12V
ANALOG ANALOG ANALOG
2
C54
.1UF X7R
7
ANALOG
R16 100
C65 3300PF COG
AGND ANALOG
3
U4 OPA627AP
6
V+
2
+
3
J2 XLR C13 100PF NPO C55
VBIAS1
1
-12V
51
4
V-
C48 X7R .1UF R44 10K 0.1%
AGND ANALOG
.1UF X7R C34
+12V
C30 470UF 16V
C31 100UF R49 25V 7.77K
0.1%
C11 100PF NPO
ANALOG
R48 7.77K
0.1%
V+
2
7
3
U3 OPA627AP
6
AGND
AGND
AGND
X7R .1UF
AGND
ANALOG
R1
187
AINR-
+
4 15
R25 1M
+12V AGND
C70 470UF
-12V +12V
V.1UF X7R C35
+12V
-12V
16V
C59 C69 470UF 1M R27 16V
-12V ANALOG
3
XR7 .1UF
AGND
V+
2
7
+ V4
AGND U6 OPA627AP ANALOG
6
R3
187
AINL+
R60
7.77K
0.1%
15
-12V
C58 C15 100UF 25V C44 100PF NPO R59 7.77K
0.1%
XR7 .1UF
R57 10K 0.1%
ANALOG
C45 100PF NPO
C26 R4
10PF AGND NPO 1M
ANALOG
ANALOG
.1UF X7R C36 U7 OPA627AP
7
+12V
R15 100
C66 3300PF COG
AGND
V+
2
2 3
+
3
J1 XLR
ANALOG
6
1
C46 100PF NPO
AGND
VBIAS2
C39
51
4
V-
C56 X7R .1UF
AGND
ANALOG
ANALOG
.1UF X7R
-12V
C16 100UF R64 25V 7.77K
0.1%
C43 100PF NPO
AGND
R58 10K 0.1%
AGND
C25 470UF 16V
R61 7.77K
0.1%
ANALOG
R24 1M
+12V
.1UF X7R V+
7
C40 U8 OPA627AP ANALOG
6
AGND
R2
187
2
AINL-
-12V
3
+
4 15
V.1UF X7R C38
Figure 4. Analog Input Buffer
AGND
-12V
DS258DB2
11
12
CDB5394 CDB5396/7
DS258DB2
Figure 5. P.C. Parallel Interface
CDB5394 CDB5396/7
Figure 6. I/O Interface for Clocks & Data
Figure 7. CAL Circuitry
DS258DB2
13
CDB5394 CDB5396/7
L1 FERRITE_BEAD
+5VD
L2 FERRITE_BEAD
+VD2
DIGITAL +5VD
J4
C60 .1UF X7R
C57 47UF
Z4 P6KE6V8P
DIGITAL DGND
J9
C41 470UF 16V
C10 .1UF X7R
C24 470UF 16V X7R
C20 .1UF
GND
TO GND2
+12V
J7
+12V
Z1 P6KE13
ANALOG
AGND
J8
C? 470UF 16V
C3 .22UF
Z2 P6KE13
-12V
J5
C? 470UF 16V
C2 .22UF
AGND -12V
L5 FERRITE_BEAD
+5VA1 +5VA
ANALOG
+5VA
J6
Z3 P6KE6V8P
C? 470UF 16V
AGND
C1 .22UF
L3 FERRITE_BEAD
+5VA2
Figure 8. Power Supply & Reset Circuitry
14
DS258DB2
CDB5394 CDB5396/7
Figure 9. CDB5394 and CDB5396/7 Component Silkscreen Side (top)
DS258DB2
15
CDB5394 CDB5396/7
Figure 10. CDB5394 and CDB5396/7 Component Silkscreen Side (bottom)
16
DS258DB2
CDB5394 CDB5396/7
Figure 11. CDB5394 and CDB5396/7 Component Copper Side (top)
DS258DB2
17
CDB5394 CDB5396/7
Figure 12. CDB5394 and CDB5396/7 Component Copper Side (bottom)
18
DS258DB2
* Notes *

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