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HB526R864ESN-10H/10/12
4,194,304-word x 64-bit (Non Parity)x 2-bank Synchronous Dynamic RAM Module
ADE-203-671A (Z) Rev. 1.1 Feb. 20, 1997 Description
The HB526R864ESN belongs to 8 byte DIMM (Dual In-line Memory Module) family, and has been developed a as optimized main memory solution for 8 byte processor applications. The HB526R864ESN is a 4M x 64 x 2 banks Synchronous Dynamic RAM module, mounted 32 pieces of 16-Mbit SDRAM (HM5216405TB) sealed in TCP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). An outline of the HB526R864ESN is 168-pin socket type package (dual lead out). Therefore, the HB526R864ESN makes high density mounting possible without surface mount technology. The HB526R864ESN provides common data inputs and outputs. Decoupling capacitors are mounted beside each TCP on the module board.
Features
* 168-pin socket type package (dual lead out) Lead pitch : 1.27 mm * 3.3 V ( 0.3 V) power supply * Clock frequency : 100 MHz / 83 MHz * JEDEC standard outline unbuffered 8-byte DIMM * LVTTL interface * Data bus width: x 64 (non parity)bit * Single pulsed RAS * 2 Banks can operate simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length: 1/2/4/8/full page * Programmable burst sequence Sequential/interleave * Full page burst length capability Sequential burst Burst stop capability * Programmable CAS latency: 1/2/3 * 4096 refresh cycles: 64 ms
HB526R864ESN-10H/10/12
* 2 variations of refresh Auto refresh Self refresh
Ordering Information
Type No. HB526R864ESN-10H HB526R864ESN-10 HB526R864ESN-12 Frequency 100 MHz 100 MHz 83 MHz Package Contact pad 168-pin dual lead out socket type Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin name VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13
Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
Pin name VSS NC S2 DQMB2 DQMB3 NC VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD
Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
Pin name VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45
Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143
Pin name VSS CKE0 S3 DQMB6 DQMB7 NC VDD NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VDD
2
HB526R864ESN-10H/10/12
Pin Arrangement (cont)
Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name VDD DQ14 DQ15 NC NC VSS NC NC VDD WE DQMB0 DQMB1 S0 NC VSS A0 A2 A4 A6 A8 A10 NC VDD VDD CK0 Pin No. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC NC SDA SCL VDD Pin No. 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name VDD DQ46 DQ47 NC NC VSS NC NC VDD CAS DQMB4 DQMB5 S1 RAS VSS A1 A3 A5 A7 A9 A11 NC VDD CK1 NC Pin No. 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
3
HB526R864ESN-10H/10/12
Pin Description
Pin name A0 to A11 Function Address input Row address Column address Bank select address DQ0 to DQ63 S0 to S3 (CS0 to CS3) RAS CAS WE DQMB0 to DQMB7 (DQM0 to DQM7) CK0 to CK3 (CLK0 to CLK3) CKE0/CKE1 SDA SCL SA0 to SA2 VDD VSS NC Data-input/output Chip select Row address strobe Column address strobe Write enable Input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD Serial address input Power supply Ground No connection A0 to A10 A0 to A9 A11
4
HB526R864ESN-10H/10/12
Serial PD Matrix
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes utilized by module manufacturer Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Notes 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 None Normal (15.625 s) Self refresh CL = 3 21 256byte SDRAM 11 10 2 64 0 (+) 3.3 V CL = 3
Total number bytes in serial PD device 0 Memory type Number of row addresses Number of column addresses Number of DIMM banks Module data width Module data width(continued) 0 0 0 0 0 0
Module supply voltage/interface levels 0 System clock cycle time 10 ns 12 ns 1 1 1 1 0 1
10
Access time from clock 8 ns 9.5 ns
11 12
SDRAM DIMM configuration type Refresh rate/type
13 14 15
SDRAM module attributes SDRAM device attributes: General SDRAM device attributes: minimum clock delay, back-to-back random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: CAS latency SDRAM device attributes: CS latency SDRAM device attributes: WE latency 0: Serial data, "driven Low" 1: Serial data, "driven High" Serial-PD Data is not protected.
0 0 0
0 0 0
0 0 0
0 0 0
0 1 0
0 1 0
0 1 0
0 0 1 1
16 17 18 19 20 Note:
1 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
1 0 0 0 0
1 0 1 0 0
1 1 1 0 0
1 0 0 1 1
1, 2, 4, 8, full page 2 2, 3 0 0
5
HB526R864ESN-10H/10/12
Block Diagram
RAS, CAS, WE S0 S1 CS DQMB0 4 R0 to R3 DQ0 to DQ3 DQM I/O0 to I/O3 D0 DQM I/O0 to I/O3 CS D16 DQMB4 DQ32 to DQ35 CS DQM D8 4 R32 to R35 I/O0 to I/O3 CS DQM DQ36 to DQ39 4 R36 to R39 I/O0 to I/O3 D9 DQM I/O0 to I/O3 DQM I/O0 to I/O3 CS D24
CS DQM DQ4 to DQ7 4 R4 to R7 I/O0 to I/O3 D1 DQM I/O0 to I/O3
CS D17
CS D25
CS DQMB1 DQ8 to DQ11 DQM 4 R8 to R11 I/O0 D2 to I/O3 CS DQM DQ12 to DQ15 S2 S3 CS DQMB2 DQ16 to DQ19 DQM D4 4 R16 to R19 I/O0 to I/O3 CS DQM DQ20 to DQ23 4 R20 to R23 I/O0 to I/O3 D5 DQM I/O0 to I/O3 DQM I/O0 to I/O3 4 R12 to R15 I/O0 to I/O3 D3 DQM I/O0 to I/O3 DQM
CS DQMB5 DQ40 to DQ43 DQM D18 I/O0 to I/O3 CS DQM D19 DQ44 to DQ47 4 R44 to R47 I/O0 to I/O3
CS DQM 4 R40 to R43 I/O0 D10 to I/O3 CS DQM D11 I/O0 to I/O3
CS D26 I/O0 to I/O3 CS D27
CS D20 DQMB6 DQ48 to DQ51
CS DQM D12 4 R48 to R51 I/O0 to I/O3 CS DQM DQ52 to DQ55 4 R52 to R55 I/O0 to I/O3 D13 DQM I/O0 to I/O3 DQM I/O0 to I/O3
CS D28
CS D21
CS D29
CS DQMB3 DQ24 to DQ27 DQM 4 R24 to R27 I/O0 D6 to I/O3 CS DQM DQ28 to DQ31 4 R28 to R31 I/O0 to I/O3 D7 DQM I/O0 to I/O3 DQM
CS DQMB7 DQ56 to DQ59 D22 I/O0 to I/O3 CS DQM D23 DQ60 to DQ63 4 R60 to R63 I/O0 to I/O3 Serial PD SCL
CS DQM 4 R56 to R59 I/O0 D14 to I/O3 CS DQM D15 I/O0 to I/O3 DQM
CS D30 I/O0 to I/O3 CS D31
A0 to A11 CKE0 VDD R200 CKE1 R100 CK0 R101 R102 CK1 R103 R104 CK2 R105 R106 CK3 R107
A0 to A11(D0 to D31) CKE (D0 to D15)
SCL U0 SDA A0 A1 A2
SDA
CKE (D16 to D31) CLK (D0, D16) CLK (D8, D24) CLK (D1, D17) CLK (D9, D25) CLK (D2, D18) CLK (D10, D26) CLK (D3, D19) CLK (D11, D27) CLK (D4, D20) CLK (D12, D28) CLK (D5, D21) CLK (D13, D29) CLK (D6, D22) CLK (D14, D30) CLK (D7, D23) CLK (D15, D31)
SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D31 : HM5216405 U0 : 24C02 C0 to C31 : 0.33 F R0 to R63, R100 to R107 : 10 R200 : 10k VDD
C0 to C31
VDD (D0 to D31) VSS (D0 to D31)
VSS
6
HB526R864ESN-10H/10/12
Command Operation, Mode Resistor Configuration and Operation
Refer to the HM5216405 Series data sheet.
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VDD Iout PT Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 16 0 to +65 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +65C)
Parameter Supply voltage Symbol VDD VSS Input high voltage Input low voltage VIH VIL Min 3.0 0 2.0 -0.3 Typ 3.3 0 -- -- Max 3.6 0 4.6 0.8 Unit V V V V 1, 2 1, 3 Notes 1
Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns
7
HB526R864ESN-10H/10/12
DC Characteristics (Ta = 0 to +65C, VDD = 3.3 V 0.3 V, V SS = 0 V)
HB526R864ESN -10H/-10 Parameter Operating current Standby current (Bank Disable) Symbol I CC1 I CC2 Min -- -- -- -- Max -12 Min Max Unit Test conditions Burst length = 1 t RC = min CKE = VIL, t CK = min CKE = VIL CLK = VIL or VIH Fixed CKE = VIH, NOP command t CK = min Notes 1, 2, 4 5 6 3
2320 -- 96 64 -- --
2000 mA 96 64 mA mA
1280 --
1120 mA
Active standby current (Bank active)
I CC3
-- --
224
--
224
mA
CKE = VIL, 1, 2 t CK = min, I/O = High-Z CKE = VIH, 1, 2, 3 NOP command t CK = min, I/O = High-Z t CK = min, BL = 4 1, 2, 4
1440 --
1280 mA
Burst operating current (CL = 2) (CL = 3) Auto refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage
I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL
-- -- -- -- -10 -10 2.4 0
2320 -- 3120 --
2000 mA 2640 mA
2080 -- 64 10 10 VDD 0.4 -- -10 -10 2.4 0
1760 mA 64 10 10 VDD 0.4 mA A A V V
t RC = min VIH VDD - 0.2 V 0 V VIL 0.2 V 0 Vin VDD 0 Vout VDD I/O = disable I OH = -2 mA I OL = 2 mA 7
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CLK cycles. 4. Input signal transition is once per one CLK cycle. 5. After power down mode, CLK operating current. 6. After power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current.
8
HB526R864ESN-10H/10/12
Capacitance (Ta = +25C, VDD = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (RAS, CAS, WE, CKE) Input capacitance (CS) Input capacitance (CLK) Input capacitance (DQM) Input/output capacitance (DQ0 to DQ63) Symbol CI1 CI2 CI3 CI4 CI5 CI/O1 Typ -- -- -- -- -- -- Max 180 180 60 60 40 27 Unit pF pF pF pF pF pF Notes 1, 3 1, 3 1, 3 1, 3 1, 3 1, 2, 3
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMB = VIH to disable Dout. 3. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to +65C, VDD = 3.3 V 0.3 V, V SS = 0 V)
HB526R864ESN -10H/-10 Parameter System clock cycle time (CL = 2) (CL = 3) CLK high pulse width CLK low pulse width Access time from CLK (CL = 2) (-10H) (CL = 2) (-10) (CL = 3) Data-out hold time CLK to Data-out low impedance Symbol t CK t CK t CKH t CKL t AC t AC t AC t OH t LZ Min 15 10 3 3 -- -- -- 3 0 -- 2 1 2 1 2 2 1 Max -- -- -- -- 9.0 9.5 8 -- -- 7 -- -- -- -- -- -- -- -12 Min 18 12 4 4 -- -- -- 3 0 -- 3 1 3 1 3 3 1 Max -- -- -- -- 12 12 9.5 -- -- 9 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 ns ns ns 1 1 1, 2 Unit ns Notes 1
CLK to Data-out high impedance (CL = 2, 3) t HZ Data-in setup time Data in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time t DS t DH t AS t AH t CES t CESP t CEH
9
HB526R864ESN-10H/10/12
AC Characteristics (Ta = 0 to 65C, VDD = 3.3 V 0.3 V, V SS = 0 V) (cont)
HB526R864ESN -10H/-10 Parameter Command setup time Command hold time Ref/Active to Ref/Active command period Active to precharge command period Active to precharge on full page mode Symbol t CS t CH t RC t RAS t RASC Min 2 1 90 60 -- 30 30 15 20 1 -- Max -- -- -- -12 Min 3 1 108 Max -- -- -- Unit ns ns ns 1 1 1 1 1 1 Notes 1 1
120000 72 120000 -- -- -- -- -- 5 64 36 36 18 24 1 --
120000 ns 120000 ns -- -- -- -- 5 64 ns ns ns ns ns ms
Active command to column command (same t RCD bank) Precharge to active command period The last data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period Notes: 1. 2. 3. 4. 5. t RP t RWL t RRD tT t REF
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is C L = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CKE rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures input
2.8 V V SS
output
80% 20%
DQ
50 +1.4 V CL
t
T
tT
10
HB526R864ESN-10H/10/12
Relationship Between Frequency and Minimum Latency
HB526R864ESN Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Symbol t RCD -10H/-10 100 10 3 9 6 3 2 2 2 5 9 3 -- 1 66 15 2 6 4 2 1 2 2 3 6 3 2 1 33 30 1 3 2 1 1 1 2 2 3 3 2 1 -12 83 12 3 9 6 3 2 2 2 5 9 3 -- 1 55 18 2 6 4 2 1 2 2 3 6 3 2 1 28 36 1 3 2 1 1 1 2 2 3 3 2 1 1 1 1 2 = [tDPL + tRP] = [tRC] Notes 1 = [tRAS + tRP] 1
Active command to active command t RC (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) t RAS t RP t DPL
Active command to active command t RRD (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CAS latency = 3) (CAS latency = 2) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CAS latency = 3) (CAS latency = 2) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CKE disable I SREX I APW I SEC I HZP I HZP I APR
I EP I EP I CCD I WCD I DID I DOD I CLE
-2 -- 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -- 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -1 1 0 0 2 1
11
HB526R864ESN-10H/10/12
Relationship Between Frequency and Minimum Latency (cont)
HB526R864ESN Parameter Frequency (MHz) tCK (ns) Register set to active command CS to command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = 3) (CAS latency = 2) Symbol t RSA I CDD I PEC I BSR I BSR -10H/-10 100 10 1 0 1 2 -- 3 -- 0 66 15 1 0 1 2 1 3 2 0 33 30 1 0 1 2 1 3 2 0 -12 83 12 1 0 1 2 -- 3 -- 0 55 18 1 0 1 2 1 3 2 0 28 36 1 0 1 2 1 3 2 0 Notes
Burst stop to output high impedance (CAS latency = 3) I BSH (CAS latency = 2) Burst stop to write data ignore I BSH I BSW
Notes: 1. t RCD to tRRD are recommended value. 2. When self refresh exit is executed, CKE should be kept "H" longer than l SREX from exit cycle.
12
HB526R864ESN-10H/10/12
Timing Waveforms
Read Cycle
t CK t CKH t CKL
, , , ,
, , ,

CLK
t RC VIH
CKE
t RCD
t RAS
t
RP
, , ,,, , , , ,,
CS
t CS t CH t CS t CH t CS t CH t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
RAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
WE
t AS t AH t AS t AH
t AS t AH
t AS t AH
t AS t AH t AS t AH
A11
t AS t AH t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
Address
t CS
t CH
DQM
DQ(input)
t AC
t AC
t AC
t HZ
DQ(output)
t AC
Bank 0 Active
Bank 0 Read
t LZ
t OH
t OH
t OH
t OH
Bank 0 Precharge
Burst length = 4 Bank0 Access = VIH or VIL
13
HB526R864ESN-10H/10/12
Write Cycle
,
,

, ,
t CK t CKH t CKL
CLK
t RC
VIH
CKE
t RCD
t RAS
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CS
, ,
RAS
t CS t CH t CS t CH t CS t CH t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
WE
t AS t AH t AS t AH
t AS t AH
t AS t AH
t AS t AH t AS t AH
A11
t AS t AH t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
Address
t CS
t CH
DQM
t DS t DH tDS
t DH t DS t DH t DS
t DH
DQ(input)
t RWL
DQ(output)
Bank 0 Active
Bank 0 Write
Bank 0 Precharge
Burst length = 4 Bank0 Access = VIH or VIL
14
HB526R864ESN-10H/10/12
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
,
A11(BS) Address
valid code R: b C: b C: b'
, ,, , , , , , , , ,, , ,
CLK CKE CS
VIH
RAS
CAS
WE
DQM
DQ(input)
b
b+3
b'
b'+1
b'+2
b'+3
DQ(output)
High-Z
t RP
t RSA
t RCD
Output mask
Precharge If needed
Mode Bank 1 register Active Set
Bank 1 Read
tRCD = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
15
HB526R864ESN-10H/10/12
Read Cycle/Write Cycle
0 1 2
,, , ,, , , , , , , , , , ,
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CS CKE
VIH

RAS CAS WE A11(BS) DQM Address R:a C:a R:b C:b C:b' C:b" DQ(output) a a+1 a+2 a+3 b b+1 b+2 b+3 b'
Bank 1 Read
Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
b'+1 b"
b"+1 b"+2 b"+3
DQ(input)
High-Z
Bank 0 Active
Bank 0 Read
Bank 1 Active
Bank 1 Bank 0 Read Precharge
Bank 1 Read
Bank 1 Precharge
CKE CS
VIH
RAS CAS
Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
WE
A11(BS)
Address DQM
R:a
C:a
R:b
C:b
C:b'
C:b"
DQ(output) DQ(input)
High-Z
a
a+1 a+2 a+3
Bank 1 Active
b
b+1 b+2 b+3 b'
Bank 0 Precharge
b'+1 b"
b"+1 b"+2 b"+3
Bank 0 Active
Bank 0 Write
Bank 1 Write
Bank 1 Write
Bank 1 Write
Bank 1 Precharge
16
HB526R864ESN-10H/10/12
Read/Single Write Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
,
DQM DQ(input) a b c DQ(output) a a+1 a+3
Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge
,,, , , , , , , , , , , ,
CLK CKE CS
VIH
RAS CAS WE
A11(BS) Address DQM
R:a
C:a
R:b
C:a' C:a a
DQ(input)
DQ(output)
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Precharge
Bank 0 Active
Bank 0 Read
Bank 1 Active
Bank 0 Bank 0 Write Read
Bank 1 Precharge
CKE CS
VIH
RAS CAS WE
A11(BS) Address
R:a
C:a
R:b
C:a
C:b C:c
Read/Single write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
17
HB526R864ESN-10H/10/12
Read/Burst Write Cycle
0 CLK CKE CS RAS CAS WE A11(BS) Address DQM DQ(input) DQ(output)
Bank 0 Active Bank 0 Read Bank 1 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a
a a+1 a+2 a+3 a a+1 a+2
Clock Suspend
a+3
Bank 0 Write Bank 0 Precharge Bank 1 Precharge
CKE CS RAS CAS WE A11(BS) Address DQM DQ(input) DQ(output)
VIH
R:a
C:a
R:b
C:a
a a+1 a+2 a+3 a a+1
Bank 0 Active Bank 0 Read Bank 1 Active
a+3
Bank 0 Write Bank 0 Precharge
Read/Burst write cycle RAS-CAS delay = 3 CAS Latency = 4 Burst Length = 4 = VIH or VIL
18
HB526R864ESN-10H/10/12
Full Page Read/Write Cycle

" ,, , " ! "
CLK CS CKE
VIH
RAS CAS
Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL
WE
A11(BS) Address DQM
R:a
C:a
R:b
DQ(output) DQ(input)
a
a+1
a+2
a+3
a-2
a-1
a
a+1
a+2
a+3
a+4
a+5
High-Z
Bank 0 Active
Bank 0 Read
Bank 1 Active
Burst stop
Bank 1 Precharge
CKE CS
VIH
RAS CAS
Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL
WE
A11(BS) Address DQM
R:a
C:a
R:b
DQ(output) DQ(input)
High-Z
a
a+1
a+2
a+3
a+4
a+5
a+6
a+1
a+2
a+3
a+4
a+5
Bank 0 Active
Bank 0 Write
Bank 1 Active
Burst stop
Bank 1 Precharge
19
HB526R864ESN-10H/10/12
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Self Refresh Cycle
CLK ISREX CKE CLK Low CS RAS CAS WE A11 (BS) Address DQM DQ(input) DQ(output) tRP
Precharge command If needed Self refresh entry command
A10x1
, ,, , , , , ,, ,, ,, , , ,, , ,
CLK CKE CS
VIH
RAS
CAS WE
A11(BS)
Address DQM
A10=1
R:a
C:a
DQ(input)
DQ(output)
High-Z
a
a+1
t RP
t RC
tRC
Precharge If needed
Auto Refresh
Auto Refresh
Active Bank 0
Read Bank 0
Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
High-Z tRC
Self refresh exit ignore command or No operation Next Self refresh entry clock command enable
tRC
Next Auto clock refresh enable
Self refresh cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 =VIH or VIL
20
HB526R864ESN-10H/10/12
Clock Suspend Mode
t CES t CEH t CES
,, , , ,, , ,, , , , , , ,,,
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE
,
Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
A11(BS) Address DQM R:a C:a R:b C:b DQ(output) DQ(input) a a+1 a+2 a+3 b b+1 b+2 b+3
High-Z
Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank1 Active Read suspend start
Read suspend end
Bank1 Read
Bank0 Precharge
Earliest Bank1 Precharge
CKE CS
RAS WE
CAS
Write cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
A11(BS) Address DQM
R:a
C:a R:b
C:b
DQ(output)
High-Z
DQ(input)
a
a+1 a+2
a+3 b
b+1 b+2 b+3
Bank0 Active
Active clock suspend start
Active clock Bank0 Bank1 supend end Write Active
Write suspend start
Write suspend end
Bank1 Bank0 Write Precharge
Earliest Bank1 Precharge
21
HB526R864ESN-10H/10/12
Power Down Mode
Precharge command If needed Power down entry Power down mode exit Active Bank 0
, , , , ,, , , ,,, ,, , , , , ,
CLK CKE CS
CKE Low
RAS CAS WE
A11(BS)
Address DQM
A10=1
R: a
DQ(input)
DQ(output)
High-Z
tRP
Power down cycle RAS-CAS delay=3 CAS latency=3 Burst length=4 = VIH or VIL
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
CLK
CKE CS RAS CAS WE
VIH
Address DQM DQ VIH
Valld
code
Valld
High-Z tRP All banks Auto Refresh Precharge tRC Auto Refresh tRC tRSA Mode register Bank active Set If needed
22
HB526R864ESN-10H/10/12
Physical Outline
Unit: mm / inch
Front side 133.35 5.250 3.00 0.118 127.35 5.014 Protective cover*1 4.80 max 0.189 max
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
C B 36.83 1.450 115.7 4.550 54.61 2.150 A 11.43 0.450
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.00 0.118
8.89 0.350
1.27 0.10 0.050 0.004
Back side 2 - 3.00 2 - 0.118
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Note: 1. Protective cover material will be Fe-Ni or stainless steel. Detail A Detail B Detail C 168 85
4.00 0.157
17.78 0.700
2.54 min 0.100 min
1.00
0.25 max 0.010 max
3.125 0.125 0.123 0.005
1.00 0.05 0.039 0.002
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
6.35 0.250 2.00 0.10 0.079 0.004
25.40 1.000
5.40 min 0.212 min
23
HB526R864ESN-10H/10/12
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
24
HB526R864ESN-10H/10/12
Revision Record
Rev. 1.0 1.1 Date Oct. 8, 1996 Contents of Modification Initial issue Drawn by T. Sugano Approved by K. Inoue
Feb. 20, 1997 Addition of HB526R864ESN-10H Series Correct error The type number of SDRAM in Block diagram : HM5216805 to HM5216405 AC Characteristics Addition of t AC (CL = 2) (HB526R864ESN-10H) max: 9.0/12 ns Change of symbol: t RWL to tDPL
25

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