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| CDB5180 Evaluation Board for the CS5180 Features l Buffered Description The CDB5180 is an evaluation board that expedites the laboratory characterization of the CS5180 A/D converter. The CS5180 is a 16-bit high speed delta-sigma converter with a serial output having an output word rate of up to 400 kHz. The board accepts single-ended or differential input signals and buffers the serial output of the CS5180 before sending it to a header for off-board use. The output header signals on the evaluation board are designed to be compatible with the CDBCapture+ board. An on-board 3 Volt regulator allows the CS5180 to be evaluated with either 3 or 5 Volt digital supplies. The converter can be operated with it's internal voltage reference although the layout makes provision for adding an external precision reference as a user-supplied option. ORDERING INFORMATION CDB5180 Evaluation Board Serial Data Output l Input Signal Conditioning Amplifiers l On-board 3 Volt regulator l Analog/Digital Patch Areas l Analog BNC Input Connector l Provision for optional precision voltage reference l Compatible with CDBCapture+ board l Provision for evaluation of CS5180 with internal digital filter enabled or disabled (onebit mode) I RESET SYNC RESET and SYNC CONDITIONING RESET CLOCK GENERATOR 25.6 MHz MCLK SYNC CS5180 AIN ANALOG SIGNAL CONDITIONING AIN+ AINSCLK SDATA SDATA FSO EXTERNAL PRECISION REFERENCE OPTION VREFOUT VREFIN BUFFERS 10 POS. SERIAL OUTPUT HEADER +15 V +5 VD -15 V 5 V DIGITAL +3 V REGULATOR +3 VD AGND +5 VA 5 V ANALOG DGND Preliminary Product Information Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved) DEC `98 DS259DB1 1 CDB5180 POWER SUPPLIES AND VOLTAGE REFERENCE Figure 1 illustrates the power supply and precision voltage reference circuits. The CDB5180 evaluation board has inputs for 4 regulated voltages, +5 Volts Digital, +5 Volts Analog, +15 Volts, and -15 Volts. As an option, one 5 Volt power supply may be used to power both the analog and digital portions of the converter. This is done by installing HDR17 and connecting the 5 Volt supply to post J7. An on-board 3 Volt regulator allows for the converter's digital circuitry to be powered from either 5 Volts or 3 Volts. This selection is achieved by setting header HDR13 to either the +5VD or +3VD position. The plus and minus 15 Volts are used to power the analog signal conditioning circuits external to the converter. The analog 5 Volt supply can be used to power a precision 2.5 Volt reference, an LT1019-2.5 or equivalent, which can JP1 JP2 JP3 +5 VD HDR13 AGND J8 Z1 1N6276A .1 F X7R C22 C3 + 68 F 2 1 GND 3 LT317AT VIN U7 HDR17 L1 FERRITE BEAD .1 F X7R C53 VOUT ADJ 1 2 .1 F X7R C21 +3 VD be substituted for the converter's on-board reference to achieve lower drift. The board is supplied with the external reference and it's passive components depopulated. If it is desired to use an external reference, then the following steps must be completed. 1) Remove zero-ohm resistor R32 and install a zero-ohm resistor in the R33 position. 2) Install the following components: U10, C38, C56, R22, C59, and R25. 3) Set the reference voltage to the desired value by adjusting potentiometer R22. The output of the internal reference is connected to the operational amplifiers through zero-ohm resistor R54. If it is desired to use the external reference to drive the signal conditioning circuits, then R54 must be removed and a zero-ohm resistor installed in position R55. L2 FERRITE BEAD HDR14 12 VCCIO VDDD R11 249 R12 392 GND + C2 68 F GND J7 Z4 P6KE6V8P J3 GND NOT POPULATED LT1019CN8_2P5 TP12 R55 0 R33 0 R22 CW 20 K R25 2.1 + C59 10 F +5 VA + C26 68 F +5 VA 2 IN OUT 6 TRIM 5 HIR 7 VREF_AMP FIGURE 4 VREFIN FIGURE 5 GND J4 Z2 1N6276A AGND .1 F X7R C57 C58 .1 F X7R AGND +15 V C38 10 F + C56 .1 F X7R C46 + 68 F AGND 3 GND TEMP U10 4 Z3 1N6276A J5 C52 68 F + AGND PRECISION VOLTAGE REFERENCE OPTION -15 V AGND Figure 1. Power Supplies and Voltage Reference 2 DS259DB1 CDB5180 CLOCK OSCILLATOR AND BUFFER Figure 2 illustrates the circuitry used to generate the clock signal MCLK that drives the CS5180. The board contains a 25.6 MHz nominal oscillator as well as a BNC connector for use with an external clock source. The on-board oscillator is buffered and inverted to form a complementary clock signal, MCLKB, that is used in the SYNC and RESET circuits. Selection of internal clock or external clock is done by setting header HDR3 to either the OSC or BNC position. Using the on-board oscillator will result in an output word rate of 400.0 kHz. INPUT SIGNAL CONDITIONING Figure 4 illustrates the circuitry used to condition the analog input signal. A single-ended input is fed in via the BNC connector to a pair of operational amplifiers. The signal is buffered and also inverted to form differential signals. These signals are then fed to two more op-amps where the voltage reference is added to each of them to bring the common mode voltage up to the range required by the converter. Potentiometer R41 is available to adjust the offsets on the two op-amp outputs to be equal, so that with zero volts in at J2, the converter reads zero. The two signals are then passed through an attenuating resistor network before being input to the converter. A 1.0 Volt peak-peak signal input at the BNC connector will result in nominal 0.2849 Volt peak-peak fully differential signals being applied between the AIN+ and AIN- pins of the converter. If the external signal is not single ended but is already differential, it can be input through connector J6 where it is capacitively coupled in and offset to the proper common mode value before being applied to the converter. The settings of HDR8 and HDR9 select whether the input signal will be input through the BNC connector as a single-ended signal or through J6 as a differential signal. To use the RESET AND SYNC CIRCUITS Figure 3 illustrates the circuits used for generating the chip RESET and SYNC signals. Two manual pushbuttons are provided for generating the RESET and SYNC signals, which are synchronized to the falling edge of the master clock by means of a flip-flop before being sent to the CS5180. Header HDR2, not populated, is provided for connecting to external SYNC and RESET signals. To use the external signals, set headers HDR6 and HDR7 to the EXT position and apply the external signals at the HDR2 thru-holes. J1 BNC 0 R56 49.9 R36* GND EXTCLK GND R35 VCCIO 10 U1 C9 0.1 F X7R 14 VCC 11 1 4 EN 2 GND GND HDR3 BNC OSC 0 MCLK Figures 5 and 6 VCCIO CLKOSC 1 2 3 GND NC7SZ04M5 GND 4 MCLKB Figure 3 U3 VCC 5 C16 0.1 F X7R 8 R57 25.6 MHz Nominal *Not Populated Figure 2. Clock Oscillator and Buffer DS259DB1 3 CDB5180 VCCIO VCCIO SNYC R13 2K R28 49.9 K C36 .1 F X7R GND VCCIO RESET R4 2K MCLKB Figure 2 U11 4 3 2 1 10 11 12 13 1/PRE 1CLK 1D 1/CLR 2/PRE 2CLK 2D 2/CLR VCC 14 1Q 5 1/Q 6 2Q 9 2/Q 8 GND 7 RESETB Figure 5 C8 0.1 F X7R GND SNYC Figure 5 SW HDR7 EXT SW HDR6 EXT VCCIO S1 GND R29 49.9 K C36 .1 F X7R GND MC74HC74AD S2 GND GND HDR2 1 2 EXT_SYNC 3 4 EXT_RESETB GND Figure 3. Reset and Sync Circuits DC-coupled signal from the BNC connector J2, set headers HDR8 and HDR9 to the BNC position. To feed a capacitively coupled signal from J6 to the CS5180, set HDR8 and HDR9 to the XLR position. Alternatively, the differential signals can be applied by feeding them into test points BAL+ and BAL-. Note that connector J6, R20, R21, C40, and C41 do not come installed on the board and must be obtained and soldered in by the user before a balanced signal can be applied to the board input. J6, R20, R21, C40, and C41 are not required when a single-ended signal is being applied to connector J2, since the op-amps will convert and apply a balanced signal to the CS5180. modulator data to be output, and for placing the chip in the power-down mode. For normal operation, header HDR15 should not be installed. To use the CS5180 internal digital filter, the mode pin should be set high by removing header HDR16. If HDR16 is installed, the internal digital filter is disabled and the direct unfiltered modulator output will be presented on the serial data pin SDO. For this condition, header HDR12 should be set to the MCLK position. OUTPUT BUFFERS AND HEADER CONNECTIONS Figure 6 illustrates the circuitry for sending the output data off-board and the associated header connections. The CS5180 outputs data in a serial format only, along with the serial clock and the frame sync signal, FSO. These signals are buffered externally to the CS5180 and then made available on the 10-pin header HDR1. Header HDR12 can be used to select between sending the serial clock SCLK or the master clock, MCLK, to pin 8 of HDR1. If the evaluation board is being used with the CDBCapture+ board then the CS5180 should be operated in Mode 1 (internal digital filter enabled), and HDR12 should be set to the SCLK position, where SCLK is connected to HDR1. If the DS259DB1 CS5180 CONVERTER CIRCUITS The connections to the CS5180 chip are illustrated in Figure 5. The analog and digital supply voltages are all decoupled with X7R ceramic capacitors close to the device. In addition to the 0.1 F ceramic capacitors, there are 1 and 10 F electrolytic caps on the voltage reference input and output lines to minimize noise on the references. An LED is connected to the MFLAG signal and when on, indicates that data from the converter may be invalid due to an input overload. Header plugs are provided to change the MODE pin, allowing for raw 1-bit 4 CDB5180 R41 CW + C42 10 F R40 1 K 10 K AGND +15 V R10 V+ 8 U6 1 4 V10 K R15 J2 BNC AGND R6 2K R9 R5 AGND 2K 5+ R38 1K AGND R18 10 K LM6172IM 2K 5 + LM6172IM BNC HDR9 XLR VREF_AMP Figure 1 R19 10 K + R39 10 F 6U6 7 R8 6 U9 7 R17 1.0 K R2 301 + C41 10 F BAL+ R20 10 K 2 J6 AIN+ 2K AGND 2K R7 23+ 8 U9 V+ 1 4 V- C19 .1 F X7R -15 V AGND VREF_AMP Figure 1 LM6172IM BNC HDR8 XLR R16 1.0 K R30 100 AINR1 301 TP14 Figure 5 AGND 10 F C40 * + C20 .1 F X7R R39 9.53 K VREF_AMP Figure 1 +15 V C17 .1 F X7R AGND R21 10 K * AGND BAL- 23+ LM6172IM 2 K .1 F X7R C18 -15 V AGND TP13 Figure 5 * (Not Populated) XLR_F 1 * AGND AGND * NOT POPULATED AGND 3 * AGND Figure 4. Input Signal Conditioning Circuitry evaluation board is being used without the CDBCapture+ board and the CS5180 is operating in Mode 0 (raw modulator output), then HDR12 should be set to the MCLK position, feeding the master clock signal to connector HDR1. Nor-gates U13 and U14 will automatically reconstruct the RTZ data from the modulator bitstream so that it can be sampled on the rising or falling edge of MCLK. USING THE EVALUATION BOARD Although the evaluation board can be connected directly to a microprocessor that has a serial port and is fast enough to process up to 400K words/second, it can be more convenient to use the evaluation board in conjunction with the Crystal CDBCapDS259DB1 ture+ Board, which has been designed specifically to interface with high speed converters and has a 10-pin header that is compatible with the signals on header HDR1 of the evalboard. Connect the appropriate power supply voltages to the binding posts of the board. Use high quality linear power supplies that are low in noise, ripple, and line frequency (50/60 Hz) interference. If both 5 V digital and 5 V analog supplies are to be used, make sure that HDR17 is removed to prevent contention between the supplies. Total 5 Volt current requirements are approximately 0.2 Amps. The load on the plus and minus 15 Volt supplies will be under 0.1 Ampere each. The Capture Plus board is then connected to a PC and Crystal's software is used to configure the board and to capture data. 5 CDB5180 VDDD R24 R23 R14 10 K 10 K 10 K AINFigure 4 AIN+ Figure 4 HDR16 1 2 C4 2200PF COG C1 2200PF COG MODE PWDNB 1 2 HDR15 R69 0 GND VDDD RESETB Figure 3 MCLK Figure 2 GND R44 0 R45 0 C35 X7R .1 F C31 X7R .1 F AGND AGND R52 0 +5 VA C27 X7R .1 F 26 27 28 AGND R50 C43 10 F + AGND VREF_AMP AGND AGND GND 25 24 23 22 21 20 19 PWDNB RESETB DGND1 MCLKB MODE MCLK VD+1 AIN+ AINVA+1 AGND1 VREF+ VREF- AGND3 FSO 18 17 16 15 14 13 12 C13 X7R .1 F R27 R31 0 0 0 0 0 0 C23 X7R .1 F 0 1 2 3 4 U8 CS5180_BL SDO SDOB SCLK SCLKB R34 R42 R43 FSO Figure 6 SDO Figure 6 SDOB Figure 6 SCLK Figure 6 R51 VREFCAP VREFIN VREFOUT VD+2 R54 0 R32 0 VREFIN Figure 1 C24 C44 X7R 10 F + .1 F 5 6 7 8 9 10 R47 0 11 GND GND GND C55 X7R .1 F C25 X7R C7 .1 F 1 F + VREFCAP .1 F .1 F +5 VA R53 SYNC Figure 3 R37 499 D1 LED_SMT3216 0 GND C14 X7R AGND C33 X7R AGND Figure 5. CS5180 Converter Circuit Connect a coaxial cable from the AIN BNC (J2) to a high quality signal source, such as the Krohn-Hite Model 4400A. Note that the performance of the CS5180 A/D converter can exceed the capability of many signal generators, especially with respect to noise and line frequency interference. COMPONENT LAYOUT Figures 7, 8, and 9 illustrate the component placement and layout of the CDB5180 evaluation board. Digital and analog patch areas have been provided for experimentation with new components. Note that all the power supply rails and their grounds are made available in the respective patch areas. DS259DB1 6 DGND2 MFLAG AGND2 SYNC VA+2 VDDD C32 X7R .1 F CDB5180 VCCIO C11 0.1 F X7R GND 1 SCLK Figure 5 2 U4 VCC 5 3 GND NC7SZ08M5 4 GND VCCIO C10 0.1 F X7R 1 FSO Figure 5 2 3 U2 VCC 5 GND NC7SZ08M5 4 GND HDR5X2 VCCIO HDR1 2 4 6 8 10 SDO_OUT VCCIO C29 0.1 F X7R GND 1 3 5 7 9 GND SCLK HDR12 MCLK MCLK Figure 2 GND U13 SDO Figure 5 1 2 3 GND NC7SZ02M5 GND SDOB Figure 5 1 2 3 GND NC7SZ02M5 GND U14 VCC VCC 5 4 5 VCCIO C30 0.1 F X7R GND 4 Figure 6. Output Buffers and Header Connections DS259DB1 7 CDB5180 Figure 7. Component Top Side Layout Silkscreen 8 DS259DB1 CDB5180 Figure 8. Top Side Traces and Groundplane DS259DB1 9 CDB5180 Figure 9. Bottom Side Traces and Groundplane 10 DS259DB1 * Notes * |
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