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| CRD4923 Reference Design for CS4923 Features Description The CRD4923 is a complete AC3 solution which takes optical SPDIF AC3 encoded digital data and outputs 6 channels of audio representing left, right, left surround, right surround, center and a low frequency effects (subwoofer) channel. This board can also take an analog input and do Dolby ProLogic decode and output 4 channels of audio representing left, right, center, and surround. Finally the CRD4923 can also take an analog input, apply stereo effects processing, and output a stereo pair with effects. This board is targeted as a system solution for home theater decoders. The CRD4923 incorporates the CS4923 AC3 Multi Channel Audio Decoder and the CS4226 Surround Sound CODEC. The CS4923 provides all digital signal processing (DSP) of the system while the CS4226 takes care of all conversion requirements between the analog and digital domain. The CRD4923 demonstrates the recommended connection topology between the CS4923 and the CS4226 to ensure proper system operation. ORDERING INFO CRD4923 I l Demonstrates suggested connection topology for CS4923 & CS4226 Dolby AC3 Decoding solution l Optical or RCA IEC61937 SPDIF reception capability for direct connection to a DVD l Stereo Analog Inputs l 6 channel output including Right, Left, Right Surround, Left Surround, Center, and Low Frequency Effect (LFE or Subwoofer) channels l All necessary clocking provided l Control from parallel port or "in system" during development Digital In Digital Out Analog Output CS4226 CRD4923-1 REV C Control Interface CS4923 Stereo Analog In Preliminary Product Information Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved) FEB `98 DS262RD1 1 CRD4923 OPERATION The CRD4923 includes the CS4923 AC3 Multi Channel Audio Decoder which handles all digital processing and the CS4226 Surround Sound CODEC which handles IEC61937 SPDIF reception, stereo differential analog to digital conversion, and six channel digital to analog conversion. The inputs to the board include one optical TOSLINK connector and one RCA connector for digital reception of compressed AC3 data in IEC61937 format and two RCA jacks for analog stereo input. The outputs to the board include six Analog outputs representing left, right, left surround, right surround, center and a low frequency effects (subwoofer) channel. There is also an optical transmitter connected to the S/PDIF transmitter on the CS4923. Digital Signal Processor and Codec Control Control of the CS4923 and the CS4226 can be handled in one of two ways. The system is shipped with a parallel computer cable and can be operated with accompanying software over any personal computer running with a Windows or DOS based operating system with a standard parallel port. Conversely the board can be operated "in system" by disabling the parallel interface and wire wrapping from an external microprocessor to the provided stake header J19. The parallel interface is disabled by tristating buffer U5 with jumper J20. The system is wired to use the SPI interface mode for both the CS4226 and the CS4923. The chips share a common serial clock and control data input with a 74VHC244 translating the signals to 3.3 V for the CS4923. Each part receives an independent chip select and the board uses separate control data outputs for each part. The CS4923 additionally has an interrupt request used for requesting attention from a host when it ahs data to be read. Figures 1&2 shows the DSP & CODEC schematic and the control interface respectively. Dolby Considerations It should be noted by the system designer that additional circuitry may be required to obtain Dolby Certification, depending on the end product and what group of Dolby certification is desired. The designer should consult the Dolby Licensee Information Manual and contact Dolby Laboratories to determine exactly what is required to meet Dolby specifications for his/her system. Clocking Architecture & Digital I/O The CRD4923 demonstrates the suggested clocking architecture that will work correctly with the hardware configurations utilized by the AC3 microcode. Figure 3 shows both the Digital I/O & the Clock Divider schematic. The onboard 49.152 MHz clock provides the DSP with it's necessary clock input. The CLKSEL pin of the CS4923 is pulled high so that this clock will bypass the internal PLL and drive the DSP directly. The 49.152 MHz clock is also divided by 4 by U6 to provide a 12.288 MHz clock input for the CS4226. In all modes the CS4226 masters MCLK. The CS4923 takes the MCLK as an input, divides this clock internally, and drives the LRCLK and SCLK so as to minimize level conversion buffers. This DS262RD1 Power Requirements The CRD4923 requires a +5 V input on J1 and digital ground on J2 for the digital side of the board. A +12 V input on J16, -12V input on J18 and analog ground on J17 are needed for the analog side of the board. The 5 V input feeds an on board regulator, U1, which provides the 3.3 V supply needed by the CS4923 and its interface components. The +5 V input also gives the CS4226, PC interface components, and the digital input and output components their power. The 12 V are the power rails for the op amps used for the input and output buffers. Figure 7 shows the power portion of the schematic. 2 CRD4923 LRCLK and SCLK are used as inputs to both the CS4226 and the CS4923's compressed data input port and digital audio input port. In this way all clocks for digital I/O between the chips are synchronized so that no buffer problems can occur. In all modes the data is passed in an I2S compatible format with 24 bits out of the CS4226 and into the CS4923 and 20 bits out of the CS4923 and into the CS4226. When the system is configured for AC3 operation, the CS4226 receives the IEC61937 AC3 stream from J6, the digital optical connector or J22, the digital RCA connector. It recovers the clock from this stream, locks to it with the PLL and produces a 256 Fs clock on the CLKOUT which is used as MCLK for the entire system . In this way the entire digital I/O is slaved to the SPDIF stream so that no buffer problems will exist between the CS4226, the CS4923, and the incoming stream. While operating in a PCM pass through mode, or PCM pass through with ProLogic decode mode, the CS4226 is configured by software to run off a divided down version of the on-board oscillator. The 49.152 MHz is divided by four with 2 D flip flops to give the 12.288 MHz clock input of the CS4226. The CS4226 CLKOUT then provides a 256 Fs clock for the system MCLK. The system sampling frequency is 48 kHz. All data in the system passes through the CS4226 for data conversion into the digital I2C format, then into the CS4923 for digital signal processing, and then back to the CS4226 for conversion into the analog domain. The digital data lines from the CS4226 to the CS4923 are buffered from 5V down to 3.3 V through U4. SDATA1 contains data from the digital receiver and is routed to the compressed data input port of the CS4923 after being level shifted down to 3.3 V by U4. SDATA2 contains data from the analog to digital converter and is routed to the digital audio input port of the CS4923 after being level shifted down to 3.3 V by U4. Input and Output Digital Input and Output Digital I/O is provided on board with two TOSLINK optical connectors and one RCA connector. S/PDIF digital input is handled in optical format by J6 and in electrical format by J22. The jumper J21 can be used to select (O)ptical input or (R)CA input. This stream is then routed to the CS4226's SPDIF receiver. The CS4923 SPDIF output is routed to the TOSLINK transmitter, J7, to provide an optical output.. Analog Input and Output The CRD4923 has the capability to take a single ended stereo analog pair in. The single ended input is converted into a differential pair and routed to the CS4226. Input levels should not exceed 2 Vrms. The first stage of the input filter (U8A and U11B) provides a gain of 1/2. The second stage (U8B and U11A) provides unity inversion. The result is a 2 Vrms differential signal that is AC coupled with the CS4226 differential input Figure 5 shows the Analog Input Circuitry. The six outputs from the CS4226 are routed to six output buffers which provide a non-inverting 2pole filter with a gain of two. The six signals represent left, right, left surround, right surround, center, and a low frequency effects (LFE) channel. The output signals coming from the board are 2 Vrms. Figure 6 shows the analog output circuitry. Analog Relay Control To prevent pops on power up and power down, relays are on all six output channels. These relays are controlled with the power on/off circuitry shown in Figure 4. The common mode out (CMOUT) of the CS4226 controls the relays at power up. The relays will not turn on until the DACs have been calibrated and the common mode has risen. This prevents any popping on power up. The signal RELAY_CTRL comes from the power failure out- DS262RD1 3 CRD4923 put (PFO) indicator of the Maxim 708 part. The power failure indicator input (PFI) tracks the level of the 5 volt supply. When this signal (PFI) falls more than 1/2 volt below 5 volts the output (PFO) falls low, cutting off the relays. The reset line is also tied into the relay control so that the relays will open when reset is low. Analog I/O Table 2 shows input signal and table 3 shows output signals for the board. All analog signals are 2 Vrms for input and output. Signal Name Left Input Right Input Connector J8 J12 Headers and Jumpers Power Table 1 shows the connections necessary for operation of the CRD4923. Section Digital Digital Analog Analog Analog Jumper J1 J2 J16 J17 J18 Voltage (volts) +5 Ground +12 Ground -12 Table 2. Analog Input Signals Signal Name Left Right Left Surround Right Surround Center Subwoofer Connector J15 J14 J10 J9 J13 J11 Table 3. Analog Output Signals Debugger Jumper J4 provides access to the CS4923 debugger. This jumper should be considered for factory use only Table 1. CRD4923 Connections Control Two stake headers are provided to enable the user to control the system from an external microprocessor. J20 enables and disables the onboard control by tristating the parallel port control buffer U5. When U5 is tristated all control signals for the board can be accessed on J19. Figure 2 shows a diagram of the signals available on J19. These signals can all be 5 volt as they are buffered by U4 before being routed to the CS4923. Memory J3 is a stake header providing access to all signals needed for an external memory interface to the CS4923. A memory module for autoboot or for DTS capability will be available in Q1 1998. Schematics & Layout The schematics in Figures 1 thru 7 show the entire circuit for the CRD4923. Figures 8 thru 13 show the layout files used to produce the board. Digital I/O The TOSLINK connector J6 provides an optical input for IEC61937 S/PDIF reception on the board. The RCA jack J22 provides an electrical IEC61937 SPDIF input. Jumper J21 can be used to select either the (R)CA signal from J22 or the (O)ptical signal from J6 to be routed to the receiver on the CS4226. The TOSLINK connector J7 provides an optical output from the digital transmitter on the CS4923. Bill of Materials The bill of materials at the end of this document shows the specific parts ordered for this design and the associated manufacturer. Most parts may be substituted as long as tolerances and voltage levels are adhered to. 4 DS262RD1 DS262RD1 REQ23 CS23 CDIN23 SCK23 CDOUT23 EXTMEM EMWR EMOE D7 D6 D5 D4 D3 D2 D1 D0 1 3 5 7 DGND +3.3VD FB2 +3.3VD +5VD FB3 +5_VDF C6 .1uF C7 1uF +3.3VD C8 .1uF C9 1uF C10 .1uF C11 1uF C12 1uF C13 .1uF C14 .1uF C15 1uF R1 2.0 C16 .1uF C17 1uF +5VD +3.3VD RP1 1 10k R94 10k DGND 23 12 34 1 DGND U2 MCLK SCLK RESET LRCLK INTREQ CS AUDATA0 A1 AUDATA1 A0 AUDATA2 SCPDIO EXTMEM CMPDAT WR CMPCLK RD 27 28 29 CDI23 SDOUT26_1 SDOUT26_2 R7 R8 D7 SDATAN D6 SCLKN D5 SLRCLKN D4 D3 XMT958 D2 D1 CLKIN D0 CLKSEL 30 31 AGND 32 33 C20 .22uF CLKIN23 3 SPDIF_OUT R10 10k R11 R66 10k 10k 22 25 26 +3.3VD AGND SPDIF_IN SDI23 R9 0 0 0 44 43 42 MCLK23 CLKOUT26 R64 33 AGND 40 AGND 19 U3 PDN AD1 AD0 SCL 8 5 6 3 4 7 10k R5 R93 10k R2 10k R3 4.7k R4 10k R62 10k R61 4.7k 36 20 18 6 7 19 21 4 5 VD3 VD2 VD1 VA+ VD+ VA+ 3 U3_31 1 38 37 CLKOUT SCLK LRCLK M R E S ET CDIN CS26 SCK CDOUT26 M R E S E T23 Debug Header J4 2 4 6 8 HDR4X2 9 8 7 6 5 4 3 2 +3.3VD DGND J3 +3.3VD R15 10k 2 4 6 8 10 12 14 16 18 20 HDR10X2 1 3 5 7 9 11 13 15 17 19 41 40 39 34 33 32 SDIN1 SDIN2 SDIN3 SDA SPI/I2C AGND 36 35 43 44 1 42 SDOUT1 SDOUT2 SCLKAUX AOUT1 21 22 23 24 25 26 LEFT RIGHT LEFTS RIGHTS CENTER SUB CS4923 CS4226 AOUT2 AOUT3 AOUT4 CMPREQ 8 9 10 11 14 15 16 17 LRCKAUX AOUT5 DATAAUX AOUT6 RX1 CMOUT 16 CMOUT C19 1uF AGND CMOUT 30 27 2 OVL/ERR DEM HOLD/RUBIT AIN1L AIN1R_AINR+ AIN2R_AINR14 13 12 11 10 9 15 AINR+ AINRAINLAINL+ 37 38 DBDA DBCK DGND1 2 DGND2 13 DGND3 24 FLT2 FLT1 R12 Should Not be Stuffed DGND R12 10k 12.288CLK 28 29 XTI XTO AGND2 DGND1 DGND2 AIN2L_AINLAIN3L_AINL+ AIN3R AINAUX AGND1 R13 17 43k C21 .015uF AGND AGND C22 1500pF FILT AGND 35 39 41 18 20 DGND M R E S E T23 ADDR17 ADDR15 REQ23 ADDR16 M R E S ET CDIN SCK CSDSP CLKOUT26 SDOUT26_1 SDOUT26_2 OSC 2 4 6 8 11 13 15 17 1 19 U4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 18 16 14 12 9 7 5 3 20 +3.3VD 10 M R E S E T 23 CDIN23 SCK23 CS23 MCLK23 CDI23 SDI23 CLKIN23 AGND AGND EXTMEM EMOE D6 D4 D2 D0 D7 D5 D3 D1 DGND R63 R6 33 33 DGND DGND External Memory Module Connector DGND TC74VHC244FW C18 .1uF Level Conversion Buffer DGND CRD4923 Figure 1. DSP and Codec 5 6 +5VD +5VD RP2 1 1.0K Control Signal Header and Buffer Disable J19 1 3 5 7 9 11 13 15 HDR8X2 DGND U5 2 4 6 8 10 12 14 16 RESET CDIN SCK CSDSP CS26 R16 R17 R18 R19 9 8 7 6 5 4 3 2 1k J5 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DB25-PL-24 1k 1k 1k PC0 PC1 PC2 PC3 TP9 TP10 TP11 CDOUT26 CDOUT23 REQ23 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 LATCH PS7 TP4 ENCNTL 2 3 4 5 6 7 8 9 11 1 D0 D1 D2 D3 D4 D5 D6 D7 CK OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VCC GND 19 18 17 16 15 14 13 12 20 10 RESET CDIN SCK CSDSP CS26 ADDR15 ADDR16 ADDR17 +5VD J20 1 2 3 3X1HDR DGND +5VD ENCNTL TC74VHC574 C24 .1uF DGND U7 LATCH DGND TP5 TP6 TP7 Parallel Port Interface and Buffers PS3 PS4 PS5 PS6 18 16 14 12 9 7 5 3 20 10 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 PC0 TP12 TP13 TP14 TP8 CDOUT26 CDOUT23 REQ23 +5VD C28 .1uF TC74HCT244FW DGND CRD4923 DGND DS262RD1 Figure 2. Control Interface DS262RD1 7 Digital Input J6 5 4 DGND 3 2 1 6 DGND DGND TORX-173 .01uF J21 1 2 3 3X1HDR DGND R68 75 DGND DGND .01uF TOTX-173 SPDIF_IN C27 .1uF C72 C26 .1uF L1 47uH +5VD Digital Output R23 1k C71 4 +5VD 3 R24 8.2K 2 1 6 DGND SPDIF_OUT J7 5 J22 J-RCA-RA-PCB DGND Oscillator and Clock Divider R20 12.288CLK 0 +5VD Y1 14 R21 OSCOUT 8 33 GND 49.152MHZ DGND 24.576CLK Q2BAR +5VD 4 3 2 1 10 11 12 13 R20 Should Not be Stuffed U6 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 1Q 1Q 5 6 24.576CLK Q1BAR C23 .1uF 7 VCC OSC Q1BAR 2Q 2Q VCC GND 9 8 14 7 R65 Q2BAR +5VD 3312.288CLK C25 .1uF DGND CRD4923 TC74VHC74AFN Figure 3. Digital I/O and Clock Divider 8 Reset and Power Monitor Circuitry +5VD Z5 BZX84-A3V3 1 R67 330 DGND C70 .1uF DGND RESET 1 4 RESET RESET U13 MAX708 8 7 MRESET Relay Control Circuit 3 2 VCC MR PFI DGND +12VA GND 3 PFO 5 RELAY_CTRL 3 D1 BAS16W 1 2 SW1A RELAY 2 SW2A RELAY 2 SW3A RELAY R58 1.0M 6 6 6 3 1 2 2 2 1 1 T4 MMBT3906 3 RESET1 T5 MMBT3906 3 1 CMOUT C85 .1uF T2 MMBT3906 3 T1 MMBT3904 1 2 3 T3 MMBT3904 2 RELAY_CTRL RESET CMOUT + C68 47uF 2 CRD4923 AGND DS262RD1 Figure 4. Reset and Power Monitor DS262RD1 J12 J-RCA-RA-PCB R44 6 22k 5 AGND AGND J8 J-RCA-RA-PCB R28 2 22k 3 AGND AGND Stereo Single Ended to Stereo Differential Pair Analog Input Buffers +12VA C44 C45 10pF R41 10pF R42 C54 .1uF 8 U11C MC33078D -12VA 11k U11B + 11k MC33078D R45 7 2 3 11k U11A + MC33078D 2 10uF 10uF C50 + AGND C48 + C56 .1uF 1 4 1 2 AINR+ 1 AINR- +12VA C29 C30 10pF R27 R26 11k U8A + 11k MC33078D MC33078D 2 10uF R29 1 6 5 10pF C37 .1uF 8 U8C MC33078D -12VA AGND C40 .1uF 4 11k U8B + 10uF C35 C32 + 7 2 1 AINL+ CRD4923 Figure 5. Analog Input + 1 AINL- 9 C74 1200pF AGND MC33078D 27pF C86 R71 11.8k R72 11.8k C82 1200pF AGND MC33078D 27pF C90 C75 AGND R87 11.8k AGND R88 11.8k R73 R74 1200pF 5 U9B C36 7 1 2 8 R36 47K + + SW1C 14 RELAY LEFTS 1.96k 3.90k C76 1200pF AGND J10 J-RCA-RA-PCB C83 R89 AGND R90 AGND MC33078D 27pF C87 R75 11.8k R76 11.8k AGND C84 1200pF AGND MC33078D 27pF C91 C77 AGND R92 11.8k R91 11.8k R77 R78 1200pF 3 U10A C46 + + 1 1 2 7 R43 47K SW2B 1 RELAY J11 J-RCA-RA-PCB +12VA AGND +12VA +12VA SUB 1.96k 3.90k C78 1200pF AGND MC33078D 27pF C88 R79 11.8k R80 11.8k AGND C79 R81 R82 1200pF 5 U10B C49 + + 7 1 2 8 R49 47K CENTER 1.96k 3.90k C80 1200pF AGND MC33078D 27pF C89 R83 11.8k R84 11.8k AGND - 6 - 2 10uF AGND AGND C53 .1uF U10C MC33078D -12VA AGND C41 .1uF AGND C55 .1uF 4 C42 .1uF SW2C 14 RELAY J13 J-RCA-RA-PCB 10uF AGND AGND Note: On certain boards made from this design, capacitors C85 through C91 were left off of the layout and consequently were stacked with their respective resistors for manufacturing. Figure 6. Analog Output - 1.96k 3.90k 2 + RIGHT + - 6 10uF 1200pF U12A 3 C60 1 1 2 7 R57 47K - AGND 1.96k 3.90k 6 + + - 1.96k 3.90k 2 + + 10 C73 R69 R70 U9A 3 C33 1 1 2 7 RELAY R33 47K R85 AGND R86 1 C81 U12B 5 C58 7 1 2 8 R54 47K RELAY 14 SW3C J15 J-RCA-RA-PCB SW1B J9 J-RCA-RA-PCB 1200pF RIGHTS 10uF 1200pF LEFT 10uF AGND SW3B 1 RELAY J14 J-RCA-RA-PCB 10uF AGND AGND U9C MC33078D -12VA 4 AGND C65 .1uF 8 8 8 U12C MC33078D -12VA C66 .1uF 4 CRD4923 DS262RD1 DS262RD1 11 Digital Power +5VD J1 1 1 DGND 4 COM IN GND C4 .1uF C5 .1uF 2 C2 .1uF OUT U1 LM3940IT-3.3 3 +3.3VD 2 1 1 CON-BANANA Z1 P6KE6.8 + C1 47uF + C3 47uF J2 1 1 2 2 CON-BANANA DGND Analog Power +12VA J16 1 2 1 CON-BANANA Z2 P6KE16 + C63 47uF C64 .1uF J17 1 1 2 AGND C69 .1uF CON-BANANA 2 Z4 P6KE16 1 + C67 47uF -12VA J18 1 1 2 CRD4923 CON-BANANA Figure 7. Power 12 CRD4923 DS262RD1 Figure 8. Silkscreen Top (SSTOP) DS262RD1 CRD4923 Figure 9. Silkscreen Top (ASSYTOP) 13 14 CRD4923 DS262RD1 Figure 10. Copper Top DS262RD1 CRD4923 Figure 11. Ground 15 CRD4923 16 DS262RD1 Figure 12. Power DS262RD1 CRD4923 Figure 13. Copper Bottom 17 18 DS262RD1 BILL OF MATERIALS - CRD4923-1 REV.C Item Quan. Reference 1 5 C1,C3,C63,C67,C68 2 30 C2,C4,C5,C6,C8,C10, C13,C14,C16,C18,C23, C24,C25,C26,C27,C28, C37,C40,C41,C42,C53, C54,C55,C56,C64,C65, C66,C69,C70,C85 C7,C9,C11,C12,C15,C17, C19 C20 C21 C22 C29,C30,C44,C45 C32,C33,C35,C36,C46, C48,C49,C50,C58,C60 C72,C71 C73,C74,C75,C76,C77, C78,C79,C80,C81,C82, C83,C84 C86,C87,C88,C89,C90, C91 D1 FB2,FB3 J1,J16 J2,J17 J3 J4 J5 J6 J7 J8,J9,J10,J11,J12,J13, J14,J15,J22 J18 J19 J20,J21 Part Name ECEV1CA470SP C1206C104J5RAC Manufacturer PANASONIC KEMET Footprint Value CSP_ELEC_2 47uF 60SQ CC1206 .1uF Description CAP,ELEC,47uF,SM260SQ,20%,16V CAP,.1uF,SM1206,5%,X7R,50V 3 4 5 6 7 8 9 10 7 1 1 1 4 10 2 12 C1206C105K5RAC C1206C224J5RAC C1206C153J5RAC C1206C152J5GAC C1206C100J5GAC ECEV1CA100SR C1206C103J5RAC C1206C122J5GAC KEMET KEMET KEMET KEMET KEMET PANASONIC KEMET KEMET CC1206 CC1206 CC1206 CC1206 CC1206 CSP_ELEC_1 70SQ CC1206 CC1206 1uF .22uF .015uF 1500pF 10pF 10uF .01uF 1200pF CAP,1uF,SM1206,10%,X7R,50V CAP,.22uF,SM1206,5%,X7R,50V CAP,.015uF,SM1206,5%,X7R,50V CAP,1500pF,SM1206,5%,COG,50V CAP,10pF,SM1206,5%,COG,50V CAP,10uF,ELEC,SM170SQ,20%,16V CAP,.01uF,SM1206,5%,X7R,50V CAP,1200pF,SM1206,5%,COG,50V 11 12 13 14 15 16 17 18 19 20 21 22 23 24 6 1 2 2 2 1 1 1 1 1 9 1 1 2 C1206C270J5GAC BAS16W FERRITE BEAD 111-0102-001 111-0103-001 TSW-110-07-G-D TSW-104-07-G-D DB25-PL-24 TORX173 TOTX173 16PJ097 111-0104-001 TSW-108-07-G-D TSW-103-07-G-S KEMET PHILLIPS TDK CC1206 27pF BAS16W FERRITE BEAD CONBANANA CONBANANA HDR10X2 HDR4X2 DB25-PL-24 TORX-173 TOTX-173 J-RCA-RAPCB CONBANANA HDR8X2 3X1HDR CAP,27pF,SM1206,5%,COG,50V DIODE,SOT323,SIGNAL DIODE FERRITE BEAD - THRU HOLE CONN,BANANA,TH,BINDING POST,RED,INSULATED STANDARD CONN,BANANA,TH,BLACK,BINDING POST,INSULATED STANDARO HDR,10X2,.025"PIN,.1"CNTR HDR,4X2,.025"PIN,.1"CNTR CONN,RT.ANG,TH,D-SUB,25PN,MALE OPTICAL TOSLINK RECIEVER OPTICAL TOSLINK TRANSMITTER CONN,.25",RCA,PHONO JACK CONN,BANANA,TH,GREEN,BINDING POST,INSULATED STANDARO HDR,8X2,.025"PIN,.1"CNTR HDR,3X1,.025"PIN,.1"CNTR SOT323 IND_FB43_22 6 JOHNSON COM- BANANA PONENTS JOHNSON COM- BANANA PONENTS SAMTEC HDR10X2 SAMTEC HDR4X2 ADAM TECH DB25-HM TOSHIBA TORX-173 TOSHIBA TOTX-173 MOUSER J-RCA-RAPCB JOHNSON COM- BANANA PONENTS SAMTEC HDR8X2 SAMTEC HDR3 CRD4923 Item Quan. 25 1 L1 26 1 RP1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 1 11 2 5 4 1 5 1 6 2 6 1 1 1 6 6 12 RP2 Reference Part Name SIMID03-47uH 4609X-101-103 4609X-101-102 9C12063A2R00J 9C12063A1002J 9C12063A4701J 9C12063A33R0J 9C12063A0R00J 9C12063A4302F 9C12063A1001J 9C12063A8201J 9C12063A1102F 9C12063A2202F 9C12063A4702J 9C12063A1004J 9C12063A3300F 9C12063A75R0J 9C12063A1961F 9C12063A3901F 9C12063A1182F Manufacturer SIEMENS BOURNS BOURNS Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Philips Footprint IND1812 RES_SIP9 RES_SIP9 Value 47uH 10k 1.0K 45 46 3 14 47 48 49 50 51 52 2 2 1 1 1 1 R1 R2,R4,R5,R10,R11,R12, R15,R62,R66,R93,R94 R3,R61 R6,R21,R63,R64,R65 R7,R8,R9,R20 R13 R16,R17,R18,R19,R23 R24 R26,R27,R29,R41,R42, R45 R44,R28 R33,R36,R43,R49,R54, R57 R58 R67 R68 R69,R73,R77,R81,R85, R89 R70,R74,R78,R82,R86, R90 R71,R72,R75,R76,R79, R80,R83,R84,R87,R88, R91,R92 SW1,SW2,SW3 TP1,TP2,TP3,TP4,TP5, TP6,TP7,TP8,TP9,TP10,T P11,TP12,TP13,TP14 T3,T1 T2,T4, T5 U1 U2 U3 U4 RES/RC1206 2 RES/RC1206 10k RES/RC1206 RES/RC1206 RES/RC1206 RES/RC1206 RES/RC1206 RES/RC1206 RES/RC1206 4.7k 33 0 43k 1k 8.2K 11k Description IND,47uH,10%,210mA RES,10K,9 PIN SIP PARALLEL NETWORK RES,1.0K,9 PIN SIP PARALLEL NETWORK RES,2.0,SM1206,5%,1/4W RES,10k,SM1206,5%,1/4W RES,4.7k,SM1206,5%,1/4W RES,33,SM1206,5%,1/4W RES,0,SM1206,5%,1/4W RES,43k,SM1206,1%,1/4W RES,1k,SM1206,5%,1/4W RES,8.2k,SM1206,5%,1/4W RES,11k,SM1206,1%,1/4W RES,22k,SM1206,1%,1/4W RES,47k,SM1206,5%,1/4W RES,1M,SM1206,5%,1/4W RES,330,SM1206,1%,1/4W RES,75,SM1206,5%,1/4W RES,1.96k,SM1206,1%,1/4W RES,3.90k,SM1206,1%,1/4W RES,11.8k,SM1206,1%,1/4W DS262RD1 19 RES/RC1206 22k RES/RC1206 47K RES/RC1206 RES/RC1206 RES/RC1206 RES/RC1206 1.0M 330 75 1.96k RES/RC1206 3.90k RES/RC1206 11.8k HE722A1200 TP HAMLIN DIP14 VIA60 RELAY TP REED RELAY, 12V, DUAL PACKAGE TESTPOINT,VIA 60 MMBT3904 MMBT3906 LM3940IT-3.3 CS4923 CS4226 TC74VHC244FW MOTOROLA MOTOROLA NATIONAL SEMICONDUCTOR CRYSTAL CRYSTAL TOSHIBA SOT23 SOT23 TO-220 PLCC44 TQFP44 SOIC20 300MIL MMBT3904 MMBT3906 LM3940IT3.3 CS4923 CS4226 TC74VHC24 4FW NPN TRANSISTOR, SOT23 PNP TRANSISTOR, SOT23 +3.3V REGULATOR, TO-220 CRD4923 DSP CODEC OCT BUFF,VHC,SOIC20 300MIL,3 & 5 V TOL 20 DS262RD1 Item Quan. 53 1 U5 54 55 56 57 58 59 60 61 1 1 5 1 1 1 2 1 U6 U7 Reference Part Name TC74VHC574FW TC74VHC74AFN TC74HCT244FW MC33078D MAX708CSA Manufacturer TOSHIBA TOSHIBA TOSHIBA MOTOROLA MAXIM U8,U9,U10,U11,U12 U13 Y1 Z1 Z2,Z4 Z5 Footprint SOIC20 300MIL SOIC14 150MIL SOIC20 300MIL SO-8 SO-8 CLKOSC_GE NERIC CASE17-02 CASE 17-02 SOT23 Value TC74VHC57 4 TC74VHC74 AFN TC74HCT24 4FW MC33078D MAX708 49.152MHZ CX21AF-49.1520MHZ CAL CRYSTAL P6KE6.8A P6KE16A BZX84-A3V3 MOTOROLA MOTOROLA Philips Description OCT D FF,VHC,SOIC20 300MIL,3 & 5 V TOL DUAL D FF,VHC,SOIC14 150MIL,3 & 5 V TOL OCT BUFF,HCT,SOIC20 300MIL,3 & 5 V TOL IC,SO-8,DUAL SUPPLY DUAL OP AMP IC, LOW COST uP SUPERVISORY CIRQUIT OSC,49.152MHZ,TTL/CMOS,FULL SIZE P6KE6.8 AXIAL ZENER DIODE,DO-7,6.8V P6KE16 AXIAL ZENER DIODE,DO-7,16V BZX84-A3V3 ZENER, 3.3V, 5ma CRD4923 CRD4923 APPENDIX A: SOFTWARE TOOLS FOR THE CRD4923 A variety of tools is shipped with the CRD4923 to allow the user to communicate with the CRD4923. These tools are DOS based and run through the parallel port of a personal computer running DOS (or Windows running a DOS shell). Each program uses the default address of 0x378 for the parallel port. If your computer does not work with this address, the default can be changed with a command line switch. -p = parallel port address XXX = address (0x278, 378* or 3bc); -v = disable verbose mode * = default The following example shows how the hex message 0x000001 would be sent with a parallel port address of 0x378: crd23cmd 000001 The following example shows how the messages in the configuration file AC3PRO.CFG would be sent with a parallel port address of 0x278: crd23cmd -fac3pro.scg -p278 CRD23_LD.EXE CRD23_LD.EXE is a program that boots and loads the CS4923 and configures the CS4226. Its usage is as follows: Usage: crd23_ld CRD23_RD.EXE CRD23_RD is a program that reads back responses from the CS4923. This program polls on the interrupt request line of the CS4923 to determine if the CS4923 has anything to be read. It should be noted that without sending a message via CRD23CMD that will illicit a response, this program will do nothing. For more on communicating with the CS4923, the CS4923 Users Guide should be read. The following is the CRD23_RD usage: Usage: crd23_rd [-pXXX] [-v] [-h] -p = parallel port address XXX = address (0x278, 378* or 3bc) -v = disable verbose mode -h = this message * = default CRD23CMD.EXE CRD23CMD.EXE is a program that sends messages to the CS4923 in the SPI format. This program can send commands from the command line or it can also send commands from a file. The CRD4923 is shipped with configuration files that allow the CS4923 to be configured in the modes given in the Application Messaging section of the CS4923 Users Guide. The following is its usage: Usage: crd23cmd <[ABCDEF] or [-fY]> [pXXX] [-v] ABCDEF = Three byte hex command Y = .cfg file containing configuration parameters"); DS262RD1 WRITE26.EXE WRITE26.EXE is a program that writes registers in the CS4226 in the SPI format. This program sends values from the command line. The following is its usage: Usage: write26 <[ABCD]> [-pXXX] [-v] AB = Register to be written CD = Value to be written to register -p = parallel port address XXX = address (0x278, 378* or 3bc); -v = disable verbose mode * = default 21 CRD4923 READ26.EXE READ26.EXE is a program that reads messages from the CS4226 in the SPI format. After executing this program the value of the register is written to the screen. The following is its usage: Usage: read26 <[AB]> [-pXXX] [-v] AB = Register to be read -p = parallel port address XXX = address (0x278, 378* or 3bc); -v = disable verbose mode * = default SINE WAVES: 1. crd23_ld asine.ld -pXXX Batch Files The batch files (.bat) shipped with the CRD4923 automate the control messages that need to be sent to the CRD4923 to set up the CS4923 and the CS4226 for different modes of operation. The different modes of operation are illustrated further in section 5, Application Messaging, of AN115, The CS4923 Users Guide. Specifically the batch files follow section 5.2, Application Modes of AN115. The batch files send the neccesary configuration messages thru CRD23CMD and a .CFG file and also set up the clocking scheme of the CS4226 for the mode. The following list displays the different modes that are provided through batch files and how to initiate them. This list is in no way demonstrative of all the modes supported by the CRD4923. 22 DS262RD1 * Notes * |
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