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| 74LVQ74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR s s s s s s s s s s s HIGH SPEED: fMAX = 250 MHz (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC =2 A (MAX.) at TA=25C LOW NOISE: VOLP = 0.2 V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY SOP TSSOP ORDER CODES PACKAGE SOP TSSOP TUBE 74LVQ74M T&R 74LVQ74MTR 74LVQ74TTR DESCRIPTION The 74LVQ74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 74LVQ74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS CLR L H L H H H X : Don't Care OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PRESET PR H L L H H H LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 74LVQ74 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 400 -65 to +150 300 Unit V V V mA mA mA mA C C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0V (note 2) Parameter Value 2 to 3.6 0 to VCC 0 to VCC -55 to 125 0 to 10 Unit V V V C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) TA = 25C Min. 2.0 0.8 IO=-50 A 3.0 IO=-12 mA IO=-24 mA VOL Low Level Output Voltage IO=50 A 3.0 IO=12 mA IO=24 mA II ICC IOLD IOHD Input Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 3.6 3.6 3.6 VI = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min 0.1 2 36 -25 0.002 0 0.1 0.36 2.9 2.58 2.99 2.9 2.48 2.2 0.1 0.44 0.55 1 20 25 -25 Typ. Max. Value -40 to 85C Min. 2.0 0.8 2.9 2.48 2.2 0.1 0.44 0.55 1 20 A A mA mA V V Max. -55 to 125C Min. 2.0 0.8 Max. V V Unit VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 3.0 to 3.6 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75 3/11 74LVQ74 DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 3.3 3.3 CL = 50 pF 3.3 0.8 V TA = 25C Min. Typ. 0.2 -0.8 2 -0.2 Max. 0.8 V V Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 2.7 3.3 2.7 (*) Value TA = 25C Min. Typ. 7.7 6.3 6.9 5.8 4.0 3.0 4.0 3.0 4.0 3.0 2.0 2.0 1.0 1.0 100 120 1.5 1.5 1.5 1.5 -0.2 -0.2 0.2 0.2 -1.0 -1.0 200 250 0.2 0.2 1.0 1.0 Max. 12.0 9.0 12.0 9.0 4.0 3.0 4.0 3.0 4.0 3.0 2.0 2.0 1.0 1.0 100 120 1.0 1.0 -40 to 85C Min. Max. 14.0 10.5 14.0 10.5 5.0 4.0 5.0 4.0 5.0 4.0 2.0 2.0 1.0 1.0 80 100 1.0 1.0 -55 to 125C Min. Max. 16.0 12.0 16.0 12.0 ns ns Unit tPLH tPHL tPLH tPHL tw tw(L) ts th tREM fMAX tOSLH tOSHL Propagation Delay Time CK to Q Propagation Delay Time PR or CLR to Q Pulse Width CK , HIGH or LOW Pulse Width PR or CLR, LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Recovery Time PR or CLR to Q Maximum Clock Frequency Output To Output Skew Time (note1, 2) 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3 2.7 (*) ns ns ns ns ns MHz 3.3 2.7 2.7 (*) 3.3(*) 3.3(*) 2.7 3.3(*) ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, t OSHL = |tPHLm - t PHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V 0.3V 4/11 74LVQ74 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 3.3 3.3 fIN = 10MHz TA = 25C Min. Typ. 4 33 Max. Value -40 to 85C Min. Max. -55 to 125C Min. Max. pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit) TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 500 or equivalent RT = ZOUT of pulse generator (typically 50) 5/11 74LVQ74 WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74LVQ74 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle) 7/11 74LVQ74 WAVEFORM 4: PULSE WIDTH 8/11 74LVQ74 SO-14 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13G 9/11 74LVQ74 TSSOP14 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 10/11 74LVQ74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com 11/11 |
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