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ST6x86
P90+, P120+, P133+, P150+, P166+ 3.52 Volt ST6x86 CPU
PRELIMINARY DATA
Sixth-Generation Superscalar Superpipelined Architecture - Dual 7-stage integer pipelines - High performance on-chip FPU with 64-bit interface - Operating at P90+ speeds and above - 16-KByte write-back cache X86 Instruction Set Compatible - Runs Windows 95, Windows NT, DOS, UNIX, Novell, OS/2, Solaris, and others
Optimum Performance for Windows(R)95 - Intelligent instruction dispatch - Out-of-order execution - Register renaming - Data forwarding - Branch prediction - Speculative execution 64-Bit Data Bus - P54C socket compatible for quick time to market
The ST6x86TM microprocessor is a superscalar, superpipelined CPU that provides sixth-generation performance for x86 software. Since the ST6x86 CPU is fully compatible with the x86 instruction set, it is capable of executing a wide range of existing operating systems and applications, including Windows 95, DOS, Unix, Windows NT, Novell, OS/2, and Solaris. The ST6x86 CPU achieves top performance levels through the use of two optimized superpipelined integer units and an on-chip floating point unit. The superpipelined architecture reduces timing constraints and allows the ST6x86 CPU to achieve P90+ performance levels and BLOCK DIAGRAM
above. In addition, the ST6x86 CPU's integer and floating point units are optimized for maximum instruction throughput by using advanced architectural techniques, including register renaming, out-of-order execution, data forwarding, branch prediction, and speculative execution. These design innovations eliminate many data dependencies and resource conflicts that provide optimum performance for Windows 95 software.
August 1996
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ST6x86
1.0 ARCHITECTURE OVERVIEW The SGS-THOMSON ST6x86 CPU is a leader in the sixth generation of high performance, x86-compatible microprocessors. Increased performance is accomplished by the use of superscalar and superpipelined design techniques. The ST6x86 CPU is superscalar in that it contains two separate pipelines that allow multiple instructions to be processed at the same time. The use of advanced processing technology and the increased number of pipeline stages (superpipelining) allow the ST6x86 CPU to achieve clocks rates of 80, 100, 110, 120, 133 MHz and above. Through the use of unique architectural features, the ST6x86 processor eliminates many data dependencies and resource conflicts, resulting in optimal performance for both 16-bit and 32-bit x86 software. The ST6x86 CPU contains two caches: a 16-KByte dual-ported unified cache and a 256-byte instruction line cache. Since the unified cache can store instructions and data in any ratio, the unified cache offers a higher hit rate than separate data and instruction caches of equal size. An increase in overall cache-to-integer unit bandwidth is achieved by supplementing the unified cache with a small, high-speed, fully associative instruction line cache. The inclusion of the instruction line cache avoids excessive conflicts between code and data accesses in the unified cache. The on-chip FPU allows floating point instructions to execute in parallel with integer instructions and features a 64-bit data interface. The FPU incorporates a four-deep instruction queue and a four-deep store queue to facilitate parallel execution. The ST6x86 CPU operates from a 3.3 volt power supply resulting in reasonable power consumption at all frequencies. In addition, the ST6x86 CPU incorporates a low power suspend mode, stop clock capability, and system management mode (SMM) for power sensitive applications. 1.1 Major Functional Blocks The ST6x86 processor consists of five major functional blocks, as shown in the overall block diagram on the first page of this manual: Integer Unit Cache Unit Memory Management Unit Floating Point Unit Bus Interface Unit
Instructions are executed in the X and Y pipelines within the Integer Unit and also in the Floating Point Unit (FPU). The Cache Unit stores the most recently used data and instructions to allow fast access to the information by the Integer Unit and FPU. Physical addresses are calculated by the Memory Management Unit and passed to the Cache Unit and the Bus Interface Unit (BIU). The BIU provides the interface between the external system board and the processor's internal execution units.
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1.2 Integer Unit The Integer Unit (Figure 1.1) provides parallel instruction execution using two seven-stage inteFigure 1.1. Integer Unit ger pipelines. Each of the two pipelines, X and Y, can process several instructions simultaneously.
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The Integer Unit consists of the following pipeline stages: - Instruction Fetch (IF) - Instruction Decode 1 (ID1) - Instruction Decode 2 (ID2) - Address Calculation 1 (AC1) - Address Calculation 2 (AC2) - Execute (EX) - Write-Back (WB) The instruction decode and address calculation functions are both divided into superpipelined stages. 1.2.1 Pipeline Stages The Instruction Fetch (IF) stage, shared by both the X and Y pipelines, fetches 16 bytes of code from the cache unit in a single clock cycle. Within this section, the code stream is checked for any branch instructions that could affect normal program sequencing. If an unconditional or conditional branch is detected, branch prediction logic within the IF stage generates a predicted target address for the instruction. The IF stage then begins fetching instructions at the predicted address. The superpipelined Instruction Decode function contains the ID1 and ID2 stages. ID1, shared by both pipelines, evaluates the code stream provided by the IF stage and determines the number of bytes in each instruction. Up to two instructions per clock are delivered to the ID2 stages, one in each pipeline. The ID2 stages decode instructions and send the decoded instructions to either the X or Y pipeline for execution. The particular pipeline is chosen, based on which instructions are already in each pipeline and how fast they are expected to flow through the remaining pipeline stages. The Address Calculation function contains two stages, AC1 and AC2. If the instruction refers to a memory operand, the AC1 calculates a linear memory address for the instruction. The AC2 stage performs any required memory management functions, cache accesses, and register file accesses. If a floating point instruction is detected by AC2, the instruction is sent to the FPU for processing. The Execute (EX) stage executes instructions using the operands provided by the address calculation stage. The Write-Back (WB) stage is the last IU stage. The WB stage stores execution results either to a register file within the IU or to a write buffer in the cache control unit. 1.2.2 Out-of-Order Processing If an instruction executes faster than the previous instruction in the other pipeline, the instructions may complete out of order. All instructions are processed in order, up to the EX stage. While in the EX and WB stages, instructions may be completed out of order. If there is a data dependency between two instructions, the necessary hardware interlocks are enforced to ensure correct program execution. Even though instructions may complete out of order, exceptions and writes resulting from the instructions are always issued in program order.
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1.2.3 Pipeline Selection In most cases, instructions are processed in either pipeline and without pairing constraints on the instructions. However, certain instructions are processed only in the X pipeline: - Branch instructions - Floating point instructions - Exclusive instructions Branch and floating point instructions may be paired with a second instruction in the Y pipeline. Exclusive Instructions cannot be paired with instructions in the Y pipeline. These instructions typically require multiple memory accesses. Although exclusive instructions may not be paired, hardware from both pipelines is used to accelerate instruction completion. Listed below are the ST6x86 CPU exclusive instruction types: - Protected mode segment loads - Special register accesses (Control, Debug, and Test Registers) - String instructions - Multiply and divide - I/O port accesses - Push all (PUSHA) and pop all (POPA) - Intersegment jumps, calls, and returns 1.2.4 Data Dependency Solutions When two instructions that are executing in parallel require access to the same data or register, one of the following types of data dependencies may occur: - Read-After-Write (RAW) - Write-After-Read (WAR) - Write-After-Write (WAW) Data dependencies typically force serialized execution of instructions. However, the ST6x86 CPU implements three mechanisms that allow parallel execution of instructions containing data dependencies: - Register Renaming - Data Forwarding - Data Bypassing The following sections provide detailed examples of these mechanisms. 1.2.4.1 Register Renaming The ST6x86 CPU contains 32 physical general purpose registers. Each of the 32 registers in the register file can be temporarily assigned as one of the general purpose registers defined by the x86 architecture (EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP). For each register write operation a new physical register is selected to allow previous data to be retained temporarily. Register renaming effectively removes all WAW and WAR dependencies. The programmer does not have to consider register renaming; it is completely transparent to both the operating system and application software.
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Example #1 - Register Renaming Eliminates Write-After-Read (WAR) Dependency A WAR dependency exists when the first in a pair of instructions reads a logical register, and the second instruction writes to the same logical register. This type of dependency is illustrated by the pair of instructions shown below: X PIPE (1) MOV BX, AX
BX AX
Y PIPE (2) ADD AX, CX
AX AX + CX
Note: In this and the following examples the original instruction order is shown in parentheses. In the absence of register renaming, the ADD instruction in the Y pipe would have to be stalled to allow the MOV instruction in the X pipe to read the AX register. The ST6x86 CPU, however, avoids the Y pipe stall (Table 1.1). As each instruction executes, the results are placed in new physical registers to avoid the possibility of overwriting a logical register value and to allow the two instructions to complete in parallel (or out of order) rather than in sequence. Table 1.1. Register Renaming with WAR Dependency
Physical Register Contents Instruction Reg0 (Initial) MOV BX, AX ADD AX, CX AX AX Reg1 BX Reg2 CX CX CX BX BX AX X Y Reg3 Reg0 Reg4 Reg0 + Reg2 Reg3 Reg4 Pipe Action
Note: The representation of the MOV and ADD instructions in the final column of Table 1.1 are completely independent.
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Example #2 - Register Renaming Eliminates Write-After-Write (WAW) Dependency A WAW dependency occurs when two consecutive instructions perform writes to the same logical register. This type of dependency is illustrated by the pair of instructions shown below: X PIPE (1) ADD AX, BX
AX AX + BX
Y PIPE (2) MOV AX, [mem]
AX [mem]
Without register renaming, the MOV instruction in the Y pipe would have to be stalled to guarantee that the ADD instruction in the X pipe would write its results to the AX register first. The ST6x86 CPU uses register renaming and avoids the Y pipe stall. The contents of the AX and BX registers are placed in physical registers (Table 1.2). As each instruction executes, the results are placed in new physical registers to avoid the possibility of overwriting a logical register value and to allow the two instructions to complete in parallel (or out of order) rather than in sequence. Table 1.2. Register Renaming with WAW Dependency
Physical Register Contents Instruction Reg0 (Initial) ADD AX, BX MOV AX, [mem] AX Reg1 BX BX BX AX AX X Y Reg2 Reg0 + Reg1 Reg3 [mem] Reg2 Reg3 Pipe Action
Note: All subsequent reads of the logical register AX will refer to Reg 3, the result of the MOV instruction.
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1.2.4.2 Data Forwarding Register renaming alone cannot remove RAW dependencies. The ST6x86 CPU uses two types of data forwarding in conjunction with register renaming to eliminate RAW dependencies: - Operand Forwarding - Result Forwarding Operand forwarding takes place when the first in a pair of instructions performs a move from register or memory, and the data that is read by the first instruction is required by the second instruction. The ST6x86 CPU performs the read operation and makes the data read available to both instructions simultaneously. Result forwarding takes place when the first in a pair of instructions performs an operation (such as an ADD) and the result is required by the second instruction to perform a move to a register or memory. The ST6x86 CPU performs the required operation and stores the results of the operation to the destination of both instructions simultaneously.
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Example #3 - Operand Forwarding Eliminates Read-After-Write (RAW) Dependency A RAW dependency occurs when the first in a pair of instructions performs a write, and the second instruction reads the same register. This type of dependency is illustrated by the pair of instructions shown below in the X and Y pipelines: X PIPE (1) MOV AX, [mem]
AX [mem]
Y PIPE (2) ADD BX, AX
BX AX + BX
The ST6x86 CPU uses operand forwarding and avoids a Y pipe stall (Table 1.3). Operand forwarding allows simultaneous execution of both instructions by first reading memory and then making the results available to both pipelines in parallel. Table 1.3. Example of Operand Forwarding
Physical Register Contents Instruction Reg0 (Initial) MOV AX, [mem] ADD BX, AX AX Reg1 BX BX AX AX BX X Y Reg2 [mem] Reg3 [mem] + Reg1 Reg2 Reg3 Pipe Action
Operand forwarding can only occur if the first instruction does not modify its source data. In other words, the instruction is a move type instruction (for example, MOV, POP, LEA). Operand forwarding occurs for both register and memory operands. The size of the first instruction destination and the second instruction source must match.
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Example #4 - Result Forwarding Eliminates Read-After-Write (RAW) Dependency In this example, a RAW dependency occurs when the first in a pair of instructions performs a write, and the second instruction reads the same register. This dependency is illustrated by the pair of instructions in the X and Y pipelines, as shown below: X PIPE (1) ADD AX, BX
AX AX + BX
Y PIPE (2) MOV [mem], AX
[mem] AX
The ST6x86 CPU uses result forwarding and avoids a Y pipe stall (Table 1.4). Instead of transferring the contents of the AX register to memory, the result of the previous ADD instruction (Reg0 + Reg1) is written directly to memory, thereby saving a clock cycle. Table 1.4. Result Forwarding Example
Physical Register Contents Instruction Reg0 (Initial) ADD AX, BX MOV [mem], AX AX Reg1 BX BX BX AX AX X Y Reg2 Reg0 + Reg1 [mem] Reg0 +Reg1 Reg2 Pipe Action
The second instruction must be a move instruction and the destination of the second instruction may be either a register or memory.
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1.2.4.3 Data Bypassing In addition to register renaming and data forwarding, the ST6x86 CPU implements a third data dependency-resolution technique called data bypassing. Data bypassing reduces the performance penalty of those memory data RAW dependencies that cannot be eliminated by data forwarding. Data bypassing is implemented when the first in a pair of instructions writes to memory and the second instruction reads the same data from memory. The ST6x86 CPU retains the data from the first instruction and passes it to the second instruction, thereby eliminating a memory read cycle. Data bypassing only occurs for cacheable memory locations. Example #1- Data Bypassing with Read-After-Write (RAW) Dependency In this example, a RAW dependency occurs when the first in a pair of instructions performs a write to memory and the second instruction reads the same memory location. This dependency is illustrated by the pair of instructions in the X and Y pipelines as shown below: X PIPE (1) ADD [mem], AX
[mem] [mem] + AX
Y PIPE (2) SUB BX, [mem]
BX BX - [mem]
The ST6x86 CPU uses data bypassing and stalls the Y pipe for only one clock by eliminating the Y pipe's memory read cycle (Table 1.5). Instead of reading memory in the Y pipe, the result of the previous instruction ([mem] + Reg0) is used to subtract from Reg1, thereby saving a memory access cycle. Table 1.5. Example of Data Bypassing
Physical Register Contents Instruction Reg0 (Initial) ADD [mem], AX SUB BX, [mem] AX AX AX Reg1 BX BX BX X Y [mem] [mem] + Reg0 Reg2 Reg1 - {[mem] + Reg0} Reg2 Pipe Action
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1.2.5 Branch Control Branch instructions occur on average every four to six instructions in x86-compatible programs. When the normal sequential flow of a program changes due to a branch instruction, the pipeline stages may stall while waiting for the CPU to calculate, retrieve, and decode the new instruction stream. The ST6x86 CPU minimizes the performance degradation and latency of branch instructions through the use of branch prediction and speculative execution. 1.2.5.1 Branch Prediction The ST6x86 CPU uses a 256-entry, 4-way set associative Branch Target Buffer (BTB) to store branch target addresses and branch prediction information. During the fetch stage, the instruction stream is checked for the presence of branch instructions. If an unconditional branch instruction is encountered, the ST6x86 CPU accesses the BTB to check for the branch instruction's target address. If the branch instruction's target address is found in the BTB, the ST6x86 CPU begins fetching at the target address specified by the BTB. In case of conditional branches, the BTB also provides history information to indicate whether the branch is more likely to be taken or not taken. If the conditional branch instruction is found in the BTB, the ST6x86 CPU begins fetching instructions at the predicted target address. If the conditional branch misses in the BTB, the ST6x86 CPU predicts that the branch will not be taken, and instruction fetching continues with the next sequential instruction. The decision to fetch the taken or not taken target address is based on a four-state branch prediction algorithm. Once fetched, a conditional branch instruction is first decoded and then dispatched to the X pipeline only. The conditional branch instruction proceeds through the X pipeline and is then resolved in either the EX stage or the WB stage. The conditional branch is resolved in the EX stage, if the instruction responsible for setting the condition codes is completed prior to the execution of the branch. If the instruction that sets the condition codes is executed in parallel with the branch, the conditional branch instruction is resolved in the WB stage. Correctly predicted branch instructions execute in a single core clock. If resolution of a branch indicates that a misprediction has occurred, the ST6x86 CPU flushes the pipeline and starts fetching from the correct target address. The ST6x86 CPU prefetches both the predicted and the non-predicted path for each conditional branch, thereby eliminating the cache access cycle on a misprediction. If the branch is resolved in the EX stage, the resulting misprediction latency is four cycles. If the branch is resolved in the WB stage, the latency is five cycles. Since the target address of return (RET) instructions is dynamic rather than static, the ST6x86 CPU caches target addresses for RET instructions in an eight-entry return stack rather than in the BTB. The return address is pushed on the return stack during a CALL instruction and popped during the corresponding RET instruction.
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1.2.5.2 Speculative Execution The ST6x86 CPU is capable of speculative execution following a floating point instruction or predicted branch. Speculative execution allows the pipelines to continuously execute instructions following a branch without stalling the pipelines waiting for branch resolution. The same mechanism is used to execute floating point instructions (see Section 1.5) in parallel with integer instructions. The ST6x86 CPU is capable of up to four levels of speculation (i.e., combinations of four conditional branches and floating point operations). After generating the fetch address using branch prediction, the CPU checkpoints the machine state (registers, flags, and processor environment), increments the speculation level counter, and begins operating on the predicted instruction stream. Once the branch instruction is resolved, the CPU decreases the speculation level. For a correctly predicted branch, the status of the checkpointed resources is cleared. For a branch misprediction, the ST6x86 processor generates the correct fetch address and uses the checkpointed values to restore the machine state in a single clock. In order to maintain compatibility, writes that result from speculatively executed instructions are not permitted to update the cache or external memory until the appropriate branch is resolved. Speculative execution continues until one of the following conditions occurs: 1) A branch or floating point operation is decoded and the speculation level is already at four. 2) An exception or a fault occurs. 3) The write buffers are full. 4) An attempt is made to modify a non-checkpointed resource (i.e., segment registers, system flags). 1.3 Cache Units The ST6x86 CPU employs two caches, the Unified Cache and the Instruction Line Cache (Figure 1.2). 1.3.1 Unified Cache The 16-KByte unified write-back cache functions as the primary data cache and as the secondary instruction cache. Configured as a four-way set-associative cache, the cache stores up to 16 KBytes of code and data in 512 lines. The cache is dual-ported and allows any two of the following operations to occur in parallel: - Code fetch - Data read (X pipe, Y pipeline or FPU) - Data write (X pipe, Y pipeline or FPU) The unified cache uses a pseudo-LRU replacement algorithm and can be configured to allocate new lines on read misses only or on read and write misses.
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1.3.2 Instruction Line Cache The fully associative 256-byte instruction line cache serves as the primary instruction cache. The instruction line cache is filled from the unified cache through the data bus. Fetches from the integer unit that hit in the instruction line cache do not access the unified cache. If an instruction line cache miss occurs, the instruction line data from the unified cache is transferred to the instruction line cache and the integer unit, simultaneously. Figure 1.2. Cache Unit Operations The instruction line cache uses a pseudo-LRU replacement algorithm. To ensure proper operation in the case of self-modifying code, any writes to the unified cache are checked against the contents of the instruction line cache. If a hit occurs in the instruction line cache, the appropriate line is invalidated.
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1.4 Memory Management Unit The Memory Management Unit (MMU), shown in Figure 1.3, translates the linear address supplied by the IU into a physical address to be used by the unified cache and the bus interface. Memory management procedures are x86 compatible, adhering to standard paging mechanisms. The ST6x86 MMU includes two paging mechanisms (Figure 1.3), a traditional paging mechanism, and a ST6x86 variable-size paging mechanism. 1.4.1 Variable-Size Paging Mechanism The SGS-THOMSON variable-size paging mechanism allows software to map pages between 4 KBytes and 4 GBytes in size. The large contiguous memories provided by this mechanism help avoid TLB (Translation Lookaside Buffer) thrashing associated with some operating systems and applications. For example, use of a single large page instead of a series of small 4-KByte pages can greatly improve performance in an application using a large video memory buffer.
Figure 1.3. Paging Mechanism within the Memory Management Unit
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1.4.2 Traditional Paging Mechanism The traditional paging mechanism has been enhanced on the ST6x86 CPU with the addition of the Directory Table Entry (DTE) cache and the Victim TLB. The main TLB (Translation Lookaside Buffer) is a direct-mapped 128-entry cache for page table entries. The four-entry fully associative DTE cache stores the most recent DTE accesses. If a Page Table Entry (PTE) miss occurs followed by a DTE hit, only a single memory access to the PTE table is required. The Victim TLB stores PTEs which have been displaced from the main TLB due to a TLB miss. If a PTE access occurs while the PTE is stored in the victim TLB, the PTE in the victim TLB is swapped with a PTE in the main TLB. This has the effect of selectively increasing TLB associativity. The ST6x86 CPU updates the eight-entry fully associative victim TLB on an oldest entry replacement basis. 1.5 Floating Point Unit The ST6x86 Floating Point Unit (FPU) interfaces to the integer unit and the cache unit through a 64-bit bus. The ST6x86 FPU is x87 instruction set compatible and adheres to the IEEE-754 standard. Since most applications contain FPU instructions mixed with integer instructions, the ST6x86 FPU achieves high performance by completing integer and FPU operations in parallel. FPU Parallel Execution The ST6x86 CPU executes integer instructions in parallel with FPU instructions. Integer instructions may complete out of order with respect to the FPU instructions. The ST6x86 CPU maintains x86 compatibility by signaling exceptions and issuing write cycles in program order. As previously discussed, FPU instructions are always dispatched to the integer unit's X pipeline. The address calculation stage of the X pipeline checks for memory management exceptions and accesses memory operands used by the FPU. If no exceptions are detected, the ST6x86 CPU checkpoints the state of the CPU and, during AC2, dispatches the floating point instruction to the FPU instruction queue. The ST6x86 CPU can then complete any subsequent integer instructions speculatively and out of order relative to the FPU instruction and relative to any potential FPU exceptions which may occur. As additional FPU instructions enter the pipeline, the ST6x86 CPU dispatches up to four FPU instructions to the FPU instruction queue. The ST6x86 CPU continues executing speculatively and out of order, relative to the FPU queue, until the ST6x86 CPU encounters one of the conditions that causes speculative execution to halt. As the FPU completes instructions, the speculation level decreases and the checkpointed resources are available for reuse in subsequent operations. The ST6x86 FPU also uses a set of four write buffers to prevent stalls due to speculative writes. 1.6 Bus Interface Unit The Bus Interface Unit (BIU) provides the signals and timing required by external circuitry. The signal descriptions and bus interface timing information is provided in Chapters 3 and 4 of this manual.
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2.0 Programming Interface In this chapter, the internal operations of the ST6x86 CPU are described mainly from an application programmer's point of view. Included in this chapter are descriptions of processor initialization, the register set, memory addressing, various types of interrupts and the shutdown and halt process. An overview of real, virtual 8086, and protected operating modes is also included in this chapter. The FPU operations are described separately at the end of the chapter. This manual does not and is not intended to - describe the ST6X86 microprocessor or its operations at the circuit level.
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Table 2.1. Initialized Register Controls
REGISTER EAX EBX ECX EDX EBP ESI EDI ESP EFLAGS EIP ES CS SS DS FS GS IDTR GDTR LDTR TR CR0 CR2 CR3 CCR (0-5) ARR (0-7) RCR (0-7) DIR0 DIR1 DR7 REGISTER NAME Accumulator Base Count Data Base Pointer Source Index Destination Index Stack Pointer Flag Word Instruction Pointer Extra Segment Code Segment Stack Segment Data Segment Extra Segment Extra Segment INITIAL IZED CONTENTS xxxx xxxxh xxxx xxxxh xxxx xxxxh 05 + Device ID xxxx xxxxh xxxx xxxxh xxxx xxxxh xxxx xxxxh 0000 0002h 0000 FFF0h 0000h F000h 0000h 0000h 0000h 0000h Base address set to 0000 0000h. Limit set to FFFFh. Base address set to FFFF 0000h. Limit set to FFFFh. Base address set to 0000 0000h. Limit set to FFFFh. Base address set to 0000 0000h. Limit set to FFFFh. Base address set to 0000 0000h. Limit set to FFFFh. Base address set to 0000 0000h. Limit set to FFFFh. Device ID = 31h or 33h (2X clock) Device ID = 35h or 37h (3X clock) COMMENTS 0000 0000h indicates self-test passed.
Interrupt Descriptor Table RegisBase = 0, Limit = 3FFh ter Global Descriptor Table Register Local Descriptor Table Register Task Register Machine Status Word Control Register 2 Control Register 3 Configuration Control (0-5) Address Region Registers (0-7) Region Control Registers (0-7) Device Identification 0 Device Identification 1 Debug Register 7 xxxx xxxxh, xxxxh xxxx xxxxh, xxxxh xxxxh 6000 0010h xxxx xxxxh xxxx xxxxh 00h 00h 00h 31h or 33h (2X clock) 35h or 37h (3X clock) Step ID + Revision ID 0000 0400h
Note: x = Undefined value
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2.1 ST6x86 Configuration Registers A set of 24 on-chip ST6x86 configuration registers are used to enable features in the ST6x86 CPU. These registers assign non-cached memory areas, set up SMM, provide CPU identification information and control various features such as cache write policy, and bus locking control. There are four groups of registers within the ST6x86 configuration register set: - 6 Configuration Control Registers (CCRx) - 8 Address Region Registers (ARRx) - 8 Region Control Registers (RCRx) - 2 Device Identification Registers (DIRx) Access to the configuration registers is achieved by writing the register index number for the configuration register to I/O port 22h. I/O port 23h is then used for data transfer. Each I/O port 23h data transfer must be preceded by a valid I/O port 22h register index selection. Otherwise, the current 22h, and the second and later I/O port 23h operations communicate through the I/O port to produce external I/O cycles. All reads from I/O port 22h produce external I/O cycles. Accesses that hit within the on-chip configuration registers do not generate external I/O cycles. After reset, configuration registers with indexes CO-CFh and FE-FFh are accessible. To prevent potential conflicts with other devices which may use ports 22 and 23h to access their registers, the remaining registers (indexes D0-FDh) are accessible only if the MAPEN(3-0) bits in CCR3 are set to 1h. See Figure 2.4 (Page 24) for more information on the MAPEN(3-0) bit locations. If MAPEN[3-0] = 1h, any access to indexes in the range 00-FFh will not create external I/O bus cycles. Registers with indexes C0-CFh, FE, FFh are accessible regardless of the state of MAPEN[3-0]. If the register index number is outside the C0-CFh or FE-FFh ranges, and MAPEN[3-0] are set to 0h, external I/O bus cycles occur. Table 2.2 (Page 20) lists the MAPEN[3-0] values required to access each ST6x86 configuration register. All bits in the configuration registers are initialized to zero following reset unless specified otherwise. Valid register index numbers include C0h to E3h, E8h, E9h, FEh and FFh (if MAPEN[3-0] = 1). 2.1.1 Configuration Control Registers (CCR0 - CCR5) control several functions, including non-cacheable memory, write-back regions, and SMM features. A list of the configuration registers is listed in Table 2.2 (Page 20). The configuration registers are described in greater detail in the following pages.
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Table 2.2. ST6x86 CPU Configuration Registers
REGISTER NAME ACRONYM REGISTER INDEX C0h C1h C2h C3h E8h E9h C4h - C6h C7h - C9h CAh - CCh CDh - CFh D0h - D2h D3h - D5h D6h - D8h D9h - DBh DCh DDh DEh DFh E0h E1h E2h E3h FEh FFh WIDTH (Bits) 8 8 8 8 8 8 24 24 24 24 24 24 24 24 8 8 8 8 8 8 8 8 8 8 MAPEN VALUE NEEDED FOR ACCESS x x x x 1 1 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 x x
Configuration Control 0 Configuration Control 1 Configuration Control 2 Configuration Control 3 Configuration Control 4 Configuration Control 5 Address Region 0 Address Region 1 Address Region 2 Address Region 3 Address Region 4 Address Region 5 Address Region 6 Address Region 7 Region Control 0 Region Control 1 Region Control 2 Region Control 3 Region Control 4 Region Control 5 Region Control 6 Region Control 7 Device Identification 0 Device Identification 1 Note: x = Don't Care
CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 ARR0 ARR1 ARR2 ARR3 ARR4 ARR5 ARR6 ARR7 RCR0 RCR1 RCR2 RCR3 RCR4 RCR5 RCR6 RCR7 DIR0 DIR1
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Figure 2.1. ST6x86 Configuration Control Register 0 (CCR0)
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 NC1 0 Reserved
Table 2.3. CCR0 Bit Definitions
BIT POSITION NAME DESCRIPTION No Cache 640 KByte - 1 MByte If = 1: Address region 640 KByte to 1 MByte is non-cacheable. If = 0: Address region 640 KByte to 1 MByte is cacheable.
1
NC1
Note: Bits 0, 2 through 7 are reserved.
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Figure 2.2. ST6x86 Configuration Control Register 1 (CCR1)
7 SM3 6 Reserved 5 Reserved 4 NO_LOCK 3 Reserved 2 SMAC 1 USE_SMI 0 Reserved
Table 2.4. CCR1 Bit Definitions
BIT POSITION NAME DESCRIPTION Enable SMM and SMIACT# Pins If = 1: SMI# and SMIACT# pins are enabled. If = 0: SMI# pin ignored and SMIACT# pin is driven inactive. System Management Memory Access If = 1: Any access to addresses within the SMM address space, access system management memory instead of main memory. SMI# input is ignored. Used when initializing or testing SMM memory. If = 0: No effect on access. Negate LOCK# If = 1: All bus cycles are issued with LOCK# pin negated except page table accesses and interrupt acknowledge cycles. Interrupt acknowledge cycles are executed as locked cycles even though LOCK# is negated. With NO_LOCK set, previously noncacheable locked cycles are executed as unlocked cycles and therefore, may be cached. This results in higher performance. Refer to Region Control Registers for information on eliminating locked CPU bus cycles only in specific address regions. SMM Address Space Address Region 3 If = 1: Address Region 3 is designated as SMM address space.
1
USE_SMI
2
SMAC
4
NO_LOCK
7
SM3
Note: Bits 0, 3, 5 and 6 are reserved.
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Figure 2.3. ST6x86 Configuration Control Register 2 (CCR2)
7 USE_SUSP 6 Reserved 5 Reserved 4 WPR1 3 SUSP_HLT 2 LOCK_NW 1 Reserved 0 Reserved
Table 2.5. CCR2 Bit Definitions
BIT POSITION NAME DESCRIPTION Lock NW If = 1: NW bit in CR0 becomes read only and the CPU ignores any writes to the NW bit. If = 0: NW bit in CR0 can be modified. Suspend on Halt If = 1: Execution of the HLT instruction causes the CPU to enter low power suspend mode. Write-Protect Region 1 If = 1: Designates any cacheable accesses in 640 KByte to 1 MByte address region are write protected. Use Suspend Mode (Enable Suspend Pins) If = 1: SUSP# and SUSPA# pins are enabled. If = 0: SUSP# pin is ignored and SUSPA# pin floats.
2
LOCK_NW
3
SUSP_HLT
4
WPR1
7
USE_SUSP
Note: Bits 0,1, 5 and 6 are reserved.
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Figure 2.4. ST6x86 Configuration Control Register 3 (CCR3)
7 6 MAPEN 5 4 3 Reserved 2 LINBRST 1 NMI_EN 0 SMI_LOCK
Table 2.6. CCR3 Bit Definitions
BIT POSITION NAME DESCRIPTION SMI Lock If = 1: The following SMM configuration bits can only be modified while in an SMI service routine: CCR1: USE_SMI, SMAC, SM3 CCR3: NMI_EN ARR3: Starting address and block size. Once set, the features locked by SMI_LOCK cannot be unlocked until the RESET pin is asserted. NMI Enable If = 1: NMI interrupt is recognized while servicing an SMI interrupt. NMI_EN should be set only while in SMM, after the appropriate SMI interrupt service routine has been setup. If = 1: Use linear address sequence during burst cycles. If = 0: Use "1 + 4" address sequence during burst cycles. The "1 + 4" address sequence is compatible with Pentium's burst address sequence. MAP Enable If = 1h: All configuration registers are accessible. If = 0h: Only configuration registers with indexes C0-CFh, FEh and FFh are accessible.
0
SMI_LOCK
1
NMI_EN
2
LINBRST
4-7
MAPEN
Note: Bit 3 is reserved.
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Figure 2.5. ST6x86 Configuration Control Register 4 (CCR4)
7 CPUID 6 Reserved 5 Reserved 4 DTE_EN 3 Reserved 2 1 IORT 0
Table 2.7. CCR4 Bit Definitions
BIT POSITION NAME DESCRIPTION I/O Recovery Time Specifies the minimum number of bus clocks between I/O accesses: 0h = 1 clock delay 1h = 2 clock delay 2h = 4 clock delay 3h = 8 clock delay 4h = 16 clock delay 5h = 32 clock delay (default value after RESET) 6h = 64 clock delay 7h = no delay Enable Directory Table Entry Cache If = 1: the Directory Table Entry cache is enabled. Enable CPUID instruction. If = 1: the ID bit in the EFLAGS register can be modified and execution of the CPUID instruction occurs as documented in section 6.3. If = 0: the ID bit in the EFLAGS register can not be modified and execution of the CPUID instruction causes an invalid opcode exception.
0-2
IORT
4
DTE_EN
7
CPUID
Note: Bits 3 and bits 5 and 6 are reserved.
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Figure 2.6. ST6x86 Configuration Control Register 5 (CCR5)
7 Reserved 6 Reserved 5 ARREN 4 LBR1 3 Reserved 2 Reserved 1 Reserved 0 WT_ALLOC
Table 2.8. CCR5 Bit Definitions
BIT POSITION NAME DESCRIPTION Write-Through Allocate If = 1: New cache lines are allocated for read and write misses. If = 0: New cache lines are allocated only for read misses. Local Bus Region 1 If = 1: LBA# pin is asserted for all accesses to the 640 KByte to 1 MByte address region. Enable ARR Registers If = 1: Enables all ARR registers. If = 0: Disables the ARR registers. If SM3 is set, ARR3 is enabled regardless of the setting of ARREN.
0
WT_ALLOC
4
LBR1
5
ARREN
Note: Bits 1 through 3 and 6 though 7 are reserved.
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2.1.2 Address Region Registers the region is not cached. The RCRs take precedence in this case. A register index, shown in Table 2.9 (Page 28) is used to select one of three bytes in each ARR. The starting address of the ARR address region, selected by the START ADDRESS field, must be on a block size boundary. For example, a 128 KByte block is allowed to have a starting address of 0 KBytes, 128 KBytes, 256 KBytes, and so on. The SIZE field bit definition is listed in Table 2.10, on page 28. If the SIZE field is zero, the address region is of zero size and thus disabled.
The Address Region Registers (ARR0 - ARR7) (Figure 2.7) are used to specify the location and size for the eight address regions. Attributes for each address region are specified in the Region Control Registers (RCR0-RCR7). ARR7 and RCR7 are used to define system main memory and differ from ARR0-6 and RCR0-6. With non-cacheable regions defined on-chip, the ST6x86 CPU delivers optimum performance by using advanced techniques to eliminate data dependencies and resource conflicts in its execution pipelines. If KEN# is active for accesses to regions defined as non-cacheable by the RCRs,
Figure 2.7. Address Region Registers (ARR0 - ARR7)
START ADDRESS Memory Address Bits A31-A24 7 0 7 Memory Address Bits A23-A16 0 7 Memory Address Bits A15-A12 4 3 SIZE Size Bits 3-0 0
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Table 2.9. ARR0 - ARR7 Register Index Assignment
ARR Register ARR0 ARR1 ARR2 ARR3 ARR4 ARR5 ARR6 ARR7 Memory Address (A31 - A24) C4h C7h CAh CDh D0h D3h D6h D9h Memory Address (A23 - A16) C5h C8h CBh CEh D1h D4h D7h DAh Memory Address (A15 - A12) C6h C9h CCh CFh D2h D5h D8h DBh Address Region Size (3 - 0) C6h C9h CCh CFh D2h D5h D8h DBh
Table 2.10. Bit Definitions for SIZE Field
BLOCK SIZE SIZE (3-0) ARR0-6 0h 1h 2h 3h 4h 5h 6h 7h Disabled 4 KBytes 8 KBytes 16 KBytes 32 KBytes 64 KBytes 128 KBytes 256 KBytes ARR7 Disabled 256 KBytes 512 KBytes 1 MBytes 2 MBytes 4 MBytes 8 MBytes 16 MBytes 8h 9h Ah Bh Ch Dh Eh Fh SIZE (3-0) ARR0-6 512 KBytes 1 MBytes 2 MBytes 4 MBytes 8 MBytes 16 MBytes 32 MBytes 4 GBytes ARR7 32 MBytes 64 MBytes 128 MBytes 256 MBytes 512 MBytes 1 GBytes 2 GBytes 4 GBytes BLOCK SIZE
.
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2.1.3 Region Control Registers Overlapping Conditions Defined. If two regions specified by ARRx registers overlap and conflicting attributes are specified, the following attributes take precedence: LBA# pin is asserted Write-back is disabled Writes are not gathered Strong locking takes place Strong write ordering takes place The overlapping regions are non-cacheable.
The Region Control Registers (RCR0 - RCR7) specify the attributes associated with the ARRx address regions. The bit definitions for the region control registers are shown in Figure 2.8 (Page 30) and in Table 2.11 (Page 30). Cacheability, weak write ordering, weak locking, write gathering, cache write through policies and control of the LBA# pin can be activated or deactivated using the attribute bits. If an address is accessed that is not in a memory region defined by the ARRx registers, the following conditions will apply: - LBA# pin is asserted - If the memory address is cached, write-back is enabled if WB/WT# is returned high. - Writes are not gathered - Strong locking takes place - Strong write ordering takes place - The memory access is cached, if KEN# is returned asserted.
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Figure 2.8. Region Control Registers (RCR0-RCR7)
7 Reserved 6 Reserved 5 NLB 4 WT 3 WG 2 WL 1 WWO 0 RCD / RCE*
*Note: RCD is defined for RCR0-RCR6. RCE is defined for RCR7.
Table 2.11. RCR0-RCR7 Bit Definitions
RCRx 0- 6 7 0- 7 0- 7 0- 7 0- 7 0- 7 BIT POSITION 0 0 1 2 3 4 5 NAME RCD RCE WWO WL WG WT NLB DESCRIPTION If = 1: Disables caching for address region specified by ARRx. If = 1: Enables caching for address region ARR7. If = 1: Weak write ordering for address region specified by ARRx. If = 1: Weak locking for address region specified by ARRx. If = 1: Write gathering for address region specified by ARRx. If = 1: Address region specified by ARRx is write-through. If = 1:LBA# pin is not asserted for access to address region specified by ARRx
Note: Bits 6 and 7 are reserved.
Region Cache Disable (RCD). Setting RCD to a one defines the address region as non-cacheable. Whenever possible, the RCRs should be used to define non-cacheable regions rather than using external address decoding and driving the KEN# pin. Region Cache Enable (RCE). Setting RCE to a one defines the address region as cacheable. RCE is used to define the system main memory as cacheable memory. It is implied that memory outside the region is non-cacheable. Weak Write Ordering (WWO). Setting WWO=1 enables weak write ordering for that address region. Enabling WWO allows the ST6x86 CPU to issue writes in its internal cache in an order different than their order in the code stream. External writes always occur in order (strong ordering). Therefore, this should only be enabled for memory regions that are NOT sensitive to this condition. WWO should not be enabled for memory mapped I/O. WWO only applies to memory regions that have been cached and designated as write-back. It also applies to previously cached addresses even if the cache has been disabled (CD=1). Enabling WWO removes the write-ordering restriction and improves performance due to reduced pipeline stalls. Weak Locking (WL). Setting WL=1 enables weak locking for that address region. With WWO enabled, all bus cycles are issued with the LOCK# pin negated except for page table accesses and interrupt acknowledge cycles. Interrupt acknowl-
edge cycles are executed as locked cycles even though LOCK# is negated. With WL=1, previously non-cacheable locked cycles are executed as unlocked cycles and therefore, may be cached, resulting in higher performance. The NO_LOCK bit of CCR1 enables weak locking for the entire address space. The WL bit allows weak locking only for specific address regions. WL is independent of the cacheability of the address region. Write Gathering (WG). Setting WG=1 enables write gathering for the associated address region. Write gathering allows multiple byte, word, or dword sequential address writes to accumulate in the on-chip write buffer. (As instructions are executed, the results are placed in a series of output buffers. These buffers are gathered into the finial output buffer). When access is made to a non-sequential memory location or when the 8-byte buffer becomes full, the contents of the buffer are written on the external 64-bit data bus. Performance is enhanced by avoiding as many as seven memory write cycles. WG should not be used on memory regions that are sensitive to write cycle gathering. WG can be enabled for both cacheable and non-cacheable regions. Write Through (WT). Setting WT=1 defines the address region as write-through instead of write-back, assuming the region is cacheable. Regions where system ROM are loaded (shadowed or not) should be defined as write through.
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LBA # Not Asserted (NLB). Setting NLB = 1 prevents the microprocessor from asserting the Local Bus Access (LBA#) output pin for accesses to that address region. The RCR regions may be used to define non-local bus address regions. The LBA# pin could then be asserted for all regions, except those defined by the RCRs. The LBA# signal may be used by the external hardware (e.g., chipsets) as an indication that local bus accesses are occurring.
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3.0 ELECTRICAL SPECIFICATIONS 3.1 Electrical Connections This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, DC characteristics, and AC characteristics. All voltage values in Electrical Specifications are measured with respect to VSS unless otherwise noted. 3.1.1 Power and Ground Connections and Decoupling Testing and operating the ST6x86 CPU requires the use of standard high frequency techniques to reduce parasitic effects. The high clock frequencies used in the ST6x86 CPU and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VCC and GND pins. The ST6x86 CPU contains 296 pins with 53 pins connected to VCC and 53 connected to VSS (ground). 3.1.2 Pull-Up/Pull-Down Resistors Table 3.1 lists the input pins that are internally connected to pull-up and pull-down resistors. The pull-up resistors are connected to VCC and the pull-down resistors are connected to VSS. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted. Table 3.1. Pins Connected to Internal Pull-Up and Pull Down Resistors
SIGNAL BRDYC# CLKMUL QDUMP# SMI# SUSP# TCK TDI TMS TRST# Reserved Reserved Reserved Reserved PIN NO. Y3 Y33 AL7 AB34 Y34 M34 N35 P34 Q33 J33 W35 Y35 AN35 20-k pull-down 20-k pull-up RESISTOR 20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up (see text)
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Absolute Maximum Ratings
ST6x86
3.1.3 Unused Input Pins All inputs not used by the system designer and not listed in Table 3.1 should be connected either to ground or to VCC. Connect active-high inputs to ground through a 20 k ( 10%) pull-down resistor and active-low inputs to VCC through a 20 k ( 10%) pull-up resistor to prevent possible spurious operation. 3.1.4 NC and Reserved Pins Pins designated NC have no internal connections. Pins designated RESV or RESERVED should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. Table 3.2. Absolute Maximum Ratings
PARAMETER Operating Case Temperature Storage Temperature Supply Voltage, VCC Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK MIN -65 -65 -0.5 -0.5 MAX 110 150 4.0 VCC +0.5 10 25 UNITS C C V V mA mA NOTES Power Applied
3.2 Absolute Maximum Ratings The following table lists absolute maximum ratings for the ST6x86 CPU microprocessors. Stresses beyond those listed under Table 3.2 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" ST6x86 is possible. Exposure to conditions beyond Table 3.2 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings may also result in reduced useful life and reliability.
Power Applied Power Applied
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3.3 Recommended Operating Conditions Table 3.3 presents the recommended operating conditions for the ST6x86 CPU device. Table 3.3. Recommended Operating Conditions
PARAMETER TC Operating Case Temperature VCC Supply Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage IOH High-Level Output Current All outputs except A20-A3 and W/R# A20-A3 and W/R# IOL Low-Level Output Current All outputs except A20-A3 and W/R# A20-A3 and W/R# MIN 0 3.15 2.0 -0.3 MAX 70 3.7 5.5 0.8 -1.0 -2.0 5.0 10.0 UNITS C V V V NOTES Power Applied
mA
VO=VOH(MIN)
mA
VO=VOL(MAX}
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DC Characteristics
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3.4 DC Characteristics Table 3.4. DC Characteristics (at Recommended Operating Conditions)
PARAMETER VOL Output Low Voltage IOL = 5 mA 2.4 15 MIN TYP MAX 0.4 UNITS V V NOTES
VOH Output High Voltage IOH = -1 mA II Input Leakage Current For all pins except those listed in Table 4-1. Input Leakage Current For all pins with internal pull-downs. Input Leakage Current For all pins with internal pull-ups. Active ICC 80 MHz 100 MHz 110 MHz 120 MHz 133 MHz
A A A
0 < VIN < VCC VIH = 2.4 V See Table 3-1. VIL = 0.45 V See Table 3-1.
IIH
200 -400
IIL ICC
3.9 4.5 4.8 5.1 5.5 43 48 50 51 54 35
4.7 5.4 5.8 6.1 6.6 75 80 83 105 115 75 15 20 25 15
A
Note 1, 5
ICCSM Suspend Mode ICC 80MHz 100 MHz 110 MHz 120 MHz 133 MHz ICCSS Standby ICC 0 MHz (Suspended/CLK Stopped) CINInput Capacitance COUTOutput Capacitance CIOI/O Capacitance CCLKCLK Capacitance mA Note 1, 3, 5
mA pF pF pF pF
Note 4,5 f = 1 MHz, Note 2 f = 1 MHz, Note 2 f = 1 MHz, Note 2 f = 1 MHz, Note 2
Notes: 1. Frequency (MHz) ratings refer to the internal clock frequency. 2. Not 100% tested. 3. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded (static IOUT = 0 mA). 4. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static and all outputs unloaded (static IOUT = 0 mA). 5. Typical, measured at VCC = 3.3 V
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AC Characteristics
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3.5 AC Characteristics Table 3.6 through 3.11 (Pages 38 through 43) list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 3.1 (Page 37) and Figure 3.2 (Page 38). The ris, ing clock edge reference level VREF and other reference levels are shown in Table 3.5. Input or output signals must cross these levels during testing. Figure 3.1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation.
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AC Characteristics
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Figure 3.1. Drive Level and Measurement Points for Switching Characteristics
Table 3.5. Drive Level and Measurement Points for Switching Characteristics
SYMBOL VREF VIHD VILD Note: Refer to Figure 3-1. VOLTAGE (Volts) 1.5 2.3 0
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AC Characteristics
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Table 3.6. Clock Specifications Tcase = 0 C to 70 C, See Figure 3.2
SYMBOL PARAMETER 40-MHz BUS MIN CLK Frequency T1 T2 T3 T4 T5 T6 CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time 9 9 0.15 0.15 2 2 25 250 7 7 0.15 0.15 2 2 MAX 40 20 250 4.0 4.0 0.15 0.15 1.5 1.5 50-MHz BUS MIN 55-MHz BUS 60-MHz BUS MIN 66-MHz BUS UNITS
MAX MIN MAX 50 18 250 55
MAX MIN MAX 60 66.6 30.0 250 4.0 4.0 1.5 1.5 0.15 0.15 1.5 1.5 MHz ns ps ns ns ns ns
16.67 33.33 15.0 250 4.0 4.0 0.15 0.15
Figure 3.2. CLK Timing and Measurement Points
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Table 3.7. Output Valid Delays C L=50 pF, Tcase = 0C to 70 C, See Figure 3.3
SYMBOL PARAMETER 40-MHz BUS MIN MAX A31-A3, BE7#-BEO# CACHE#, D/C#, LBA#, LOCK#, PCD, PWT, SCYC, SMIACT#, W/R# ADS#, M/IO# ADSC# AP APCHK#, FERR# PCHK#, 50-MHz BUS MIN MAX 55-MHz BUS MIN MAX 60-MHz BUS MIN MAX 66-MHz BUS MIN MAX UNITS
T7
3
14
1
12
1
7
1
8
1
7
ns
T 7b T8 T9 T10 T11 T12a T12b T13 T14
3 3 3 3 3 3 3 3 3
14 14 14 16 14 14 14 14 16
1 1 1 1 1.3 1 1.1 1 1
12 12 12 14 12 12 12 12 14
1 1 1 1 1.3 1 1.1 1 1
7.5 7 8.5 8.3 9 8 7 8 8
1 1 1 1 1.3 1 1.1 1 1
7.5 8 8.5 7 9 8 7 8 8
1 1 1 1 1.3 1 1.1 1 1
6 7 8.5 7 7.5 8 6 8 8
ns ns ns ns ns ns ns ns ns
D63-DO, DP7-DPO (Write) HIT# HITM# BREQ, HLDA SUSPA#
Figure 3.3. Output Valid Delay Timing
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Table 3.8. Output Float Delays C L=50 pFcase = 0 C to 70 C, See Figure 3.4
SYMBOL PARAMETER 40-MHz BUS MIN MAX A31-A3, ADS#, BE7#-BE0#, BREQ, CACHE#, D/C#, LBA#, LOCK#, M/IO#, PCD, PWT, SCYC, SMIACT#, W/R# AP D63-D0, DP7-DP0 (Write) 50-MHz BUS MIN MAX 55-MHz BUS MIN MAX 60-MHz BUS MIN MAX 66-MHz BUS MIN MAX UNITS
T15
19
16
10
10
10
ns
T16 T17
19 19
16 16
10 10
10 10
10 10
ns ns
Figure 3.4. Output Float Delay Timing
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Table 3.9. Input Setup Times
Tcase = 0 C to 70 C, See Figure 3.5 SYMBOL T18 PARAMETER A20M#, FLUSH#, IGNNE#, SUSP# AHOLD, BHOLD, BOFF#, DHOLD, HOLD BRDY# BRDYC# A31-A3, AP, BE7#-BE0#, D63-D0 (Read), DP7-DP0 (Read) EADS#, INV INTR, NMI, RESET, SMI#, WM_RST EWBE#, KEN#, NA#, WB/WT# QDUMP# 40-MHz BUS MIN 5 50-MHz BUS MIN 5 55-MHz BUS MIN 5 60-MHz BUS MIN 5 66-MHz BUS MIN 5 UNITS ns
T19 T20 T21 T22 T22a T23 T24
5 5 5 5 3.8 5 5
5 5 5 5 3.8 5 5
5 5 5 5 3.8 5 5
5 5 5 5 3 5 5
5 5 5 5 3 5 5
ns ns ns ns ns ns ns
T25 T26
5 5
5 5
4.5 5
4.5 5
4.5 5
ns ns
Table 3.10. Input Hold Times
Tcase = 0 Cto 70 C, See Figure 3.5 SYMBOL T27 PARAMETER A20M#, FLUSH#, IGNNE#, SUSP# AHOLD, BHOLD, BOFF#, DHOLD, HOLD BRDY# BRDYC# A31-A3, AP, BE7#-BE0# D63-D0, DP7-DP0 (Read) EADS#, INV INTR, NMI, RESET, SMI#, WM_RST EWBE#, KEN#, NA#, WB/WT# QDUMP# 40-MHz BUS MIN 3 50-MHz BUS MIN 2 55-MHz BUS MIN 1 60-MHz BUS MIN 1 66-MHz BUS MIN 1
UNITS ns
T28 T29 T30 T31a T31b T32 T33
3 3 3 3 3 3 3
2 2 2 2 2 2 2
1 1 1 1 2 1 1
1 1 1 1 2 1 1
1 1 1 1 2 1 1
ns ns ns ns ns ns ns
T34 T35
3 3
2 2
1 1
1 1
1 1
ns ns
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Figure 3.5. Input Setup and Hold Timing
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Table 3.11. JTAG AC Specifications
ALL BUS FREQUENCIES SYMBOL PARAMETER MIN TCK Frequency (MHz) T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49 TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDO Valid Delay Non-test Outputs Valid Delay TDO Float Delay Non-test Outputs Float Delay TRST# Pulse Width TDI, TMS Setup Time Non-test Inputs Setup Time TDI, TMS Hold Time Non-test Inputs Hold Time 40 20 20 13 13 3 3 50 25 25 5 5 20 20 25 25 MAX 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-6 3-6 3-6 3-6 3-6 3-7 3-7 3-7 3-7 3-8 3-7 3-7 3-7 3-7 UNITS FIGURE
Figure 3.6. TCK Timing and Measurement Points
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ST6x86
Figure 3.7. JTAG Test Timings
Figure 3.8. Test Reset Timing
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4.0 MECHANICAL SPECIFICATIONS 4.1 296-Pin CPGA Package The pin assignments for the ST6x86 CPUin a 296-pin CPGA package are shown in Figure 4.1. The pins are listed by signal name in Table 4.1 (Page 46) and by pin number in Table 4.2 (Page 47). Dimensions are shown in Table 4.2 (Page 47) and Table 4.3 (Page 49). Figure 4.1. 296-Pin CPGA Package Pin Assignments
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ST6x86
Table 4.1. 296-Pin CPGA Package Signal Names Sorted by Pin Number
Pin
A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27
Signal
NC D41 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc D22 D18 D15 NC NC D43 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss D20 D16 D13 D11 NC D47 D45 DP4 D38 D36 D34 D32 D31 D29 D27 D25 DP2 D24
Pin
C29 C31 C33 C35 C37 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 E1 E3 E5 E7 E9 E33 E35 E37 F2 F4 F6 F34 F36 G1 G3 G5 G33 G35 G37 H2 H4 H34 H36 J1 J3 J5 J33
Signal
D21 D17 D14 D10 D9 D50 D48 D44 D40 D39 D37 D35 D33 DP3 D30 D28 D26 D23 D19 DP1 D12 D8 DP0 D54 D52 D49 D46 D42 D7 D6 Vcc DP6 D51 DP5 D5 D4 Vcc D55 D53 D3 D1 Vcc Vss D56 NC Vss Vcc D57 D58 Reserve d
Pin
J35 J37 K2 K4 K34 K36 L1 L3 L5 L33 L35 L37 M2 M4 M34 M36 N1 N3 N5 N33 N35 N37 P2 P4 P34 P36 Q1 Q3 Q5 Q33 Q35 Q37 R2 R4 R34 R36 S1 S3 S5 S33 S35 S37 T2 T4 T34 T36 U1 U3 U5 U33
Signal
D2 Vcc Vss D59 D0 Vss Vcc D61 D60 Vcc NC Vcc Vss D62 TCK Vss Vcc D63 DP7 TDO TDI Vcc Vss NC TMS Vss Vcc Reserved FERR# TRST# NC Vcc Vss Reserved BHOLD Vss Vcc Reserved LBA# Reserved DHOLD Vcc Vss MI/O# Vcc Vss Vcc CACHE# INV Vcc
Pin
U35 U37 V2 V4 V34 V36 W1 W3 W5 W33 W35 W37 X2 X4 X34 X36 Y1 Y3 Y5 Y33 Y35 Y37 Z2 Z4 Z34 Z36 AA1 AA3 AA5 AA33 AA35 AA37 AB2 AB4 AB34 AB36 AC1 AC3 AC5 AC33 AC35 AC37 AD2 AD4 AD34 AD36 AE1 AE3 AE5 AE33
Signal
Vss Vcc Vss AHOLD SUSP# Vss Vcc EWBE# KEN# SUSPA# Reserved Vcc Vss BRDY# Reserved Vss Vcc BRDYC# NA# CLKMUL Reserved Vcc Vss BOFF# NC Vss Vcc Reserved WB/WT# WM_RST IGNNE# Vcc Vss HOLD SMI# Vss Vcc Reserved NC NMI NC Vcc Vss NC INTR Vss Vcc NC APCHK# A23
Pin
AE35 AE37 AF2 AF4 AF34 AF36 AG1 AG3 AG5 AG33 AG35 AG37 AH2 AH4 AH34 AH36 AJ1 AJ3 AJ5 AJ33 AJ35 AJ37 AK2 AK4 AK6 AK8 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 AL1 AL3 AL5 AL7 AL9 AL11 AL13 AL15 AL17 AL19
Signal
NC Vcc Vss PCHK# A21 Vss Vcc SMIACT# PCD A27 A24 Vcc Vss LOCK# A26 A22 BREQ HLDA ADS# A31 A25 Vss AP D/C# HIT# A20M# BE1# BE3# BE5# BE7# CLK RESET A19 A17 A15 A13 A9 A5 A29 A28 NC PWT HITM# QDUMP# BE0# BE2# BE4# BE6# SCYC Reserved
Pin
AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM2 AM4 AM6 AM8 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 AM36 AN1 AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37
Signal
A20 A18 A16 A14 A12 A11 A7 A3 Vss ADSC# EADS# W/R# Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss A8 A4 A30 NC NC NC FLUSH# Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc A10 A6 Reserved Vss
Note: Reserved pins are reserved for future use by SGS-TH OMSON only. Pins marked NC are not internally connected.
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Table 4.2. 296-Pin CPGA Package Pin Numbers Sorted by Signal Name
Signal
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A20M# A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ADS# ADSC# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BHOLD BOFF# BRDY# BREQ CLK
Pin
AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 AK26 AL25 AK24 AL23 AK22 AL21 AK8 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33 AJ5 AM2 V4 AK2 AE5 AL9 AK10 AL11 AK12 AL13 AK14 AL15 AK16 R34 Z4 X4 AJ1 AK18
Signal
CLKMUL D/C# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47
Pin
Y33 AK4 K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 B34 C33 A35 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 D24 C21 D22 C19 D20 C17 C15 D16 C13 D14 C11 D12 C9 D10 D8 A5 E9 B4 D6 C5 E7 C3
Signal
D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DHOLD DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# HIT# HITM# HLDA HOLD IGNNE# INTR INV KEN# LBA# LOCK# MI/O# NA# NC NC NC NC NC NC NC NC NC
Pin
D4 E5 D2 F4 E3 G5 E1 G3 H4 J3 J5 K4 L5 L3 M4 N3 S35 D36 D30 C25 D18 C7 F6 F2 N5 AM4 W3 Q5 AN7 AK6 AL5 AJ3 AB4 AA35 AD34 U5 W5 S5 AH4 T4 Y5 A3 A37 AC35 AC5 AD4 AE3 AE35 AL1 AN1
Signal
NC NC NC NC NC NC NC NC NC NMI PCD PCHK# PWT QDUMP# RESET SCYC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMI# SMIACT# SUSP# SUSPA# TCK TDI TDO TMS TRST# Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc
Pin
AN3 AN5 B2 C1 H34 L35 P4 Q35 Z34 AC33 AG5 AF4 AL3 AL7 AK20 AL17 AA3 AC3 AL19 AN35 J33 Q3 R4 S3 S33 W35 X34 Y35 AB34 AG3 V34 W33 M34 N35 N33 P34 Q33 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 AA1
Signal
Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss
Pin
AA37 AC1 AC37 AE1 AE37 AG1 AG37 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN9 E37 G1 G37 J1 J37 L1 L33 L37 N1 N37 Q1 Q37 S1 S37 T34 U1 U33 U37 W1 W37 Y1 Y37 AB2 AB36 AD2 AD36 AF2 AF36 AH2 AJ37 AL37 AM10
Signal
Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss WB/WT# W/R# WM_RST
Pin
AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM8 AN37 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 H2 H36 K2 K36 M2 M36 P2 P36 R2 R36 T2 T36 U35 V2 V36 X2 X36 Z2 Z36 AA5 AM6 AA33
BRDYC# Y3 CACHE# U3
Note: Reserved pins are reserved for future use by SGS-TH OMSON only. Pins marked NC are not internally connected.
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ST6x86
Figure 4.2. 296-Pin CPGA Package
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ST6x86
Table 4.3. 296-Pin CPGA Package Dimensions
MILLIM ETERS SYMBOL MIN A A1 A2 B D D1 D2 D3 D4 E1 E2 F L N S1 1.65 2.16 3.91 0.33 2.51 0.43 49.28 45.47 31.50 Sq. 33.99 8.00 2.41 1.14 3.05 MAX 4.70 0.43 3.07 0.51 49.91 45.97 32.00 Sq. 34.59 9.91 2.67 1.40 0.127 Diag. 3.30 296 (Pin Count) 0.065 0.085 MIN 0.154 0.013 0.099 0.017 1.940 1.790 1.240 Sq. 1.338 0.315 0.095 0.045 0.120 MAX 0.185 0.017 0.121 0.020 1.965 1.810 1.260 Sq. 1.362 0.390 0.105 0.055 0.005 Diag. 0.130 INCHES
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ST6x86
4.2 Thermal Characteristics The ST6x86 processor is designed to operate when the case temperature at the top center of the package is between 0C and 70C. The maximum die (junction) temperature, TJ MAX, and the maximum ambient temperature, TA MAX, can be calculated by substituting thermal resistance and maximum values for case or junction temperature and power dissipation in the following equations: TJ TA where: TA TJ TC P JC JA = = = = = = Ambient temperature (C) Average junction temperature (C) Case temperature at top center of package (C) Power dissipation (W) Junction-to-case thermal resistance (C/W) Junction-to-ambient thermal resistance (C/W). = T C + (P * JC) = T J - (P * JA)
Table 4.4 lists the junction-to-case and case-to-ambient thermal resistances for the SPGA package.
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ST6x86
Table 4.4. Thermal Resistances for CPGA Package With and Without Heatsinks
Thermal Resistance Laminar Air Flow (ft/min) 1.95 x 1.95 x 0.25 Heatsink 1.95 x 1.95 x 0.40 Heatsink 1.95 x 1.95 x 0.65 Heatsink Without Heatsink
JC C/W
0 0.9 0.9 0.9 1.4 0 8.4 7.7 5.9 14.7 100 7.4 6.6 4.7 11.5
CA C/W
200 6.0 4.9 3.2 9.1 400 4.0 3.2 2.1 7.3 600 3.1 2.7 1.7 7.0 800 2.6 2.1 1.4 6.2
Notes: For a ST6x86 processor with 1.25 x 1.25 x 0.40 inch CuW heat spreader. Heatsinks are omni-directional pin aluminum alloy. Features are based on standard extrusion practices for a given height. Heatsink attachment was made with 0.006 inch of thermal grease applied between heatsink and case. Maximum air temperature is assumed to be 40 C
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ST6x86
Ordering Information
Example:
ST
6X86
P120+ H
S
SGS Thomson Prefix
Device Name
Speed Equalizer P90+= 80MHz(internal) P120+=100MHz(internal) P133+=110MHz(internal) P150+=120Mhz(internal) P166+=133MHz(internal) P200+=150MHz(internal)
Package Type H = CPGA Package B = BGA Package P = PPGA Package
S= Supply Voltage (3.52 V Commercial Grade Temperature)
Please contact your nearest SGS-THOMSON sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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ST6x86
The ST6x86 CPU part numbers are listed below. ST6x86 Part Numbers
NOM Vcc (V) BUS ST6X86P90+HS ST6X86P120+HS ST6X86P133+HS ST6X86P150+HS ST6X86P166+HS 3.52 3.52 3.52 3.52 3.52 40 50 55 60 66 FREQUENCY (MHz) INTERNAL 80 100 110 120 133
PART NUMBER
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSO N Microelectronics. (c) SGS-THOMS ON Microelectronics. All rights reserved. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Taiwan - United Kingdom - U.S.A.
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