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ST14E32F ST15E32F
SERIAL ACCESS EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 32K (4K x 8) EEPROM
BRIEF DATA
COMPATIBLE WITH I2C EXTENDED ADDRESSING s TWO WIRE SERIAL INTERFACE, SUPPORTS 400kHz PROTOCOL s 100,000 ERASE/WRITE CYCLES, OVER THE FULL SUPPLY VOLTAGE RANGE s 10 YEARS DATA RETENTION s SINGLE SUPPLY VOLTAGE - 4.5V to 5.5V FOR THE ST14E32F - 2.7V to 5.5V FOR THE ST15E32F s WRITE CONTROL FEATURE s BYTE and PAGE WRITE (UP TO 32 BYTES) s BYTE, RANDOM AND SEQUENTIAL READ MODES s SELF TIMED PROGRAMING CYCLE s AUTOMATIC ADDRESS INCREMENTING s ENHANCED ESD/LATCH UP PERFORMANCES
s
Figure 1 Delivery forms
Module
Wafer
Figure 2 Pin Connection
VCC
SCL WC
Table 1 Signal Names
SDA SCL WC VCC GND Serial Data Address Input Output Serial Clock Write Control Supply Voltage Ground
ST14E32F ST15E32F
SDA
GND
SCP 028 a/AI
BD.32F/9609V1
This is Brief Data from SGS-THOMSON. Details are subject to change without notice For complete data, please contact your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: (+33) 4 42 25 87 29
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ST14E32F ST15E32F
BD.32F/9609V1
DESCRIPTION The ST14/15E32F are 32K bit electrically erasable programmable memory products (EEPROM), organized as 8 blocks of 512 x 8 bits. The ST15E32F circuit operates with a power supply value as low as 2.7V. The ST14/15E32F are compatible with the I 2C extended addressing standard, two wire serial interface which uses a bi-directional data bus and serial clock. The ST14/15E32F carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition.The ST14/15E32F behave as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 4 bits (identification code 1010), 3 bit Chip Enable input to form a 7 bit Device Select, plus one read/ write bit and terminated by an acknowledge bit. When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Both wafers (sawn or unsawn) and micromodules (on film) are available.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - Printed in France - All Rights Reserved Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a licence under the Philips I2C Patent. Right to use these 2 components in an I C system is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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