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M
* PIC16C505
PIC16C50X
1.2 Programming Mode
The programming mode for the PIC16C50X allows programming of user program memory, and the configuration word for the PIC16C50X.
EPROM Memory Programming Specification
This document includes the programming specifications for the following devices:
1.0
PROGRAMMING THE PIC16C50X
PIN DIAGRAM
PDIP, SOIC, Windowed CERDIP
The PIC16C50X can be programmed using a serial method. Due to this serial programming, the PIC16C50X can be programmed while in the user's system increasing design flexibility. This programming specification applies to PIC16C50X devices in all packages.
VDD RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/VPP RC5/T0CKI RC4
1
14
VSS RB0 RB1 RB2 RC0 RC1 RC2
PIC16C505
2 3 4 5 6 7
13 12 11 10 9 8
1.1
Hardware Requirements
RC3
The PIC16C50X requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V.
TABLE 1-1:
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16C50X
During Programming
Pin Name Pin Name RB1 RB0 RB3/MCLR/VPP VDD VSS CLOCK DATA VPP VDD VSS Pin Type I I/O P P P Clock input Data input/output Programming Power Power Supply Ground Pin Description
Legend: I = input, O = Output, P = Power
(c) 1998 Microchip Technology Inc.
DS30603A-page 1
PIC16C50X
2.0 PROGRAM MODE ENTRY
5. 6. The program/verify test mode is entered by holding pins RB0 and RB1 low while raising MCLR pin from VIL to VIHH. Once in this test mode the user program memory and the test program memory can be accessed and programmed in a serial fashion. The first selected memory location is the configuration word. RB0 and RB1 are Schmitt trigger inputs in this mode. Incrementing the PC once (using the increment address command) selects location 0x000 of the regular program memory. Afterwards all other memory locations from 0x001-03FF can be addressed by incrementing the PC. If the program counter has reached the last user program location and is incremented again, the on-chip special EPROM area will be addressed. (See Figure 2-2 to determine where the special EPROM area is located for the various PIC16C50X devices). Verify all locations (using speed verify mode) at VDD = VDDmin Verify all locations at VDD = VDDmax VDDmin is the minimum operating voltage spec. for the part. VDDmax is the maximum operating voltage spec. for the part. 2.1.2 SYSTEM REQUIREMENTS
Clearly, to implement this technique, the most stringent requirements will be that of the power supplies: VPP: VPP can be a fixed 13.0V to 13.25V supply. It must not exceed 14.0V to avoid damage to the pin and should be current limited to approximately 100mA. VDD: 2.0V to 6.5V with 0.25V granularity. Since this method calls for verification at different VDD values, a programmable VDD power supply is needed. Current Requirement: 40 mA maximum Microchip may release devices in the future with different VDD ranges which make it necessary to have a programmable VDD. It is important to verify an EPROM at the voltages specified in this method to remain consistent with Micro chip's tes t sc ree ning . F or exa mp le, a PIC16C50X specified for 4.5V to 5.5V should be tested for proper programming from 4.5V to 5.5V. Note: Any programmer not meeting the programmable VDD requirement and the verify at VDDmax and VDDmin requirement may only be classified as "prototype" or "development" programmer but not a production programmer. 2.1.3 SOFTWARE REQUIREMENTS
2.1
Programming Method
The programming technique is described in the following section. It is designed to guarantee good programming margins. It does, however, require a variable power supply for VCC. 2.1.1 1. 2. PROGRAMMING METHOD DETAILS
Essentially, this technique includes the following steps: Perform blank check at VDD = VDDmin. Report failure. The device may not be properly erased. Program location with pulses and verify after each pulse at VDD = VDDP: where VDDP = VDD range required during programming (4.5V 5.5V). Programming condition: VPP = 12.75V to 13.25V VDD = VDDP = 4.5V to 5.5V VPP must be VDD + 7.25V to keep "programming mode" active. b) Verify condition: VDD = VDDP VPP VDD + 7.5V but not to exceed 13.25V If location fails to program after "N" pulses, (suggested maximum program pulses of 8) then report error as a programming failure. Note: Device must be verified at minimum and maximum specified operating voltages as specified in the data sheet.
a)
Certain parameters should be programmable (and therefore easily modified) for easy upgrade. a) b) c) Pulse width Maximum number of pulses, present limit 8. Number of over-programming pulses: should be = (A * N) + B, where N = number of pulses required in regular programming. In our current algorithm A = 11, B = 0.
2.2
Programming Pulse Width
Program Memory Cells: When programming one word of EPROM, a programming pulse width (TPW) of 100 s is recommended. The maximum number of programming attempts should be limited to 8 per word. After the first successful verify, the same location should be over-programmed with 11X over-programming. Configuration Word: The configuration word for oscillator selection, WDT (watchdog timer) disable and code protection, and MCLR enable, requires a programming pulse width (TPWF) of 10 ms. A series of 100 s pulses is preferred over a single 10 ms pulse.
3.
4.
Once location passes `Step 2', apply 11X overprogramming, i.e., apply 11 times the number of pulses that were required to program the location. This will guarantee a solid programming margin. The overprogramming should be made "software programmable" for easy updates. Program all locations.
DS30603A-page 2
(c) 1998 Microchip Technology Inc.
PIC16C50X
FIGURE 2-1: PROGRAMMING METHOD FLOWCHART
Start Blank Check @ VDD = VDDmin
Pass?
No
Report Possible Erase Failure Continue Programming at user's option Report Programming Failure
Yes Program 1 Location @ VPP = 12.75V to 13.25V VDD = VDDP No
Yes
N > 8?
No Pass?
N=N+1 (N = # of program pulses)
Yes Increment PC to point to next location, N = 0 Apply 11N additional program pulses
No
All locations done? Yes
Verify all locations @ VDD = VDDmin
No Pass?
Report verify failure @ VDDmin
Yes Verify all locations VDD = VDD max. @ VDD = VDDmax
No Pass?
Report verify failure @ VDDmax
Yes Now program Configuration Word Verify Configuration Word @ VDDmax & VDDmin
Done
(c) 1998 Microchip Technology Inc.
DS30603A-page 3
PIC16C50X
FIGURE 2-2: PIC16C50X SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE
Address 11 (Hex) 000 Bit Number 0
NNN TTT TTT + 1 TTT + 2 TTT + 3
User Program Memory (NNN + 1) x 12 bit 0 0 0 0 0 0 0 0 ID0 ID1 ID2 ID3 For Customer Use (4 x 4 bit usable)
For Factory Use
TTT + 3F (FFF) Configuration Word 5 bits
NNN Highest normal EPROM memory address. NNN = 0x3FF for PIC16C505. Note that some versions will have an oscillator calibration value programmed at NNN TTT Start address of special EPROM area and ID locations.
2.3
Special Memory Locations
EXAMPLE 2-1:
CUSTOMER CODE 0xD1E2
The highest address of program memory space is reserved for the internal RC oscillator calibration value. This location should not be overwritten except when this location is blank, and it should be verified, when programmed, that it is a MOVLW XX instruction. The ID Locations area is only enabled if the device is in programming/verify mode. Thus, in normal operation mode only the memory location 0x000 to 0xNNN will be accessed and the Program Counter will just roll over from address 0xNNN to 0x000 when incremented. The configuration word can only be accessed immediately after MCLR going from VIL to VHH. The Program Counter will be set to all '1's upon MCLR = VIL. Thus, it has the value "0xFFF" when accessing the configuration EPROM. Incrementing the Program Counter once causes the Program Counter to roll over to all '0's. Incrementing the Program Counter 4K times after reset (MCLR = VIL) does not allow access to the configuration EPROM. 2.3.1 CUSTOMER ID CODE LOCATIONS
The Customer ID code "0xD1E2" should be stored in the ID locations 400-403 like this:
400: 401: 402: 403: 0000 0000 0000 0000 0000 0000 0000 0000 1101 0001 1110 0010
Reading these four memory locations, even with the code protection bit programmed would still output on Port A the bit sequence "1101", "0001", "1110", "0010" which is "0xD1E2". Note: All other locations in PICmicroTM configuration memory are reserved and should not be programmed.
Per definition, the first four words (address TTT to TTT + 3) are reserved for customer use. It is recommended that the customer use only the four lower order bits (bits 0 through 3) of each word and filling the eight higher order bits with '0's. A user may want to store an identification code (ID) in the ID locations and still be able to read this code after the code protection bit was programmed.
DS30603A-page 4
(c) 1998 Microchip Technology Inc.
PIC16C50X
2.4 Program/Verify Mode
2.4.1 PROGRAM/VERIFY OPERATION The program/verify mode is entered by holding pins RB1 and RB0 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB0 and RB1 are Schmitt Trigger inputs in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note: The MCLR pin should be raised from VIL to VIHH within 9 ms of VDD rise. This is to ensure that the device does not have the PC incremented while in valid operation range. The RB1 pin is used as a clock input pin, and the RB0 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB1) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB0 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin RB0 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1s is required between a command and a data word (or another command). The commands in Table 2-1. that are available are listed
TABLE 2-1:
COMMAND MAPPING
Command Load Data Read Data Increment Address Begin programming End Programming
0 0 0 0 0
Mapping (MSB ... LSB)
0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 0 0 0
Data 0, data(14), 0 0, data(14), 0
Note:
The clock must be disabled during in-circuit programming.
(c) 1998 Microchip Technology Inc.
DS30603A-page 5
PIC16C50X
2.4.1.1 LOAD DATA
2.5
After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. Because this is a 12 bit core, the two msb's of the data word are ignored. A timing diagram for the load data command is shown in Figure 5-1. 2.4.1.2 READ DATA
Programming Algorithm Requires Variable VDD
The PIC16C50X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC16C50X at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC16C50X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer.
After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RB0 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.4.1.3 INCREMENT ADDRESS
The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.4.1.4 BEGIN PROGRAMMING
A load data command must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.4.1.5 END PROGRAMMING
After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time.
DS30603A-page 6
(c) 1998 Microchip Technology Inc.
PIC16C50X
3.0 CONFIGURATION WORD
The PIC16C50X family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits.
FIGURE 3-1:
Bit Number: 11 10 9
CONFIGURATION WORD BIT MAP
8 7 6 5 4 3 2 1 0 FOSC0 Register: Address CONFIG 0FFFh
CP CP CP CP CP CP MCLRE CP WDTE FOSC2 FOSC1 bit 11-6, 4: CP Code Protection bits (1) (2) bit 5: MCLRE: RB3/MCLR pin function select
1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to Vdd bit 3: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0: FOSC2:FOSC0: Oscillator Selection bits 111 = external RC oscillator / CLKOUT function on RB4/OSC2/CLKOUT pin 110 = external RC oscillator / RB4 function on RB4/OSC2/CLKOUT pin 101 = internal RC oscillator / CLKOUT function on RB4/OSC2/CLKOUT pin 100 = internal RC oscillator / RB4 function on RB4/OSC2/CLKOUT pin 011 = invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Note 1: All of the CP pins have to be given the same value to enable the code protection scheme listed. 2: 03FFh is always uncode protected on the PIC16C505. This location contains the MOVLW xx calibration instruction for the INTRC.
(c) 1998 Microchip Technology Inc.
DS30603A-page 7
PIC16C50X
4.0 CODE PROTECTION
The program code written into the EPROM can be protected by writing to the CP bit of the configuration word. In PIC16C50X, it is still possible to program and read locations 0x000 through 0x03F, after code protection. Once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID locations and configuration word, read normally. These locations can be programmed. Once code protection is enabled, all code protected locations (0x040 to 0x3FE) read 0's. All unprotected segments, including the internal oscillator calibration value (0x3FF location), ID, config word read as normal.
4.1
Embedding Configuration Word and ID Information in the Hex File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 4-1:
PIC16C505 To code protect:
CODE PROTECTION
(CP enable pattern: 000000X0XXXX) Program Memory Segment Configuration Word (0xFFF) [0x00:0x3F] [0x40:0x3FE] 0x3FF ID Locations (0x400 : 0x403) R/W in Protected Mode Read enabled, Write Enabled Read enabled, Write Enabled Read disabled (all 0's), Write Disabled Read enabled, Write Enabled Read enabled, Write Enabled R/W in Unprotected Mode Read enabled, Write Enabled Read enabled, Write Enabled Read enabled, Write Enabled Read enabled, Write Enabled Read enabled, Write Enabled
DS30603A-page 8
(c) 1998 Microchip Technology Inc.
PIC16C50X
4.2
4.2.1
Checksum
CHECKSUM CALCULATIONS
Checksum is calculated by reading the contents of the PIC16C50X memory locations and adding up the opcodes up to the maximum user addressable location, (not including the last location which is reserved for the oscillator calibration value) e.g., 0x3FE for the PIC16C505. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16C50X family is shown in Table 4-2. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum.
The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. At the oscillator calibration value location is not used in the above checksums.
TABLE 4-2:
Device PIC16C505
CHECKSUM COMPUTATION
Code Protect OFF ON Checksum* SUM[0x000:0x3FE] + CFGW & 0xFFF SUM[0x000:0x03F] + CFGW & 0xFFF + SUM(IDS) Blank Value FC00 FBEF 0x723 at 0 and max address EA48 E15B
Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND
(c) 1998 Microchip Technology Inc.
DS30603A-page 9
PIC16C50X
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE TABLE 5-1:
Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic General PD1 PD2 PD3 PD4 PD5 PD6 PD9 PD8 VDDP Supply voltage during programming IDDP Supply current (from VDD) during programming VDDmin 12.75 VDD + 4.0 4.75 5.0 5.25 20 VDDmax 13.25 13.5 50 0.8 VDD 0.2 VDD mA V V Schmitt Trigger input Schmitt Trigger input V mA V V Note 1 Note 2 Min. Typ. Max. Units Conditions
VDDV Supply voltage during verify VIHH1 Voltage on MCLR/VPP during programming VIHH2 Voltage on MCLR/VPP during verify IPP VIH1 VIL1 Programming supply current (from VPP) (RB1, RB0) input high level (RB1, RB0) input low level
Serial Program Verify P1 P2 P3 P4 P5 TR Tf MCLR/VPP rise time (VSS to VHH) MCLR Fall time 100 100 1.0 8.0 8.0 s s ns ns s
Tset1 Data in setup time before clock Thld1 Data in hold time after clock Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) Tdly2 Delay between clock to clock of next command or data Tdly3 Clock to date out valid (during read data) Thld0 Hold time after MCLR
P6 P7 P8
1.0 200 2
s ns s
Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
DS30603A-page 10
(c) 1998 Microchip Technology Inc.
PIC16C50X
FIGURE 5-1:
VIHH MCLR/VPP P8 RB1 (CLOCK) RB0 (DATA) 0 P3 P4 100ns min. Reset 1 100ns 0 0 1 100ns 2 3 4 5 6 P6 1ms min. 1 2 3 4 5 15
LOAD DATA COMMAND (PROGRAM/VERIFY)
0
0 P5 1ms min.
0 P3 P4
0
} }
} }
Program/Verify Mode
100ns min.
FIGURE 5-2:
VIHH MCLR/VPP
READ DATA COMMAND (PROGRAM/VERIFY)
100ns P8 1 2 3 4 5 6 P6 1ms min. 1 2 3 4 5 15
RB1 (CLOCK) RB0 (DATA) 0 P3 0 P4
100ns 1
0
0
0 P5 1ms min.
P7
} }
100ns min. RB0 = output RB0 input
Reset
Program/Verify Mode
FIGURE 5-3:
MCLR/VPP
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH P6 1 2 3 4 5 6 1ms min. 1 Next Command 2
RB1 (CLOCK) RB0 (DATA)
0
1
1
0
0
0 P5
0
0
P3 P4
1ms min.
Program/Verify Mode
Reset
} }
100ns min
(c) 1998 Microchip Technology Inc.
DS30603A-page 11
M
WORLDWIDE SALES AND SERVICE
AMERICAS
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Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 6/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30603A-page 12
(c) 1998 Microchip Technology Inc.

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