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PIC16C55X
EPROM Memory Programming Specification
This document includes the programming specifications for the following devices:
* PIC16C554 * PIC16C556 * PIC16C558
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C55X
1.0
PROGRAMMING THE PIC16C55X
The PIC16C55X can be programmed using a serial method. In serial mode the PIC16C55X can be programmed while in the users system. This allows for increased design flexibility.
SSOP
RA2 RA3 RA4/T0CKI MCLR VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
1.1
Hardware Requirements
PIC16C55X
The PIC16C55X requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V.
1.2
Programming Mode
The programming mode for the PIC16C55X allows programming of user program memory, special locations used for ID, and the configuration word for the PIC16C55X.
Note:
Peripheral pinout functions are not shown (see data sheets for full pinout information).
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16C554/556/558
During Programming Pin Name RB6 RB7 MCLR/VPP VDD VSS Pin Name CLOCK DATA VPP VDD VSS Pin Type I I/O P P P Pin Description Clock input Data input/output Programming Power Power Supply Ground
Legend: I = Input, O = Output, P = Power
(c) 1998 Microchip Technology Inc.
DS30261B-page 1
PIC16C55X
2.0
2.1
PROGRAM MODE ENTRY
User Program Memory Map
The user memory space extends from 0x0000 to 0x1FFF (8K). Table 2-1 shows actual implementation of program memory in the PIC16C55X family.
In the configuration memory space, 0x2000-0x20FF are utilized. When in a configuration memory, as in the user memory, the 0x2000-0x2XFF segment is repeatedly accessed as the PC exceeds 0x2XFF (see Figure 2-1). A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in a scrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb" where 'bbbb' is ID information. Note: All other locations are reserved and should not be programmed.
TABLE 2-1:
IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC16C55X
Program Memory Size 0x000 - 0x1FF (0.5K) 0x000 - 0x3FF (1K) 0x000 - 0x7FF (2K) Access to Program Memory PC<8:0> PC<9:0> PC<10:0>
Device PIC16C554 PIC16C556 PIC16C558
In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 4.1.
When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (see Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2.
DS30261B-page 2
(c) 1998 Microchip Technology Inc.
EPROM Memory Programming Specification
FIGURE 2-1: PROGRAM MEMORY MAPPING
0.5KW 1KW Implemented 2KW Implemented Implemented
0 2000 2001 2002 2003 2004 2005 2006
ID Location ID Location ID Location ID Location Reserved Reserved Reserved Reserved
1FF 3FF 400 7FF 800 BFF C00 FFF 1000
Implemented
Reserved Reserved Reserved Reserved
2007 Configuration Word 1FFF 2000 2008 2100
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3FFF
(c) 1998 Microchip Technology Inc.
DS30261B-page 3
PIC16C55X
2.2 Program/Verify Mode
The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note: The MCLR pin should be raised as quickly as possible from VIL to VIHH. this is to ensure that the device does not have the PC incremented while in valid operation range. PROGRAM/VERIFY OPERATION and load) are specified to have a minimum delay of 1s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1s is required between a command and a data word (or another command). The commands in Table 2-2. 2.2.1.1 that are available are listed
LOAD CONFIGURATION
2.2.1
The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read
After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL).
TABLE 2-2:
COMMAND MAPPING
Command Mapping (MSB ... LSB)
0 1 0 1 0 1 0 0 0 0 0 0
Data 0, data(14), 0 0, data(14), 0 0, data(14), 0
0 0 0 0 Load Configuration 0 0 0 0 Load Data 0 0 0 1 Read Data 0 0 0 1 Increment Address 0 0 1 0 Begin programming 0 0 1 1 End Programming Note: The CPU clock must be disabled during in-circuit programming.
DS30261B-page 4
(c) 1998 Microchip Technology Inc.
EPROM Memory Programming Specification
FIGURE 2-2: PROGRAM FLOW CHART - PIC16C55X PROGRAM MEMORY
Start
Set VDD = VDDP*
N=0 No Program Cycle N > 25 Yes Report Programming Failure
Read Data Command
N=N+1 N=# of Program Cycles No
Increment Address Command
Data Correct? Yes Apply 3N Additional Program Cycles
Program Cycle No Load Data Command
All Locations Done? Yes Verify all Locations @ VDD min.* VPP = VIHH2
Begin Programming Command
Wait 100 s Data Correct? Yes Verify all Locations @ VDD max. VPP = VIHH2 No Report Verify @ VDD min. Error End Programming Command
Data Correct? Yes Done
No
Report Verify @ VDD max. Error
* VDDP = VDD range for programming (typically 4.75V - 5.25V). VDDmin = Minimum VDD for device operation. VDDmax = Maximum VDD for device operation.
(c) 1998 Microchip Technology Inc.
DS30261B-page 5
PIC16C55X
FIGURE 2-3: PROGRAM FLOW CHART - PIC16C55X CONFIGURATION WORD & ID LOCATIONS
Start
Load Configuration Command
N=0
No
Program ID Loc?
Yes Program Cycle
Read Data Command
Increment Address Command
N=N+1 N=# of Program Cycles
No Data Correct? Yes
No
Address = 2004 Yes
No
N > 25 Yes
Increment Address Command
ID/Configuration Error
Apply 3N Program Cycles
Increment Address Command
Increment Address Command
Program Cycle 100 Cycles
Read Data Command
No
Data Correct? Yes
Report Program ID/Config. Error No Done Yes Data Correct?
No
Data Correct? Yes Set VDD = VDDmax VDDmax Read Data Command Set VPP = VIHH2
Set VDD = VDDmin VDDmin Read Data Command Set VPP = VIHH2
DS30261B-page 6
(c) 1998 Microchip Technology Inc.
EPROM Memory Programming Specification
2.2.1.2 LOAD DATA
2.3
After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.2.1.3 READ DATA
Programming Algorithm Requires Variable VDD
The PIC16C55X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDD max.= maximum operating VDD spec for the part. Programmers must verify the PIC16C55X at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC16C55X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer.
After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.2.1.4 INCREMENT ADDRESS
The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.2.1.5 BEGIN PROGRAMMING
A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.2.1.6 END PROGRAMMING
After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time.
(c) 1998 Microchip Technology Inc.
DS30261B-page 7
PIC16C55X
3.0 CONFIGURATION WORD
The PIC16C55X family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits.
FIGURE 3-1:
Bit Number:
CONFIGURATION WORD BIT MAP
13
CP1
12
CP0
11
CP1
10
CP0
9
CP1
8
CP0
7
--
6
0
5
CP1
4
CP0
3
PWRTE
2
WDTE
1
FOSC1
0
FOSC0
PIC16C554/556/558
bit 7: Reserved for future use bit 6: Set to 0 bit 5-4: CP1:CP0, Code Protect bit 8-13
Device PIC16C554 CP1 CP0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Code Protection All memory protected Do not use Do not use Code protection off All memory protected Upper 1/2 memory protected Do not use Code protection off All memory protected Upper 3/4 memory protected Upper 1/2 memory protected Code protection off
PIC16C556
PIC16C558
bit 3: PWRTE, Power Up Timer Enable Bit PIC16C554/556/558: 0 = Power up timer enabled 1 = Power up timer disabled bit 2: WDTE, WDT Enable Bit 1 = WDT enabled 0 = WDT disabled bit 1-0:FOSC<1:0>, Oscillator Selection Bit 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator
DS30261B-page 8
(c) 1998 Microchip Technology Inc.
EPROM Memory Programming Specification
4.0 CODE PROTECTION
4.1
The program code written into the EPROM can be protected by writing to the CP0 & CP1 bits of the configuration word.
Programming Locations 0x0000 to 0x03F after Code Protection
For PIC16C55X devices, once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID locations and configuration word, read normally. These locations can be programmed.
4.2
Embedding Configuration Word and ID Information in the Hex File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 4-1:
PIC16C554
CONFIGURATION WORD
To code protect: * Protect all memory * No code protection
0000001000XXXX 1111111011XXXX R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003) PIC16C556
To code protect: * Protect all memory 0000001000XXXX * Protect upper 1/2 memory 0101011001XXXX * No code protection 1111111011XXXX Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003) PIC16C558 To code protect: * Protect all memory * Protect upper 3/4 memory * Protect upper 1/2 memory * No code protection 0000001000XXXX 0101011001XXXX 1010101010XXXX 1111111011XXXX R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003)
(c) 1998 Microchip Technology Inc.
DS30261B-page 9
PIC16C55X
4.3
4.3.1
Checksum
CHECKSUM CALCULATIONS
Checksum is calculated by reading the contents of the PIC16C55X memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16C74. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16C55X devices is shown in Table 4-2. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum.
The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums.
TABLE 4-2:
CHECKSUM COMPUTATION
0x25E6 at 0 and max address
094D 099C 074D 0093 079C 034D 0FA3 FC93 039C
Device
Code Protect
OFF ALL OFF 1/2 ALL OFF 1/2 3/4 ALL
Checksum*
Blank Value
3D7F 3DCE 3B7F 4EDE 3BCE 377F 5DEE 4ADE 37CE
PIC16C554
SUM[0x000:0x1FF] + CFGW & 0x3F7F SUM_ID + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID
PIC16C556
PIC16C558
Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND
DS30261B-page 10
(c) 1998 Microchip Technology Inc.
EPROM Memory Programming Specification
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE TABLE 5-1:
Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (25C is recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. General PD1 PD2 PD3 PD4 PD5 PD6 PD9 PD8 VDDP Supply voltage during programming IDDP Supply current (from VDD) during programming VDDmin 12.75 VDD + 4.0 4.75 5.0 5.25 20 VDDmax 13.25 13.5 50 0.8 VDD 0.2 VDD mA V V Schmitt Trigger input Schmitt Trigger input V mA V V Note 1 Note 2 Sym. Characteristic Min. Typ. Max. Units Conditions
VDDV Supply voltage during verify VIHH1 Voltage on MCLR/VPP during programming VIHH2 Voltage on MCLR/VPP during verify IPP VIH1 VIL1 Programming supply current (from VPP) (RB6, RB7) input high level (RB6, RB7) input low level
Serial Program Verify P1 P2 P3 P4 P5 TR Tf MCLR/VPP rise time (VSS to VHH) for test mode entry MCLR Fall time 100 100 1.0 8.0 8.0 s s ns ns s
Tset1 Data in setup time before clock Thld1 Data in hold time after clock Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) Tdly2 Delay between clock to clock of next command or data Tdly3 Clock to date out valid (during read data) Thld0 Hold time after MCLR
P6 P7 P8
1.0 200 2
s ns s
Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
(c) 1998 Microchip Technology Inc.
DS30261B-page 11
PIC16C55X
FIGURE 5-1:
VIHH MCLR/VPP P8 RB6 (CLOCK) RB7 (DATA) 0 P3 P4 100ns min. Reset 1 100ns 0 0 1 100ns 2 3 4 5 6 P6 1s min. 1 2 3 4 5 15
LOAD DATA COMMAND (PROGRAM/VERIFY)
0
0 P5 1s min.
0 P3 P4
0
} }
} }
Program/Verify Test Mode
100ns min.
FIGURE 5-2:
VIHH MCLR/VPP
READ DATA COMMAND (PROGRAM/VERIFY)
100ns P8 1 2 3 4 5 6 P6 1s min. 1 2 3 4 5 15
RB6 (CLOCK) RB7 (DATA) 0 P3 0 P4 100ns 1 0
0
0 P5 1s min.
P7
} }
100ns min. RB7 = output RB7 input
Reset
Program/Verify Test Mode
FIGURE 5-3:
MCLR/VPP
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH P6 1s min. Next Command 1 2
1 RB6 (CLOCK) RB7 (DATA)
2
3
4
5
6
0
1
1
0
0
0 P5
0
0
P3 P4
1s min.
Program/Verify Test Mode
Reset
} }
100ns min
DS30261B-page 12
(c) 1998 Microchip Technology Inc.
EPROM Memory Programming Specification
NOTES:
(c) 1998 Microchip Technology Inc.
DS30261B-page 13
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Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 3/98
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DS30261B-page 14
(c) 1998 Microchip Technology Inc.

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