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2N6782 Data Sheet December 2001 3.5A, 100V, 0.600 Ohm, N-Channel Power MOSFET [ /Title (2N67 82) /Subject (3.5A, 100V, 0.600 Ohm, NChannel Power MOSFET) /Autho r () /Keywords (Fairchild Corporation, NChannel Power MOSFET, TO205AF ) /Creator () /DOCI NFO pdfmark The 2N6782 is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Features * 3.5A, 100V * rDS(ON) = 0.600 * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Majority Carrier Device Ordering Information PART NUMBER 2N6782 PACKAGE TO-205AF BRAND 2N6782 * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" NOTE: When ordering, use the entire part number. Symbol D G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE (c)2001 Fairchild Semiconductor Corporation 2N6782 Rev. B 2N6782 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified 2N6782 100 100 3.5 2.25 14 20 3.5 14 15 0.12 -55 to 150 300 260 UNITS V V A A A V A A W W/oC oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed Drain Current (Notes 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulse Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS VDS(ON) IGSS rDS(ON) VSD gfs td(ON) tr td(OFF) tf CISS COSS CRSS RJC RJA SOA Free Air Operation VDS = 80V, ID = 188mA VDS = 4.28V, ID = 3.5A VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) TEST CONDITIONS ID = 0.25mA, VGS = 0V VGS = VDS, ID = 0.5mA VDS = 100V, VGS = 0V VDS = 80V, VGS = 0V TC = 125oC ID = 3.5A, VGS = 10V VGS = 20V ID = 2.25A, VGS = 10V ID = 2.25A, VGS = 10V, TC = 125oC TC = 25oC, IS = 3.5A, VGS = 0V VDS = 5V, ID = 2.25A VDD 34V, ID = 2.25A, RG = 50 (Figure 17) MOSFET Switching Times are Essentially Independent of Operating Temperature MIN 100 2 0.75 1 60 40 10 15 15 TYP 0.5 1.5 135 80 20 MAX 4 250 1000 2.1 100 0.600 1.080 1.5 3 15 25 25 20 200 100 25 8.33 175 UNITS V V A A V nA V S ns ns ns ns pF pF pF oC/W oC/W Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Diode Forward Voltage (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Safe Operating Area W W Source to Drain Diode Specifications PARAMETER Reverse Recovery Time Reverse Recovered Charge NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL trr QRR TEST CONDITIONS TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/s TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/s MIN TYP 200 1.0 MAX UNITS ns C (c)2001 Fairchild Semiconductor Corporation 2N6782 Rev. B 2N6782 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A) Unless Otherwise Specified 5 4 3 0.6 0.4 2 0.2 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 1 0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 THERMAL IMPEDANCE ZJC, NORMALIZED 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 1 10 PDM FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 12 10 80s PULSE TEST 10V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10 10s 100s 1ms 8 6 4 2 0 9V VGS = 8V 1 TC = 25oC TJ = MAX RATED RJC = 8.33oC/W SINGLE PULSE 10ms 100ms DC 1000 7V 6V 5V 4V 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) 60 -0.1 -1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS (c)2001 Fairchild Semiconductor Corporation 2N6782 Rev. B 2N6782 Typical Performance Curves 10 Unless Otherwise Specified (Continued) 80s PULSE TEST VGS = 10V 9.0V ID, DRAIN CURRENT (A) 10 80s PULSE TEST ID, DRAIN CURRENT (A) 8 6 8.0V 7.0V TJ = 125oC TJ = 25oC 1.0 TJ = -55oC 4 6.0V 2 5.0V 4.0V 0 0 1 3 4 5 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 6 7 0.1 0 2 4 6 8 10 12 VGS, SOURCE TO DRAIN VOLTAGE (V) 14 FIGURE 6. SATURATION CHARACTERISTICS 2.0 rDS(ON), ON-STATE RESISTANCE () NORMALIZED ON-RESISTANCE 2.00 1.75 1.50 1.25 1.00 0.75 0.50 FIGURE 7. TRANSFER CHARACTERISTICS VGS = 10V ID = 1.5A 1.5 VGS = 10V 1.0 VGS = 20V 0.5 0 0 5 10 ID, DRAIN CURRENT (A) 15 20 0.25 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.15 NORMALIZED ON-RESISTANCE 1.10 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 400 1.05 1.00 0.95 0.90 0.85 0.80 -80 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 10 30 C, CAPACITANCE (pF) 300 200 CISS 100 COSS CRSS 0 20 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE (c)2001 Fairchild Semiconductor Corporation 2N6782 Rev. B 2N6782 Typical Performance Curves 2.5 gfs, TRANSCONDUCTANCE (S) Unless Otherwise Specified (Continued) IDR, REVERSE DRAIN CURRENT (A) 80s PULSE TEST TJ = -55oC TJ = 25oC 10 5 2 1.0 0.5 80ms PULSE TEST 2.0 TJ = 150oC TJ = 25oC 1.5 TJ = 125oC 1.0 0.5 0.2 0.1 0 0 2 4 6 8 10 ID, DRAIN CURRENT (A) 12 14 0 0.4 0.8 1.2 1.6 2.0 2.2 VSD, SOURCE TO DRAIN VOLTAGE (V) 2.4 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE VOLTAGE (V) ID = 8A VDS = 20V VDS = 50V VDS = 80V 15 10 5 0 0 2 4 6 8 Qg , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE (c)2001 Fairchild Semiconductor Corporation 2N6782 Rev. B 2N6782 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS 90% tOFF td(OFF) tf 90% + RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2F 50k 0.3F G DUT 0 IG(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS (c)2001 Fairchild Semiconductor Corporation 2N6782 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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