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1 Megabit (128K x 8) SuperFlash MTP
SST27SF010
Preliminary Specifications
FEATURES: * 5.0-Volt Read Operation (4.5V to 5.5V) * Superior Reliability - Endurance: Minimum 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) - Standby Current: 10 A (typical) * Fast Access Time - 70 and 90 ns * Fast Programming Operation - 20 s per byte - 2.8 second for the entire chip
* Features Electrical Erase - Does Not Require UV Source - Chip Erase Time: 100 ms * TTL I/O Compatibility * JEDEC Standard Byte-wide EPROM Pinouts * 12V Power Supply for Programming/Erase * Packages Available - 32-Pin PLCC - 32-Pin Plastic DIP - 32-Pin TSOP (8mm x 14mm)
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PRODUCT DESCRIPTION The SST27SF010 is a 128K x 8 CMOS, many-time programmable (MTP) low cost flash, manufactured with SST's proprietary, high performance SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST27SF010 can be electrically erased and programmed at least 1000 times using an external programmer with a 12 volt supply. The SST27SF010 has to be erased prior to programming. The SST27SF010 conforms to JEDEC standard pinouts for byte-wide memories. Featuring high performance byte programming, the SST27SF010 provides a byte-program time of 20 s. The entire memory can be programmed byte by byte in 2.8 seconds. Designed, manufactured, and tested for a wide spectrum of applications, the SST27SF010 is offered with a minimum endurance of 1000 cycles. Data retention is rated at greater than 100 years. The SST27SF010 is suited for applications that require infrequent writes and low power nonvolatile storage. The SST27SF010 will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27SF010 is offered in 32-pin PLCC, 32-pin PDIP and 32-pin TSOP packages. See Figures 1 and 2 for pinouts.
Device Operation The SST27SF010 is a low cost flash solutions that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. They are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, the device also supports electrical erase operation via an external programmer. The SST27SF010 does not require a UV source to erase, and therefore the packages do not have a window. Read The Read operation of the SST27SF010 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 10 A is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Programming operation The SST27SF010 is programmed by using an external programmer. The programming mode is activated by asserting 12V (5%) on VPP pin, Vcc = 5V5%, VIL on CE# pin, and VIH on OE# pin. The device is programmed byte by byte with the desired data at the desired address using a single pulse (PGM# pin low) of 20 s. Using the
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(c) 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon storage Technology, Inc. 1 315-06 8/98 These specifications are subject to change without notice.
1 Megabit SuperFlash MTP SST27SF010
Preliminary Specifications MTP programming algorithm, the byte programming process continues byte by byte until the entire chip (128K bytes) has been programmed. Chip Erase Operation The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". Unlike traditional EPROMs, which use UV light to do the chip erase, the SST27SF010 uses an electrical chip erase operation. This saves a significant amount of time (about 30 minutes for each erase operation). The entire chip can be erased in a single pulse of 100 ms (PGM# pin low). In order to activate the erase mode, the 12V (5%) is applied to VPP and A9 pins, Vcc = 5V5%, VIL on CE# pin, and VIH on OE# pin. All other address and data pins are "don't care". The falling edge of PGM# will start the Chip Erase operation. Once the chip has been erased, all bytes must be verified for FF. Refer to figure 8 for the flow chart. The SST27SF010 can also be reprogrammed in the system. This requires the availability of 12V for VPP to program and an additional 12V for address A9 to erase. Product Identification Mode The product identification mode identifies the device as the SST27SF010 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force VH (12V5%) on address A9 with VPP pin at 5V10%. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation.
TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 H Device Code 0001 H
Data BF H A5 H
315 PGM T1.0
FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF010 1,048,576 Bit EEPROM Cell Array
X-Decoder
A16 - A0
Address Buffer Y-Decoder
CE# OE# A9 VPP PGM#
I/O Buffers Control Logic DQ7 - DQ0
315 ILL B1.0
(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications
A11 A9 A8 A13 A14 NC PGM# VCC VPP A16 A15 A12 A7 A6 A5 A4 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
315 ILL F01.0
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Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
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PGM#
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
VCC
VPP
A12
A15
A16
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC PGM# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
NC
6
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
7 8 9 10
315 ILL F02.0
32-Lead PLCC Top View
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FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS TABLE 2: PIN DESCRIPTION Symbol Pin Name A16-A0 Address Inputs DQ7-DQ0 Data Input/Output CE# OE# PGM# VPP VCC VSS NC Chip Enable Output Enable Program/Erase Pin Power Supply for Program or Erase Power Supply Ground No Connection
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315 PGM T2.1
Functions To provide memory addresses To output data during read cycles and receive input data during program cycle, the outputs are in tri-state when OE# or CE# is high To activate the device when CE# is low To gate the data output buffers during read operation Used for program or erase (PGM# = VIL pulse during program or erase) High voltage pin during chip erase and programming operation 12-volt (5%) To provide 5-volt supply (10%) Unconnected pins
(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications TABLE 3: OPERATION MODES SELECTION Mode CE# OE# PGM# Read VIL VIL X Output Disable Program Standby Chip Erase Program/Erase Inhibit Product Identification
Note:
A9 AIN X AIN X VH X VH
VIL VIL VIH VIL VIH VIL
VIH VIH X VIH X VIL
X VIL X VIL X X
VPP VCC or VSS VCC or VSS VPPH VCC or VSS VPPH VPPH VCC or VSS
DQ DOUT High Z DIN High Z High Z High Z Manufacturer Code (BF) Device Code A5
Address AIN AIN AIN X X X A16-A1 = VIL, A0 = VIL A16-A1 = VIL, A0 = VIH
315 PGM T3.1
X = VIL or VIH VPPH = 12V5%, VH = 12V5%
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V Voltage on A9 and VPP Pin to Ground Potential .................................................................................. -0.5V to 14.0V Package Power Dissipation Capability (TA = 25C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ............................................................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C
AC CONDITIONS OF TEST VCC 5V10% 5V10% Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF See Figures 6 and 7
(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications TABLE 4: READ MODE DC OPERATING CHARACTERISTICS Vcc = 5 V10%, TA = 0C to 70C (Commercial) or -40C to +85C (Industrial) Limits Symbol Parameter Min Max Units Test Conditions ICC VCC Read Current 30 mA CE# = OE# = VIL all I/Os open, Address Input = VIL/VIH at f = 1/TRC Min, VCC = VCC Max IPPR VPP Read Current 100 A CE# = OE# = VIL, all I/Os open, Address Input = VIL/VIH at f = 1/TRC Min, VCC = VCC Max, VPP = Vcc ISB1 Standby VCC Current 3 mA CE# = OE# = VIH, VCC = VCC Max (TTL input) ISB2 Standby VCC Current 50 A CE#=OE#=VCC -0.3V (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 A VIN = GND to VCC, VCC = VCC Max ILO Output Leakage Current 10 A VOUT = GND to VCC, VCC = VCC Max VIL Input Low Voltage 0.8 V VCC = VCC Max VIH Input High Voltage 2.0 Vcc+0.5 V VCC = VCC Max VOL Output Low Voltage 0.4 V IOL = 2.1 mA, VCC = VCC Min VOH Output High Voltage 2.4 V IOH = -400A, VCC = VCC Min IH Supervoltage Current 100 A CE# = OE# = VIL, A9 = VH Max. for A9
315 PGM T4.2
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(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS Vcc = 5 V10%, VPP = VPPH,TA = 25C5C Limits Symbol Parameter Min Max Units ICP VCC Erase or Program 30 mA Current IPP VPP Erase or Program 1 mA Current ILI Input Leakage Current 1 A ILO Output Leakage Current 10 A VH Supervoltage for A9 11.4 12.6 V IH Supervoltage Current 100 A for A9 VPPH High Voltage for VPP Pin 11.4 12.6 V
Test Conditions CE# = VIL, VPP = 12V5%, VCC = VCC Max CE# = VIL, VPP = 12V5%, VCC = VCC Max VIN = GND to VCC, VCC = VCC Max VOUT = GND to VCC, VCC = VCC Max CE# = OE# = VIL CE# = OE# = VIL, A9 = VH Max
315 PGM T5.0
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up to Read Operation
Maximum 100
Units s
315 PGM T6.1
TABLE 7: CAPACITANCE (TA = 25 C, f=1 MHz, other pins open) Parameter Description Test Condition (1) CI/O I/O Pin Capacitance VI/O = 0V CIN(1) Input Capacitance VIN = 0V
Maximum 12 pF 6 pF
315 PGM T7.0
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention (1) VZAP_HBM ESD Susceptibility Human Body Model (1) VZAP_MM ESD Susceptibility Machine Model (1) ILTH Latch Up
Note:
(1)
Minimum Specification 1000 100 1000 300 100
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
315 PGM T8.1
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change SST27SF010-70 Min Max 70 70 70 30 0 0 25 25 0 SST27SF010-90 Min Max 90 90 90 40 0 0 30 30 0 Units ns ns ns ns ns ns ns ns ns
315 PGM T9.0
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TABLE 10: PROGRAMMING/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min TCES CE# Setup Time 2 TCEH CE# Hold Time 2 TAS Address Setup Time 2 TAH Address Hold Time 2 TPRT VPP Pulse Rise Time 50 TVPS VPP Setup Time 2 TVPH VPP Hold Time 2 TPW PGM# Program Pulse Width 20 TEW PGM# Erase Pulse Width 100 TDS Data Setup Time 2 TDH Data Hold Time 2 TVR A9 Recovery Time for Erase 2 TART A9 Rise Time to 12V during Erase 50 TA9S A9 Setup Time during Erase 2 TA9H A9 Hold Time during Erase 2
Max
40 500
Units s s s s ns s s s ms s s s ns s s
315 PGM T10.0
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(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications
TRC TAA
ADDRESS
CE#
TCE
OE#
TOE
TOLZ
TOHZ TOH DATA VALID TCHZ DATA VALID
DQ7-0
HIGH-Z TCLZ VCC
VPP VSS
VIH
PGM#
VIL
315 ILL F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT A9) CE#
TCEH
OE# VIH
DQ7-0 VPPH VCC VSS VPPH A9 VIH VIL TART TA9H PGM# TCES
315 ILL F04.0
TVPS TVPH TPRT TA9S TVR
VPP
TEW
FIGURE 4: ERASE TIMING DIAGRAM
(c) 1998 Silicon Storage Technology, Inc.
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1 Megabit SuperFlash MTP SST27SF010
Preliminary Specifications
ADDRESS
ADDRESS VALID
TAH
1
TAS TCEH
2 3
CE#
OE#
VIH
TDS TDH
4 5
DQ7-0
HIGH-Z VPPH VCC
DATA VALID
TVPS
6
TPRT
VPP PGM#
VSS
TPW TVPH
7
315 ILL F05.0
TCES
8 9 10
FIGURE 5: PROGRAM TIMING DIAGRAM
2.4
INPUT
2.0
REFERENCE POINTS
2.0
OUTPUT
11
315 ILL F06.0
0.4
0.8
0.8
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AC test inputs are driven at VOH (2.4 V) for a logic "1" and VOL (0.4 V) for a logic "0". Measurement reference points for inputs and outputs are VIH (2.0 V) and VIL (0.8 V). Inputs rise and fall times (10% 90%) are <10 ns. FIGURE 6: AC INPUT/OUTPUT REFERENCE WAVEFORMS
(c) 1998 Silicon Storage Technology, Inc.
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1 Megabit SuperFlash MTP SST27SF010
Preliminary Specifications
TEST LOAD EXAMPLE VCC TO TESTER RL HIGH
TO DUT CL RL L OW
315 ILL F07.0
FIGURE 7: TEST LOAD EXAMPLE
(c) 1998 Silicon Storage Technology, Inc.
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1 Megabit SuperFlash MTP SST27SF010
Preliminary Specifications
Start
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A9 = VH, VPP = VPPH
CE# = VIL, OE# = VIH Erase 100ms pulse (PGM# = VIL)
PGM# = VIH
A9 = VIL or VIH
A9 Recovery Time
7
Device into Read mode
8
Compare all bytes to FF Yes No
9 10
Device Passed
Device Failed
11
315 ILL F08.0
12
FIGURE 8: ERASE ALGORITHM
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(c) 1998 Silicon Storage Technology, Inc.
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1 Megabit SuperFlash MTP SST27SF010
Preliminary Specifications
Start
Erase
See Figure 8
VPP = VPPH
Address = First Location
CE# = VIL, OE# = VIH
Program 20s pulse (PGM# = VIL)
Increment Address No
Last Address? Yes
Device into Read mode
Compare all bytes to original data Yes
No
Device Passed
Device Failed
315 ILL F09.0
FIGURE 9: PROGRAMMING ALGORITHM
(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications PRODUCT ORDERING INFORMATION
Device SST27SF010
Speed - XXX -
Suffix1 XX -
Suffix2 XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (8mm x 14mm) U = Unencapsulated die Operating Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 3 = 1000 cycles Read Access Speed 70 = 70 ns, 90 = 90 ns
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Valid combinations SST27SF010- 70-3C-WH SST27SF010- 90-3C-WH SST27SF010- 70-3I-WH SST27SF010- 90-3I-WH
10
SST27SF010- 70-3C-NH SST27SF010- 90-3C-NH SST27SF010- 70-3I-NH SST27SF010- 90-3I-NH SST27SF010- 70-3C-PH SST27SF010- 90-3C-PH
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SST27SF010- 90-3C-U1
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 1998 Silicon Storage Technology, Inc.
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1 Megabit SuperFlash MTP SST27SF010
Preliminary Specifications PACKAGING DIAGRAMS
32pn TSOP WH AC.3
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (.05) mm.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: WH
32pn PDIP PH AC.2 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications
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32pn PLCC NH AC.3 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
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32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
(c) 1998 Silicon Storage Technology, Inc.
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