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SL1925
Satellite Zero IF QPSK Tuner IC
Preliminary Information
DS4955 ISSUE 3.1 October 2001
Features
q q
q q q q q q
q
Single chip system for direct quadrature down conversion from L-band High signal handling capability for minimum external component count application, requires external RF AGC of 30dB Compatible with DSS and DVB system requirements Excellent gain and phase match up to 30MHz baseband High output referred linearity for low distortion and multi channel application Fully balanced low radiation design Integral RF AGC amplifier Two selectable varactor tuned local oscillators with buffered output for driving external synthesiser loop ESD protection (Normal ESD handling procedures should be observed)
Ordering Information SL1925/KG/NP2S (Tubes) SL1925/KG/NP2T (Tape and Reel)
Description
The SL1925 is a wideband quadrature converter operating from 950 to 2150 MHz, intended primarily for application in satellite tuners. The device contains all elements necessary, with the exception of local oscillator sustaining network, to fabricate a high performance I(n-phase) & Q(uadrature) phase splitter and downconverter optimised for systems containing RF AGC gain control. The device allows for systems containing higher power analog interferers. For most applications RF tunable filtering is not essential. The SL1925 is optimised for use with a low phase noise synthesiser, a range of which are available from Zarlink Semiconductor. This will form a complete front end tuner function for digital satellite receiver systems utilising DSP derotation recovery. The device includes a very high signal handling front end with AGC, this provides for gain control, reference local oscillator with output buffer, phase splitter with I and Q mixers and baseband buffer amplifiers with external interstage filtering.
Applications
q q
Satellite receiver systems Data communications systems
SL1925
Preliminary Information
OPFI Vcc PSout PSoutb Vee Tanks Tanksb Vee Tankv Tankvb Vee NC Vcc OPFQ
14
1
28
Vee IPFI Vee Iout LOsel Vcc RF RFB Vee AGC Qout Vee IPFQ Vee
15
NP28
Figure 1 Pin connections
25 AGC 19 AGC SENDER
Iout
27
IPFI
1
OPFI
RF RFB
22 21
0 DEG
14
OPFQ
90 DEG 16 IPFQ
Tankv Tankvb
9 10
vcov
18
Qout
Tanks Tanksb
6 7
vcos DIVIDE BY 2
FREQUENCY AGILE PHASE SPLITTER
3 4
PSout PSoutb Vcc Vee
LOsel
24
2, 13, 23 5, 8, 11, 15, 17, 20, 26, 28
Figure 2 Block diagram
2
Preliminary Information
Quick Reference Data
Characteristic Operating range Input noise figure, DSB, maximum gain, 1500MHz Maximum conversion gain (assuming 6dB filter loss) Minimum conversion gain (assuming 6dB filter loss) IP32T input referred Converter input referred IM3, two tones at 97dBV IP22T input referred P1dB input referred Baseband amplifier Output limit voltage Gain match up to 22 MHz Phase match up to 22 MHz Gain flatness up to 22 MHz Local oscillator phase noise across entire 950MHz to 2150MHz band: SSB @ 10 kHz offset Table 1
SL1925
950-2150 19 >55 <20 113 30 140 103 2.0 0.2 0.7 0.5 -80
Units MHz dB dB dB dBuV dBc dBuV dBuV V dB deg dB dBc/Hz
Functional Description
The SL1925 is a wideband direct conversion quadrature downconverter optimised for application in satellite receiver systems. A block diagram is given in Figure 2 and shows the device to include a broadband RF preamplifier with AGC control, two oscillator sustaining amplifiers, a frequency agile 90 phase splitter, I Q channel mixers and I Q channel baseband amplifiers. The only additional elements required are an external tank circuit for each oscillator, and baseband interstage filters. To fabricate a complete tuner an RF AGC stage offering +20dB to -10 dB of gain range and a 2.2 GHz PLL frequency synthesiser are also required. An example application is shown in Figure 16. In normal application the first satellite IF frequency of typically 950 to 2150 MHz is fed via the tuner RF AGC stage to the RF preamplifier, which is optimised for impedance match and signal handling. The RF preamplifier is designed such that no tracking RF filter is required and also allows for analog interferers at up to 10 dB higher amplitude. The converter RF input impedance is shown in Figure 5. The amplifier signal is then fed to an AGC stage providing a minimum of 35dB AGC control, which together with the RF attenuator provides a possible overall tuner dynamic range of 65dB, to allow for normal operating dynamic range and MCPC systems. The signal is then split into two balanced channels to drive the I and Q mixers. The AGC characteristic, and gain variation of IIP3, IIP2, P1dB and NF are contained in Figs. 6, 7, 8, 9 and 10 respectively.
The required 950MHz to 2150MHz I and Q reference LO frequencies for quadrature direct conversion are generated by the on board oscillators named `vcos' and `vcov', and the phase splitter. Oscillator `vcos' operates nominally from 1900MHz to 3000MHz and is then divided by two to provide 950MHz to 1500MHz. Oscillator `vcov' operates nominally from 1400MHz to 2150MHz. Only one oscillator is active at any time and selection is made within the phase splitter under the control of the LOsel input. Each oscillator uses an external varactor tuned resonant network optimised for low phase noise with a single varactor line control. A recommended application circuit for the oscillators is shown in Figure 4. The LO from the phase splitter drives a buffer whose outputs `PSout' and `PSoutb' can be used for driving an external PLL control loop for the VCO's. The typical LO phase noise is shown in Figure 11. The mixer outputs are coupled to baseband buffer outputs `OPFI' and `OPFQ' which drive external band limit filters. The output impedance of these buffers is contained in Figure 12. The outputs of the filters are then connected to the inputs `IPFI' and `IPFQ' of the baseband channel amplifiers. The outputs `Iout' and `Qout' provide for a low impedance drive and can be used with a maximum load as in Figure 3. The output impedance of this section is contained in Figure 13. An example filter for application with 30MS/s systems is contained in Figure 14. All port peripheral circuitry for the SL1925 is shown in Figure 15a and 15b. The typical key performance data at 5V Vcc and 25C ambient are shown in the `QUICK REFERENCE DATA' of Table 1.
3
SL1925
Preliminary Information
100 1k 15pF
Figure 3 Baseband output load condition
1T379 6.15MM STRIPLINE 1k 1T379 6.15MM STRIPLINE
6
Tanks "vcos"
7
Tanksb
Vcnt BB811 9MM STRIPLINE 9 Tankv "vcov" Tankvb
BB811 1k
9MM STRIPLINE 10
Note: Stripline width =0.44mm,dimensions are approximate.
Figure 4 Local oscillator application circuit
+j1 +j0.5 +j2
Marker
+j0.2 +j5
Freq (MHz) 950 1350 1750 2150
Zreal Zimag 90 76 63 46 -18 -15 -35 -29
1 2
0
0.2
0.5
1 1X X2 X3
2
5 X
3 4
X 4 -j0.2
-j5
-j0.5
-j2 -j1
START 700 MHz Normalised to 50
STOP 2 500 MHz
Figure 5 Converter RF input impedance (typical)
4
Preliminary Information
SL1925
50.0
40.0
Converter conversion gain (dB)
30.0
30dB minimum, AGC <1V
20.0
10.0
0.0
-5dB maximum, AGC >4V
-10.0
-20.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
AGC control voltage (V)
Figure 6 Converter gain variation with AGC voltage (typical)
120
115
Converter input referred IP3 (dBuV)
110
105
100
95
90 -6 -1 4 9 14 Converter gain setting (dB) 19 24 29 34
Figure 7 Converter input referred IP3 variation with gain setting (typical)
5
SL1925
Preliminary Information
140
135
130
Converter input referred IP2 (dBuV)
125
120
115
110
105
100 -6 -1 4 9 14 Converter gain setting (dB) 19 24 29 34
Figure 8 Converter input referred IP2 variation with gain setting (typical)
110
105
Converter RF input level at P1dB (dBuV)
100
95
90
85
80 -6 -1 4 9 14 Converter gain setting (dB) 19 24 29 34
Figure 9 Converter input referred 1dB gain compression, P1dB (typical)
6
Preliminary Information
SL1925
60
50
Noise Figure (dB)
40
30
20
10 20 25 30 35 System gain (dB) 40 45 50 55
Figure 10 Noise figure variation with gain setting (typical)
7
SL1925
Preliminary Information
LO Frequency (MHz) -70 950 -72 1150 1350 1550 1750 1950 2150
vcos enabled
-74
Phase noise @10kHz offset (dBc/Hz)
vcov enabled
-76 -78 -80 -82 -84 -86 -88 -90
Figure 11 LO phase noise variation with frequency (typical)
+j1 +j0.5 +j2
+j0.2
x
2
3
Marker
+j5
Freq (MHz) 1 10 30
Zreal Zimag 24 25 30 0.5 11 29
1
x
1 2 5
0
0.2
0.5
2 3
1x
-j0.2
-j5
-j0.5
-j2 -j1
START 10kHz 700 Normalised to 50
STOP 2 500 50MHz
Figure 12 Converter output impedance, OPFI and OPFQ (typical)
8
Preliminary Information
SL1925
+j1 +j0.5 +j2
Marker
+j0.2 +j5
Freq (MHz) 1 10 30
Zreal Zimag 11.4 9.6 7.3 3.4 0.2 4.7
1 2
0
3X 2X 1X
0.5
1
2
5 X
3
-j0.2
-j5
-j0.5
-j2 -j1
START 10kHz Normalised to 50
STOP 50MHz
Figure 13 Baseband output impedance, Iout and Qout (typical)
100nF OPFI / OPFQ
1k IPFI / IPFQ 1k 3.9pF
Figure 14 Example baseband interstage filter for 30MS/s application
9
SL1925
Preliminary Information
Vcc
IF-OP-SEL LOsel
RF INPUTS
VREF 3
Converter RF inputs (pins 21, 22)
Oscillator select input (pin 24)
VREF 2
1K TANK
1K
TANKB
OPFI & OPFQ
Oscillator inputs (pins 6, 7, and 9,10)
Converter outputs (pins 1, 14)
Vcc
VREF4
PSout LO OUTPUT PSoutb LO OUTPUTB
2K AGC 12K
CONTROL
Prescaler buffer drive (Pins 3,4)
AGC input (pin 19)
Figure15a Input/Output interface circuits
10
Preliminary Information
SL1925
BIAS IPFI and IPFQ
Iout and Qout
Baseband amplifier inputs (pins 16,27)
Baseband outputs (pins 18, 25)
Figure 15b Input/Output interface circuits (continued)
11
SL1925
Electrical Charqacterisitics
Preliminary Information
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Tamb = -20C to + 70C, Vee= 0V, Vcc = 4.75V to 5.25V. Desired channel at fc MHz Value Min
Supply current, Icc RF input operating frequency SYSTEM System noise figure, DSB Variation in system NF with gain adjust System input referred IP2 System input referred IP3 System conversion gain 21,22 21,22 135 110 19 -1 140 113 dB dB/dB dBV dBV 2,13,23 21,22 950
Characteristic
Pin
Typ
130
Max
175 2150
Units
mA MHz
Conditions
All system specification items should be read in conjunction with Note 1. Maximum gain, AGC = 1V See Figure 10 See Note 2. See Note 3. Terminated voltage conversion gain into load as in Figure 3. AGC monotonic from Vee to Vcc, see Figure 6 AGC = 4.0V, 950MHz AGC = 1.0V, 950MHz 950MHz to 2150MHz Excluding interstage filter stage Excluding interstage filter stage Excluding interstage filter stage See Note 5 See Note 6 Within 0 100MHz band, under all gain settings, RF input set to deliver 108dBV at baseband outputs See Figure 5
Minimum AGC gain Maximum AGC gain Gain Roll off System I/Q gain match System I/Q phase balance System I & Q channel in band ripple LO 2nd harmonic interference level LNA 2nd harmonic interference level All other spurii on I & Q outputs
20 59 5 18,25 18,25 18,25 -1 -3 +1 3 1 -50 -35 18,25 78
dB dB dB dB deg dB dBc dBc dBV
CONVERTER Converter input impedance Converter input return loss Converter input referred IP2 Converter input referred IP3 Converter input referred IM2 Converter input referred IM3 Converter input referred 1dB gain compression (P1dB) Converter conversion gain Minimum AGC gain Maximum AGC gain AGC gain control slope variation AGC control input current
21,22 21,22 21,22 21,22 21,22 21,22 21,22 10 121 110
75 12 130 112 -33 -30
dB dBV dBV dBc dBc
-24 -26
See Note 4 See Note 4 See Note 4 See Note 4 See Figure 9 Terminated voltage conversion gain in load as in Figure 3. AGC = 4.0V AGC = 1.0V Monotonic from Vee to Vcc, see Figure 6 AGC bandwidth 100kHz
-5 30 19 -250 250
dB dB A
12
Preliminary Information
Electrical Characteristics (continued)
SL1925
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Tamb = -20C to + 70C, Vee= 0V, Vcc = 4.75V to 5.25V. Desired channel at fc MHz Value Min
Converter output impedance Converter output limiting Converter bandwidth 1dB Converter output roll off Oscillator vcos operating range Tanks/Tanksb Oscillator vcov operating range, Tankv/Tankvb Local oscillator SSB phase noise 1,14 1,14 1,14 6,7 9,10 6,7
Characteristic
Pin
Typ
25 1.2
Max
50
Units
Conditions
0.5 40 6 1900 1450
Vp-p MHz dB/oct MHz MHz dBc/Hz
0.1 to 30MHz. See Figure 12 No Load No Load
3000 2150 -80 -76
Giving LO = 950MHz to1500MHz Application as in Figure 4. Application as in Figure 4. @ 10kHz offset PLL loop BW < 1kHz, application as Figure 4. Measured at baseband outputs of 10MHz Oscillator vcos enabled Oscillator vcov enabled
LO leakage to converter input LOsel low voltage LOsel high voltage LOsel low current LOsel high current Prescaler output drive Prescaler output impedance Prescaler output return loss BASEBAND AMPLIFIERS Baseband amplifier input impedance Resistance Capacitance Baseband amplifier input referred IP3 Baseband amplifier input referred IP2 Baseband amplifier input referred IM3 Baseband amplifier input referred IM2 Baseband amplifier input referred 1dB compression (P1dB) Baseband amplifier gain
21,22 24 24 Vcc-0.7 24 24 3,4 88 3,4 3,4 16,27 10
59
69 0.6 -50 200
dBV V V A A dBV dB
Single ended into 50. Synthesiser should be driven differentially
50 8
0.1 -30MHz bandwidth k pF dBV dBV -34 -22 dBc dBc dBV dB
5 16,27 16,27 16,27 16,27 16,27 16,18 27,25 84 30 94 99 97 111 -40 -34
See Note 7 See Note 7 See Note 7 See Note 7 Terminated voltage gain into load as in Figure 3. Terminated voltage gain into load as in Figure 3
13
SL1925
Electrical Characteristics (continued)
Preliminary Information
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Tamb = -20C to + 70C, Vee= 0V, Vcc = 4.75V to 5.25V. Desired channel at fc MHz Value
Min
Characteristic Baseband amplifier output impedance Baseband amplifier output limiting Baseband amplifier 1dB bandwidth Baseband output roll off
Pin 18,25 18,25 18,25 18,25 2.0 40 6
Typ
Max 20
Units Vp-p MHz dB/oct
Conditions
pk-pk level at hard clipping. Load as in Figure 3. Load as in Figure 3. Above 3dB point, no load
Notes : 1. Systems specifications refer to total cascaded system of front end converter/AGC stage and baseband amplifier stage with nominal 6dB pad as interstage filter and load impedance as in Figure 3. 2. AGC set to deliver output amplitude of 108dBV on desired channel, input frequency fc and amplitude of 79dBV, with two interferers of frequencies fc+146 and fc+155MHz at 97dBV generating output intermodulation spur at 9MHz. 40MHz 3dB bandwidth interstage filter included. 3. AGC set to deliver output amplitude of 108dBV on desired channel, input frequency fc and amplitude 79 dBV, with two interferers of frequencies fc+110 and fc+211MHz at 97 dBV generating output intermodulation spur at 9MHz. 40MHz 3dB bandwidth interstage filter included. 4. Two tones within RF operating frequency range at 97dBV, conversion gain set at 4dB. 5. The level of 2.01GHz downconverted to baseband relative to 1.01 GHz with the oscillator tuned to 1 GHz, measured with no input filtering. 6. The level of second harmonic of 1.01 GHz input at -25 dBm downconverted to baseband relative to 2.01 GHz at -40 dBm with the oscillator tuned to 2 GHz, measured with no input filtering. 7. Two tones within operating frequency range at 77dBV.
Absolute Maximum Ratings
All voltages are referred to Vee at 0V (pins 5,8,11,15,17,20,26,28) Characteristic
Supply Voltage, Vcc PSout &PSoutb DC offset RF & RFB input voltage All other I/O ports DC offset
Pin Min
2,13,23 3,4 21,22 1,6,7,9 10,12 14,16 18,19 24,25,27
Value Max
7 Vcc+0.3 2.5 Vcc+0.3
Units
V Vp-p Vp-p V
Conditions
Transient condition only AC coupled, transient conditions only
-0.3 Vcc-3.0 -0.3
Storage Temperature Junction Temperature NP28 package Thermal resistance Chip to ambient Chip to case Power consumption at 5.25V ESD protection
-55
+150 +150
C C
85 20 893 All 4
C/W C/W mW kV
Mil Std-883 latest revision method 3015 class 1
14
Preliminary Information
SL1925 Demo Board
The demo board contains an SL1925 direct conversion IC and SP5769 synthesiser. Reference to the specifications for each device may be required in conjunction with these notes. The board contains all components necessary to demonstrate operation of the SL1925. The schematic and PCB layout of the board are shown in figures 16, 17 and 18. The SP5769 synthesiser is provided to control each of the oscillators of the SL1925. Supplies The board must be provided with the following supplies: 5V for the synthesiser, 30V for the varactor line and 5V for the SL1925. The supply connector is a 5 pin 0.1" pitch pin header. The order of connections is 5V - GND - 30V - GND - 5V I2C Bus Connections The board is provided with a RJ11 I2C bus connector which feeds directly to the SP5769 synthesiser. This connects to a standard 4 way cable which is supplied with the interface box. Operating Instructions 4. Free running the VCO's 1. Software Use the Zarlink Semiconductor synthesiser software. Pull down the I2C bus section menu then select the SP5769. It is suggested that the charge pump setting 130uA is used, and the reference divider is set to 32. These settings give a small loop bandwidth (i.e. 100's Hz), which allows detailed phase noise measurements of the oscillators to be taken, if desired. 2. VCO control
SL1925
The two VCO's are selected by toggling port P1 on the synthesiser which in turn toggles the LOsel input of the SL1925. VCOS is switched on (and hence VCOV off) by clicking P1 on - a tick will appear. VCOS oscillates at twice the LO frequency (lower band) and is then divided by two to provide the required LO frequency in the range 950MHz to 1500MHz approximately. VCOV is switched on (and hence VCOS off) by clicking P1 off - no tick. VCOV oscillates at the LO frequency (upper band) in the range 1450MHz to 2150MHz approximatley. 3. AGC control The AGC input of the SL1925 which determines the conversion gain should be controlled by application of an external voltage to the AGC pin, TP1. Caution: Care should be taken to ensure the chip is powered ON when +ve voltages are applied to the AGC input so as to avoid powering the chip up via the ESD protection diode of the AGC input. It is recommended that a low current limit is set on the external source used.
Select the required VCO using port P1 and then using the software choose an LO frequency which is above the maximum frequency capability of the oscillator. 3GHz is suggested for both oscillators. Under this condition the varactor control voltage is pumped to its maximum value, i.e. to the top of the band. The oscillator frequency may be manually tuned by varying the 30V supply.
15
C42 100pF C47 100pF C43 100nF C49 100nF C33 100nF
C44 100pF
C41 4u7
3
30V
C4 3p9 R3 1K C25 100nF
R4 1K R100 0R
+5V GND +30V GND +5V
1 2 3 4 5
C26 100nF
5V Synth
R8 22K IC1 SL1925
J1 DC Power C51 100pF R9 15K
100nF C34
+ C52 4u7 1 5V 2 Vcc IP FI Vee I OUT LO Sel Vcc RF inA RF inB Vee AGC Q OUT NC 13 11 14 10 9 5V Synth
C23 100nF R1 1K R101 0R
OP FI Vee 27 26 25 24 5V 23 22 21 20 19 18 Vee Vee Vcc OP FQ IP FQ Vee
R2 1K C2 C1 C16 C6 220nF
28
SMA3 I OUT R5 100R C80 15pF R18 1K
C50 100nF
PSCb PSout PSoutb Vee Tanks Tanksb Vee Tankv Tankvb
C39 2n2
C14 1nF 3
PSCa
C13 1nF R10 1K VD1 1T379
4 5 6 7 8
L3
C31 15nF T1 BCW31 L1 L2 R19 1K VD2 1T379
R7 13K
LO SELECT
R102 120R 1nF 1nF 1nF TP1 Ext AGC Volts SMA2 Q OUT
C32 68pF
C30 82pF
1 CH PUMP DRIVE 9 10 11 12 5V Vee
L4
16 15 14 PSCb PSCa
VD4 BB811
1
1
APPROXIMATE STRIPLINE DIMENSIONS
L1 & L2 6.0mm X 0.44mm L1 & L2 6.15mm X 0.44mm L3 & L49.0mm XX0.44mm L3 L4 8.0mm 0.44mm
Title:
SL1925 L BAND QUADRATURE DOWNCONVERTER
3
16
LINK INFORMATION
SL1925
5V
2-3 FILTER INPUT 1-2 FILTER OUTPUT
+
J4
2
SMA5 IP/OP FI
VD3 BB811
SMA1 RF IN
2 C60 150pF 3 XTAL CAP XTAL RF IP RF IP Vcc REF/COMP ADDRESS PORT P0 12 13 SDA SCL P3/LL P2 PORT P1
IC2 SP5769
J3
4 5 6 7 8
X1 4MHz
17 16 15
SDA5 5V0 GND SCL5
3 4 5 6
C5 220nF
R6 100R
C81 15pF
R17 1K
I2C BUS
R16 10K
C3 3p9
C37 100pF
C38 100pF
C24 100nF
LINK INFORMATION 2-3 FILTER INPUT
LO SELECT
J2
1-2 FILTER OUTPUT
2
SMA6 IP/OP FQ
MITEL
Figure 16
Preliminary Information
Preliminary Information
SL1925
Figure 17 Top View
17
SL1925
Preliminary Information
Figure 18 Bottom view
18
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Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved.
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