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FEATURES Nonvolatile Memory1 Preset Maintains Wiper Settings 4-Channel Independent Programmable 64-Position Resolution Full Monotonic Operation 10 k , 50 k , and 100 k Terminal Resistance Permanent Memory Write Protection Wiper Settings Readback Linear Increment/Decrement Log Taper Increment/Decrement Push Button Increment/Decrement Compatible SPI Compatible Serial Interface with Readback Function 3 V to 5 V Single Supply or 2.5 V Dual Supply 11 Bytes User Nonvolatile Memory for Constant Storage 100-Year Typical Data Retention TA = 55 C APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment
CS CLK SDI SDO WP RDY
Nonvolatile Memory, Quad 64-Position Potentiometers AD5233*
FUNCTIONAL BLOCK DIAGRAM
AD5233
RDAC1 REGISTER VDD A1 W1 B1 RDAC1 ADDR DECODE SDI SERIAL INTERFACE SDO
EEMEM1
EEMEM CONTROL
RDAC2 REGISTER
A2 W2 B2 RDAC2
11 BYTES USER EEMEM
EEMEM2
O1 O2
DIGITAL OUTPUT BUFFER 2 DIGITAL 5 REGISTER
RDAC3 REGISTER
A3 W3 B3 RDAC3
EEMEM3
PR
RDAC4 REGISTER
A4 W4 B4 RDAC4 VSS
GND
EEMEM5
EEMEM4
GENERAL DESCRIPTION
RWA(D), RWB(D), - % of Full-Scale RAB
The AD5233 provides a nonvolatile memory, digitally controlled set of potentiometers2 with 64-position resolution. These devices perform the same electronic adjustment function as a mechanical potentiometer. The AD5233's versatile programming via a standard 3-wire serial interface allows sixteen modes of operation and adjustment including scratch pad programming, memory storing and retrieving, increment/decrement, log taper adjustment, wiper setting readback, and extra user defined EEMEM. In the scratchpad programming mode, a specific setting can be programmed directly to the RDAC2 register, which sets the resistance at terminals W-A and W-B. The RDAC register can also be loaded with a value previously stored in the EEMEM1 register. The value in the EEMEM can be changed or protected. When changes are made to the RDAC register, the value of the new setting can be saved into the EEMEM. Thereafter, such value will be transferred automatically to the RDAC register during system POWER ON, which is enabled by the internal preset strobe. EEMEM can also be retrieved through direct programming and external preset pin control.
*Patent pending NOTES 1 The terms nonvolatile memory and EEMEM are used interchangeably. 2 The terms Digital Potentiometer and RDAC are used interchangeably.
The linear step increment and decrement commands allows the setting in the RDAC register to be moved UP or DOWN, one step at a time. For logarithmic changes in wiper setting, a left/right bit shift command adjusts the level in 6 dB steps.
100 RWA RWB
75
50
25
0
0
16
32 CODE - Decimal
48
63
Figure 1. RWA(D) and RWB(D) vs. Decimal Code
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The AD5233 is available in a thin TSSOP-24 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD5233-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--10 k , 50 k , and 100 k
(VDD = 3 V
Parameter
VERSIONS
Min
-0.5 -0.5 -40
10%, or 5 V
10%, and VSS = 0 V, VA = VDD, VB = 0 V, -40 C < TA < +85 C unless otherwise noted.)
Symbol Conditions
RWB, VA = NC, MONOTONIC RWB, VA = NC D = 3FH IW = 100 A Code = Half-Scale 6 -0.5 -0.5 -1.5 0 VSS f = 1 MHz, measured to GND, Code = Half-Scale f = 1 MHz, measured to GND, Code = Half-Scale VW = VDD /2 with respect to GND, VDD = 5 V with respect to GND, VDD = 5 V with respect to GND, VDD = 3 V with respect to GND, VDD = 3 V with respect to GND, VDD = +2.5 V, VSS = -2.5 V with respect to GND, VDD = +2.5 V, VSS = -2.5 V R PULL-UP = 2.2 k to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or VDD VDD = 5 V, VSS = 0 V, TA = 25oC, Sourcing only VDD = 2.5 V, VSS = 0 V, TA = 25oC, Sourcing only VSS = 0 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VA = +2.5 V, VB = -2.5 V VIH = VDD or VIL = GND VDD = 5 V 10% 2.7 2.25 3.5 40 3 2.4 0.8 2.1 0.6 2.0 0.5 4.9 0.4 2.5 4 50 7 35 35 0.015 1
Typ1
0.1 0.1 600 15
Max
+0.5 +0.5 +20 100
Unit
LSB LSB % ppm/C
DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL Resistor Integral Nonlinearity2 R-INL Nominal Resistor Tolerance RWB Resistance Temperature Coefficient RAB/T Wiper Resistance RW
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Resolution N Differential Nonlinearity3 DNL MONOTONIC Integral Nonlinearity3 INL Voltage Divider Temperature Coefficient VW/ T Code = Half-Scale Full-Scale Error VWFSE Code = Full-Scale Zero-Scale Error VWZSE Code = Zero-Scale RESISTOR TERMINALS Terminal Voltage Range4 Capacitance5 A, B Capacitance5 W Common-Mode Leakage Current 5, 6 DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO, RDY) Output Logic Low Input Current Input Capacitance5 Output Current5 VA, B, W CA, B CW ICM VIH VIL VIH VIL VIH VIL VOH VOL IIL CIL IO1, IO2
0.1 0.1 15
+0.5 +0.5 0 +1.5 VDD
Bits LSB LSB ppm/C %FS %FS V pF pF A V V V V V V V V A pF mA mA
POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current7 Negative Supply Current
VDD VDD/VSS IDD IDD(PG) IDD(XFR) ISS
5.5 2.75 10 9
0.3
V V A mA mA
Power Dissipation8 Power Supply Sensitivity5
PDISS PSS
0.55 0.018 0.002
10 0.05 0.01
A mW %/%
-2-
REV. 0
AD5233
Parameter
DYNAMIC CHARACTERISTICS5, 9 Bandwidth Total Harmonic Distortion Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk (CW1/CW2) Analog Crosstalk (CW1/CW2)
Symbol Conditions
BW THDW THDW tS eN_WB CT CTA -3 dB, RAB = 10 k/50 k/100 k VA = 1 Vrms, VB = 0 V, f = 1 kHz, RAB = 10 k VA = 1 Vrms, VB = 0 V, f = 1 kHz, RAB = 50 k, 100 k VA = VDD, VB = 0 V, VW = 0.50% error band, Code 000H to 200H for RAB = 10 k/50 k/100 k RWB = 5 k, f = 1 kHz VA = VDD, VB = 0 V, Measure VW with Adjacent RDAC Making Full-Scale Code Change VDD = VA1 = +2.5 V, VSS = VB1 = -2.5 V, Measure VW1 with VW2 = 5 V p-p @ f = 10 kHz, Code1 = 20H, Code 2 = 3FH, RAB = 10 k/50 k/100 k
Min
Typ1
630/130/66 0.04 0.015
Max
Unit
kHz % %
0.6/2.2/3.8 9 -1
s nV/Hz nV-s
-86/-73/-68 20 10 1 10 5 5 40 50 50 0 10 4 0 0.1 10 50 70 100 100 0.15 25
dB ns ns tCYC ns ns ns ns ns ns ns ns tCYC ns ms ms ns ns s K Cycles Years
INTERFACE TIMING CHARACTERISTICS (Applies to all parts)5, 10 Clock Cycle Time (tCYC) t1 CS Setup Time t2 CLK Shutdown Time to CS Rise t3 Input Clock Pulsewidth t4 , t5 Clock Level High or Low Data Setup Time t6 From Positive CLK Transition Data Hold Time t7 From Positive CLK Transition CS to SDO-SPI Line Acquire t8 CS to SDO-SPI Line Release t9 CLK to SDO Propagation Delay11 t10 RP = 2.2 k, CL < 20 pF CLK to SDO Data Hold Time t11 RP = 2.2 k, CL < 20 pF CS High Pulsewidth12 t12 CS High to CS High12 t13 RDY Rise to CS Fall t14 CS Rise to RDY Fall Time t15 Read/Store to Nonvolatile EEMEM13 t16 Applies to Command 2H, 3H, 9H CS Rise to Clock Rise/Fall Setup t17 Preset Pulsewidth (Asynchronous) tPRW Not Shown in Timing Diagram Preset Response Time to RDY High tPRESP PR Pulsed Low to Refreshed Wiper Positions FLASH/EE MEMORY RELIABILITY Endurance14 Data Retention15
NOTES 1 Typicals represent average readings at 25C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. I W 50 A @ VDD = 2.7 V for the R AB = 10 k version, IW 50 A for the RAB = 50 k and IW 25 A for the RAB = 100 k version. See Test Circuit 1. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS. DNL specification limits of -1 LSB minimum are Guaranteed Monotonic operating conditions. See Test Circuit 2. 4 Resistor terminals A, B, and W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground referenced bipolar signal adjustment. 5 Guaranteed by design and not subject to production test. 6 Common mode leakage current is a measure of the DC leakage from any terminal B and W to a common mode bias level of V DD /2. 7 Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19. 8 PDISS is calculated from (IDD VDD) + (ISS VSS) 9 All dynamic characteristics use V DD = +2.5 V and V SS = -2.5 V 10 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = 3 V and 5 V. 11 Propagation delay depends on value of V DD, RPULL_UP, and C L see applications text. 12 Valid for commands that do not activate the RDY pin. 13 RDY pin low only for commands 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 1 ms; CMD_9, 10 0.12 ms; CMD_2, 3 20 ms. Device operation at TA = -40oC and VDD < 3 V extends the save time to 35 ms. 14 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22, Method A117 and measured at -40 C, +25C, and +85C, typical endurance at 25C is 700,000 cycles. 15 Retention lifetime equivalent at junction temperature (T J) = 55C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will derate with junction temperature as shown in Figure 11 in the Flash/EE Memory description section of this data sheet. The AD5233 contains 9,646 transistors. Die size: 69 mil 115 mil, 7,993 sq. mil. Specifications subject to change without notice.
REV. 0
-3-
AD5233
CS
t12 t3 t2
CLK CPOL = 1
t13
t1 t5 t4 t17 t11
LSB OUT
t8
SDO
t10
t10
MSB
t9
*
t7 t6
SDI MSB LSB
t14
RDY
t15 t16
*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
t12 t1 t2
CLK CPOL = 0
t3 t5 t17
t13
t4
t8
SDO
t10
MSB OUT
t11
LSB
t9
*
t7 t6
SDI MSB IN LSB
t14
RDY
t15 t16
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED. THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
-4-
REV. 0
AD5233
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, VW to GND . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V A-B, A-W, B-W, Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Digital Inputs and Output Voltage to GND . . -0.3 V, VDD + 0.3 V Operating Temperature Range3 . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ Max) . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
Thermal Resistance Junction-to-Ambient JA, TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128C/W Thermal Resistance Junction-to-Case JC, TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28C/W Package Power Dissipation = (TJ Max - TA)/ JA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Includes programming of nonvolatile memory.
ORDERING GUIDE
Model AD5233BRU10 AD5233BRU10-REEL7 AD5233BRU50 AD5233BRU50-REEL7 AD5233BRU100 AD5233BRU100-REEL7
Number of Channels 4 4 4 4 4 4
RAB (k ) 10 10 50 50 100 100
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24
Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24
Ordering Quantity 96 1,000 96 1,000 96 1,000
Top Mark* 5233B10 5233B10 5233B50 5233B50 5233BC 5233BC
*Line 1 contains ADI logo symbol and the date code YYWW, line 2 contains detail model number listed in this column.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5233 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-5-
AD5233
PIN CONFIGURATION
O1 1 CLK 2 SDI 3 SDO 4 GND 5
24 23 22
O2 RDY CS PR
AD5231
21 20
WP TOP VIEW VSS 6 (Not to Scale) 19 VDD A1 7 W1 8 B1 9 A2 10 W2 11 B2 12
18 17 16 15 14 13
AD5233
A4 W4 B4 A3 W3 B3
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4
Mnemonic O1 CLK SDI SDO
Description Nonvolatile Digital Output #1. Address(O1) = 4H, data bit position D0, Defaults to logic 1 initially. Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10 activate the SDO output. See Table III, Instruction Operation Truth Table. Other commands shift out the previously loaded SDI bit pattern delayed by 16 clock pulses. This allows daisy-chain operation of multiple packages. Ground Pin, Logic Ground Reference Negative Supply. Connect to 0 V for single supply applications. A Terminal of RDAC1 Wiper Terminal of RDAC1, address(RDAC1) = 0H B Terminal of RDAC1 A Terminal of RDAC2 Wiper Terminal of RDAC2, address(RDAC2) = 1H B Terminal of RDAC2 B Terminal of RDAC3 Wiper Terminal of RDAC3, address(RDAC3) = 2H A Terminal of RDAC3 B Terminal of RDAC4 Wiper Terminal of RDAC4, address(RDAC4) = 3H A Terminal of RDAC4 Positive Power Supply Pin Write Protect Pin. When active low, WP prevents any changes to the present contents except PR strobe, CMD_1, and CMD_8 will refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 3210 until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. Ready. Active high open drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR. Nonvolatile Digital Output #2. Address(O2) = 4H, data bit position D1, Defaults to logic 1 initially.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GND VSS A1 W1 B1 A2 W2 B2 B3 W3 A3 B4 W4 A4 VDD WP
21
PR
22 23 24
CS RDY O2
-6-
REV. 0
Typical Performance Characteristics-AD5233
0.20 0.15 0.10 TA = +85 C TA = +25 C 0.20 0.15 0.10 TA = +85 C TA = +25 C 0.20 VDD = 5V, VSS = 0V 0.15 0.10
DNL ERROR - LSB
INL ERROR - LSB
TA = +25 C
TA = +85 C
R-INL - LSB
TA = -40 C
0.05 0 -0.05 TA = -40 C -0.10 -0.15 -0.20
0.05 0 -0.05 -0.10 -0.15 -0.20
0.05 0 -0.05 -0.10 TA = -40 C -0.15 -0.20
0
16
32 48 CODE - Decimal
64
0
16
32 48 CODE - Decimal
64
0
16
32 48 CODE - Decimal
64
TPC 1. INL vs. Code, T A = -40C, +25C, +85C Overlay, RAB = 10 k
TPC 2. DNL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 10 k
TPC 3. R-INL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 10 k
0.15 0.10 TA = +85 C TA = +25 C
RHEOSTAT MODE TEMPCO - ppm/ C
VDD = 5V, VSS = 0V
2500
VDD = 5V, VSS = 0V TA = -40 C to +85 C
POTENTIOMETER MODE TEMPCO - ppm/ C
0.20
3000
1600 VDD = 5V, V SS = 0V TA = -40 C to +85 C VA = 2V VB = 0V
1200
R-DNL - LSB
2000
0.05 0 -0.05 -0.10 -0.15 -0.20 TA = -40 C
1500
800
1000
400
500
0
16
32 48 CODE - Decimal
64
0
0
16
48 32 CODE - Decimal
64
0
0
16
48 32 CODE - Decimal
64
TPC 4. R-DNL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 10 k
TPC 5. RWB /T vs. Code, RAB = 10 k
TPC 6. VWB /T vs. Code, RAB = 10 k
80 VDD = 2.7V, V SS = 0V TA = 25 C
4
0.30 VDD = 5V VSS = 0V FULL-SCALE
3 60
A
0.25
IDD @ V DD/V SS = 5V/0V
0.20
CURRENT -
IDD - mA
2
RW -
40
MIDSCALE 0.15
ZERO-SCALE
1 ISS @ V DD/V SS = 5V/0V 0 IDD @ V DD/V SS = 2.7V/0V ISS @ V DD/V SS = 2.7V/0V
0.10
20
0.05
0
0
16
48 32 CODE - Decimal
64
-1 -40
-20
0 20 40 60 TEMPERATURE - C
80
100
0
0
2
4 6 8 10 CLOCK FREQUENCY - MHz
12
TPC 7. Wiper On-Resistance vs. Code
TPC 8. IDD vs. Temperature, RAB = 10 k
TPC 9. IDD vs. Clock Frequency, RAB = 10 k
REV. 0
-7-
AD5233
3.0 0 VDD/V SS = 2.5V V A/1Vms D = MIDSCALE 0.05 0 -6 -12 -18 -24 -30 01H -36 0 10 VDD/V SS = 2.5V VA = 1V ms 100 10k 1k FREQUENCY - Hz 100k -42 100 CODE 20H 10H 08H 04H 02H 0.04 RAB = 10k
THD + NOISE - %
GAIN - dB
-3.0
f-3dB = 66kHz
0.03
-6.0
0.02 50k 100k 0.01
f-3dB = 600kHz, R AB = 10k
-9.0
f-3dB = 132kHz, R AB = 50k
-12.0 1k 10k 100k FREQUENCY - Hz 1M
AMPLITUDE - dB
1k
10k 100k FREQUENCY - Hz
1M
10M
TPC 10. -3 dB Bandwidth vs. Resistance. Test Circuit 7.
TPC 11. Total Harmonic Distortion vs. Frequency
TPC 12. Gain vs. Frequency vs. Code, RAB = 10 . Test Circuit 7.
0 CODE 20H -6 -12 -18 -24 -30 -36 10H
0 CODE 20H -6 -12 -18 -24 -30 -36 10H 08H 04H 02H 01H
80 RAB = 100k 70 60 RAB = 50k RAB = 10k
AMPLITUDE - dB
AMPLITUDE - dB
08H 04H 02H 01H
PSRR - - dB
50 40 30 20 10
-42 100
1k
10k 100k FREQUENCY - Hz
1M
-42 100
1k
10k 100k FREQUENCY - Hz
1M
0 0.1k
VDD = 5V 100mV AC VSS = 0V, VA = 5V, VB = 0V MEASURED AT VW WITH CODE = 200 H 1k 10k 100k FREQUENCY - Hz 1M 10M
TPC 13. Gain vs. Frequency vs. Code, RAB = 50 k. Test Circuit 7.
TPC 14. Gain vs. Frequency vs. Code, RAB = 100 k. Test Circuit 7.
2.60
TPC 15. PSRR vs. Frequency
VDD = 5V VA = 2.25V VB = 0V
2.58
VA
5V/DIV
2.56 2.54
VOUT - V
VDD = VA = 5V VSS = VB = 0V CODE = 20H to 1FH
5V/DIV
CS
VW EXPECTED VALUE MIDSCALE 100 s/DIV 0.5V/DIV
2.52 2.50 2.48 2.46 2.44 2.42 2.40 0 5 100 150 200 250 300 350 400 450 511 TIME - s
CLK
5V/DIV
SDI
IDD 20mA/DIV 4ms/DIV
TPC 16. Power-On Reset, VA = 2.25 V, Code = 101010B
TPC 17. Midscale Glitch Energy, Code 20H to 1FH
TPC 18. IDD vs. Time (Save) Program Mode
-8-
REV. 0
AD5233
100
5V/DIV CS
THEORETICAL - IWB_MAX - mA
VA = VB = OPEN TA = 25 C 10
5V/DIV
CLK
RAB = 10k 1 RAB = 50k 0.1
5V/DIV
SDI
IDD* 2mA/DIV 4ms/DIV *SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF INSTRUCTION #0 (NOP) IS EXECUTED IMMEDIATELY AFTER INSTRUCTION #1 (READ EEMEM)
RAB = 100k
0.01
0
8
16
24 32 40 CODE - Decimal
48
56
64
TPC 19. IDD vs. Time (Read) Program Mode
TPC 20. IMAX vs. Code
TEST CIRCUITS
Test Circuits 1 to 10 define the test conditions used in the product specification's table.
NC
A DUT B 5V VIN OFFSET GND W OP279 VOUT
DUT A W B VMS
IW
OFFSET BIAS
NC = NO CONNECT
Test Circuit 1. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
DUT A V+ B W VMS V+ = V DD 1LSB = V+/2N
Test Circuit 5. Inverting Gain
5V
VIN W OFFSET GND A DUT B
OP279
VOUT
OFFSET BIAS
Test Circuit 2. Potentiometer Divider Nonlinearity Error (INL, DNL)
DUT A VMS2 B VMS1 RW = [V MS1 - V MS2]/ IW W VW IW
Test Circuit 6. Noninverting Gain
A VIN OFFSET GND W DUT B 2.5V OP42 VOUT +15V
-15V
Test Circuit 3. Wiper Resistance
VA V+ = V DD 10% VDD V+ A B PSRR (dB) = 20 LOG PSS (%/%) = VMS% VDD%
Test Circuit 7. Gain vs. Frequency
DUT RSW = CODE = W B ISW VBIAS 0.1V ISW
H
~
W VMS
(
VMS VDD
)
+ _ 0.1V
A = NC
Test Circuit 4. Power Supply Sensitivity (PSS, PSRR)
Test Circuit 8. Incremental ON Resistance
REV. 0
-9-
AD5233
TEST CIRCUITS (continued)
NC VDD DUT VSS GND A W B VCM ICM
Scratch Pad and EEMEM Programming
NC NC = NO CONNECT
Test Circuit 9. Common-Mode Leakage Current
VDD A1 RDAC1 W1 B1 A2 RDAC2 W2 B2
The scratch pad register (RDAC register) directly controls the position of the digital potentiometer wiper. When the scratch pad register is loaded with all zeros the wiper will be connected to the B-Terminal of the variable resistor. When the scratch pad register is loaded with midscale code (one-half of full-scale position) the wiper will be connected to the middle of the variable resistor. And when the scratch pad is loaded with full-scale code, all one's, the wiper will connect to the A-Terminal. Since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. The EEMEM registers have a program erase/write cycle limitation described in the Flash/EEMEM Reliability section.
Basic Operation
VIN
NC
VOUT
~
NC = NO CONNECT
VSS
CTA = 20 log
()
VOUT VIN
Test Circuit 10. Analog Crosstalk
OPERATIONAL OVERVIEW
The basic mode of setting the variable resistor wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the command instruction #11, which includes the desired wiper position data. When the desired wiper position is determined, the user may load the serial data input register with the command instruction #2, which makes a copy of the desired wiper position data into the nonvolatile EEMEM register. After 25 ms the wiper position will be permanently stored in the nonvolatile EEMEM location. Table I provides an application-programming example listing the sequence of serial data input (SDI) words and the serial data output appearing at the SDO pin in hexadecimal format.
Table I. Set and Save RDAC data to EEMEM Register
The AD5233 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The basic voltage range is limited to a |VDD - VSS| < 5.5 V. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratch pad register allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The scratch pad register can be programmed with any position value using the standard SPI serial interface mode by loading the complete representative data word. Once a desirable position is determined this value can be saved into a EEMEM register. Thereafter the wiper position will always be set at that position for any future ON-OFF-ON power supply sequence. The EEMEM save process takes approximately 25 ms, during this time the shift register is locked preventing any changes from taking place. The RDY pin indicates the completion of this EEMEM save. There are 16 instructions which facilitates users' programming needs, (refer to Table III). The instructions are: 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Do nothing Restore EEMEM setting to RDAC Save RDAC setting to EEMEM Save user data or RDAC setting to EEMEM Decrement 6 dB Decrement all 6 dB Decrement one step Decrement all one step Reset EEMEM setting to RDAC Read EEMEM to SDO Read Wiper Setting to SDO Write data to RDAC Increment 6 dB Increment all 6 dB Increment one step Increment all one step
SDI B010H
SDO XXXXH
Action Loads data 10H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Saves copy of RDAC1 register contents into EEMEM1 register.
20xxH
B010H
At system power ON, the scratch pad register is automatically refreshed with the value last saved in the EEMEM register. The factory preset EEMEM value is midscale but thereafter, the EEMEM value can be changed by user. During operation, the scratch pad (wiper) register can also be refreshed with the current contents of the nonvolatile EEMEM register under hardware control by pulsing the PR pin without activating instruction 1 or 8. Beware that the PR pulse first sets the wiper at midscale when brought to logic zero, and then on the positive transition to logic high, it reloads the RDAC wiper register with the contents of EEMEM. Many additional advanced programming commands are available to simplify the variable resistor adjustment process (see Table III). For example, the wiper position can be changed one step at a time by using the Increment/Decrement instruction or by 6 dB at a time with the Shift Left/Right instruction command. Once an Increment, Decrement or Shift command has been loaded into the shift register, subsequent CS strobes will repeat this command. This is useful for push button control applications. See the advanced control modes section following the Instruction Operation Truth Table. A serial data output SDO pin is available for daisy chaining and for readout of the internal register contents. The serial input data register uses a 24-bit [instruction/address/data] WORD format.
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REV. 0
AD5233
EEMEM Protection
Write protect (WP) disables any changes of the scratch pad register contents regardless of the software commands, except that the EEMEM setting can be refreshed and overwrite WP by using commands 8 and PR. pulse. Therefore, the write-protect (WP) pin provides a hardware EEMEM protection feature. To disable WP, it is recommended to execute a NOP command before returning WP to logic high.
Digital Input/Output Configuration
these MicroConverter(R)s and microprocessors: ADuC812/824, M68HC11, and MC68HC16R1/916R1. ESD protection of the digital inputs is shown in Figures 4a and 4b.
VDD
LOGIC PINS
INPUT 300
All digital inputs are ESD protected high input impedance that can be driven directly from most digital sources. Active at logic low, PR and WP must be biased to VDD if they are not used. There are no internal pull-up resistors present on any digital input pins. Since the device may be detached from the driving source once it is programmed, adding pull-up resistance in the digital input pins is a good way to avoid falsely triggering the floating pins in a noisy environment. The SDO and RDY pins are open drain digital outputs where pullup resistors are needed only if using these functions. A resistor value in the range of 1 k to 10 k is a proper choice which balances the power and switching speed trade off.
Serial Data Interface
GND
Figure 4a. Equivalent ESD Digital Input Protection
VDD U INPUT 300 WP
The AD5233 contains a four-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK). The AD5233 uses a 16-bit serial data word loaded MSB first. The format of the SPI-compatible word is shown in Table II. The chip select CS pin needs to be held low until the complete data word is loaded into the SDI pin. When CS returns high, the serial data word is decoded according to the instructions in Table III. The Command Bits (Cx) control the operation of the digital potentiometer. The Address Bits (Ax) determine which register is activated. The Data Bits (Dx) are the values that are loaded into the decoded register. To program RDAC 1-4, only the 6 LSB databits are used. Table V provides an address map of the EEMEM locations. The last instruction executed prior to a period of no programming activity should be the No Operation (NOP) instruction 0. This will place the internal logic circuitry in a minimum power dissipation state.
PR VALID COMMAND COUNTER WP
GND
Figure 4b. Equivalent WP Input Protection
Daisy-Chain Operation
COMMAND PROCESSOR AND ADDRESS DECODE
5V
RPULLUP CLK SERIAL REGISTER (FOR DAISY CHAIN ONLY) SDO CS SDI GND
The serial data output pin (SDO) serves two purposes. It can be used to read out the contents of the wiper setting and EEMEM values using instructions 10 and 9 respectively. The remaining 14 instructions (#0-#8, #11-#15) are valid for daisy chaining multiple devices in simultaneous operations. Daisy chaining minimizes the number of port pins required from the controlling IC (see Figure 5). The SDO pin contains an open drain N-Ch FET that requires a pull-up resistor, if this function is used. As shown in Figure 5, users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-SDI interface may require an additional time delay between subsequent packages. When two AD5233s are daisy chained 32 bits of data are required. The first 16 bits go to U2 and the second 16 bits go to U1. The 16 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, then 8-bits of data. The CS should be kept low until all 32 bits are clocked into their respective serial registers. The CS is then pulled high to complete the operation.
+V
AD5233
AD5233
Figure 3. Equivalent Digital Input-Output Logic
RP 2k SDO SDI
AD5233
U2
CS SDO
The equivalent serial data input and output logic is shown in Figure 3. The open drain output SDO is disabled whenever chip select CS is logic high. The SPI interface can be used in two slave modes CPHA = 1, CPOL = 1, and CPHA = 0, CPOL = 0. CPHA, and CPOL refer to the control bits, which dictate SPI timing in
C
SDI
U1
CS
CLK
CLK
Figure 5. Daisy Chain Configuration Using SDO
MicroConverter is a registered trademark of Analog Devices, Inc.
REV. 0
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AD5233
Table II. 16-Bit Serial Data Word
MSB
RDAC EEMEM C3 C3 C2 C2
Instruction Byte
C1 C1 C0* 0 C0 A3 0 A2 A1 A1 A0 A0
LSB
X D7 X D6 D5 D5
Data Byte
D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
*Command bits are C0 to C3. Address bits are A3-A0. Data bits D0 to D5 are applicable to RDAC wiper register whereas D0 to D7 are applicable to EEMEM register. Command instruction codes are defined in Table III.
Table III. Instruction Operation Truth Table 1, 2, 3 Instruction Byte 0 Inst. B16 * * * * * * * * * * * * * * * * * * * B8 No. C3 C2 C1 C0 A3 A2 A1 A0 0 1 0 0 0 0 0 0 0 1 X 0 X 0 X X Data Byte 0 B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X X
Operation NOP: Do Nothing. See Table X for programming example. Write content of EEMEM to RDAC Register. This command leaves device in the Read Program power state. To return part to the idle state, perform NOP instruction #0. See Table X. SAVE WIPER SETTING: Write contents of RDAC at address A1 A0 to EEMEM. See Table IX. Write contents of Serial Register Data Byte 0 (total 8-bit) to EEMEM(ADDR). See Table XII. Decrement 6 dB: Right Shift contents of RDAC Register, stops at all "Zeros." Decrement all 6 dB: Right Shift contents of all RDAC Registers, stops at all "Zeros." Decrement content of RDAC Register by "One," stops at all "Zero." Decrement contents of all RDAC Registers by "One," stops at all "Zero." RESET: Load all RDACs with their corresponding EEMEM previously-saved values Transfer content of EEMEM(ADDR) to Serial Register Data Byte 0 and previously stored data can be read out from SDO pin. See Table XIII. Transfer content of RDAC (ADDR) to Serial Register Data Byte 0 and wiper setting can be read out from SDO pin. See Table XIV. Write content of Serial Register Data Byte 0 (total 6-bit) to RDAC. See Table VIII. Increment 6 dB: Left Shift content of RDAC Register, stops at all "Ones." See Table XI. Increment all 6 dB: Left Shift contents of RDAC Registers, stops at all "Ones." Increment content of RDAC Register by "One," stops at all "Ones." See Table IX. Increment contents of all RDAC Registers by "One," stops at all "Ones."
A1 A0
2 34 45 55 65 75 8 9
0 0 0 0 0 0 1 1
0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
0
0
A1 A0
X D7 X X X X X X
X
X
X
X
X
X
X
A3 A2 A1 A0 0 X 0 X X 0 X 0 X X A1 AO X X
D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A1 A0 X X X X
A3 A2 A1 A0
10
1
0
1
0
0
0
A1 A0
X
X
X
X
X
X
X
X
11 125 135 145 155
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
0 0 X 0 X
0 0 X 0 X
A1 A0 A1 A0 X X
X X X X X
X X X X X
D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X X X X X X X X X X
A1 A0 X X
NOTES 1 The SDO output shifts out the last 16-bits of data clocked into the serial register for daisy-chain operation. Exception, any instruction that follows Instruction #9 or #10, see details of these instruction for proper usage. 2 The RDAC register is a volatile scratch pad register that is automatically refreshed at power ON from the corresponding non-volatile EEMEM register. 3 Execution of the above Operations takes place when the CS strobe returns to logic high. 4 Instruction #3 write one data byte (8-bit data) to EEMEM. But in the cases of addresses 0, 1, 2, 3 only the last 6 bits are valid for wiper position setting. 5 The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
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REV. 0
AD5233
Terminal Voltage Operation Range
VDD
The AD5233 positive VDD and negative VSS power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or VSS will be clamped by the internal forward biased diodes (see Figure 6).
VDD
OUTPUTS O1 AND O2 PINS
GND
A W
Figure 7. Logic Outputs O1 and O2.
ADVANCED CONTROL MODES
B
VSS
Figure 6. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5233 device is primarily used as a digital ground reference that needs to be tied to the PCB's common ground. The digital input control signals to the AD5233 must be referenced to the device ground pin (GND), and satisfy the logic level defined in the specification table of this data sheet. An internal level shift circuit ensures that the common-mode voltage range of the three-terminals extends from VSS to VDD regardless of the digital input level. Power Up Sequence Since there are diodes to limit the voltage compliance at terminals A, B, and W (see Figure 6) it is important to power VDD/VSS first before applying any voltages to terminals A, B, and W. Otherwise, the diode will be forward biased such that VDD/VSS will be powered unintentionally. For example, applying 5 V across terminals A and B prior to VDD will cause the VDD terminal to exhibit 4.3 V. It is not destructive to the device, but it may affect the rest of the user's system. As a result, the ideal power up sequence is in the following order: GND, VDD, VSS, Digital Inputs, and VA/B/W. The order of powering VA, VB, VW, and Digital Inputs is not important as long as they are powered after VDD/VSS. Regardless of the power up sequence and the ramp rates of the power supplies, once VDD/VSS are powered, the power-on reset remains effective, which retrieves EEMEM saved values to the RDAC registers. Latched Digital Outputs A pair of digital outputs, O1 and O2, are available on the AD5233 that provide a nonvolatile logic 0 or logic 1 setting. O1 and O2 are standard CMOS logic outputs shown in Figure 7. These outputs are ideal to replace functions often provided by DIP switches. In addition, they can be used to drive other standard CMOS logic controlled parts that need an occasional setting change. O1 and O2, are defaulted to logic 1 initially.
The AD5233 digital potentiometer contains a set of user programming features to address the wide applications available to these universal adjustment devices. Key programming features include: * Scratch Pad Programming to any desirable values * Nonvolatile memory storage of the present scratch pad RDAC register value into the EEMEM register * Increment and Decrement instructions for RDAC wiper register * Left and right Bit Shift of RDAC wiper register to achieve 6 dB level changes * Eleven extra bytes of user addressable nonvolatile memory
Linear Increment and Decrement Commands
The increment and decrement commands (#14, #15, #6, #7) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the device. For the increment command, executing instruction #14 with proper address will automatically move the wiper to the next resistance segment position. Instruction #15 performs the same function except that address does not need to be specified. All RDACs are changed at the same time.
Logarithmic Taper Mode Adjustment ( 6 dB/Step)
Four programming instructions produce logarithmic taper increment and decrement wiper. These settings are activated by the 6 dB increment and 6 dB decrement instructions #12, #13, #4, and #5 respectively. For example, starting at zero scale, executing eight increment instructions #12 will move the wiper in 6 dB per step from the 0% to full scale RAB. The 6 dB increment instruction doubles the value of the RDAC register content each time the command is executed. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale 6310 code position. Further 6 dB per increment instruction will no longer change the wiper position beyond its full scale. 6 dB step increment and decrement are achieved by shifting the bit internally to the left and right respectively. The following information explains the nonideal 6 dB step adjustment at certain conditions. Table IV illustrates the operation of the shifting function on the RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift #12 and #13 commands were modified such that if the data in the RDAC register is equal to zero, and the data is left shifted, the RDAC register is then set
REV. 0
-13-
AD5233
to code 1. Similarly, if the data in the RDAC register is greater than or equal to mid-scale, and the data is left shifted, then the data in the RDAC register is automatically set to full-scale. This makes the left shift function as ideal logarithmic adjustment as is possible. The right shift #4 and #5 commands will be ideal only if the LSB is zero (i.e. ideal logarithmic--no error). If the LSB is a one then the right shift function generates a linear half LSB error, which translates to a numbers of bits dependent logarithmic error as shown in Figure 8. The plot shows the error of the odd numbers of bits for AD5233.
Table IV. Detail Left and Right Shift Functions for 6 dB Step Increment and Decrement Table V. EEMEM Address Map
EEMEM Number 1 2 3 4 5 6 7 : 15 16
Address 0000 0001 0010 0011 0100 0101 0110 : 1110 1111
EEMEM Content For RDAC11, 2 RDAC21, 2 RDAC31, 2 RDAC41, 2 O1 and O23 USER14 USER2 : USER10 USER11
Left Shift 00 0000 00 0001 00 0010 00 0100 00 1000 01 0000 10 0000 11 1111 11 1111
Right Shift 11 1111 01 1111 00 1111 00 0111 00 0011 00 0001 00 0000 00 0000 00 0000
Left Shift (+6 dB/Step)
Right Shift (-6 dB/Step)
NOTES 1 RDAC data stored in the EEMEM location is transferred to the RDAC REGISTER at Power ON, or when instructions Inst#1, #8, and PR are executed. 2 Execution of instruction #1 leaves the device in the Read Mode power consumption state. After the last Instruction #1 is executed, the user should perform a NOP, Instruction #0 to return the device to the low power idling state. 3 O1 and O2 data stored in EEMEM locations are transferred to their corresponding DIGITAL REGISTER at Power ON, or when instructions #1 and #8 are executed. 4 USER <#> are internal nonvolatile EEMEM registers available to store and retrieve constants and other 8-bit information using Inst#3 and Inst#9 respectively.
RDAC STRUCTURE
Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each Right Shift #4 and #5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in Figure 8 shows plots of Log_Error [i.e. 20 log10 (error/code)] AD5233. For example, code 3 Log_Error = 20 log10 (0.5/3) = -15.56 dB, which is the worst case. The plot of Log_Error is more significant at the lower codes.
0
-10
The patent pending RDAC contains multiple strings of equal resistor segments, with an array of analog switches, that act as the wiper connection. The number of positions is the resolution of the device. The AD5233 has 64 connection points allowing it to provide better than 1.5% set ability resolution. Figure 9 shows an equivalent structure of the connections between the three terminals of the RDAC. The SWA and SWB will always be ON, while one of the switches SW(0) to SW(2N - 1) will be ON one at a time depending on the resistance position decoded from the Data Bits. Since the switch is not ideal, there is a 15 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed.
SWA A
-20 dB -15.56dB @ CODE 3 SW(2N-1) -30 RDAC WIPER REGISTER AND DECODER 0 5 10 15 20 25 30 35 40 45 50 55 60 65 RS
W SW(2N- 2)
-40
-50
RS
SW(1)
CODE
Figure 8. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits is Ideal)
RS RS = RAB / 2N DIGITAL CIRCUITRY OMITTED FOR CLARITY
SW(0)
The AD5233 contains additional internal user storage registers (EEMEM) for saving constants and other 8-bit data. Table V provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and 11 bytes of USER EEMEM.
SWB B
Figure 9. Equivalent RDAC Structure (Patent Pending)
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REV. 0
AD5233
PROGRAMMING THE VARIABLE RESISTOR RHEOSTAT OPERATION
between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches. Like the mechanical potentiometer the RDAC replaces, the AD5233 parts are totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled complementary resistance R WA. Figure 10 shows the symmetrical programmability of the various terminal connections. When RWA is used, the B-terminal can be let floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: R WA( D ) = 64 - D x RAB + RW 64 (2)
The nominal resistance of the RDAC between terminals A-and-B, RAB, are available with 10 k, 50 k and 100 k with 64 positions (6-bit resolution). The final digit(s) of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50, 100 k = 100. The 6-bit data word in the RDAC latch is decoded to select one of the 64 possible settings. The following discussion describes the calculation of resistance RWB at different codes of a 10 k part. For VDD = 5 V, the wipers first connection starts at the B terminal for data 00H. RWB(0) is 15 because of the wiper resistance and it is independent to the nominal resistance. The second connection is the first tap point where RWB(1) becomes 156 + 15 = 171 for data 01H. The third connection is the next tap point representing RWB(2) = 312 + 15 = 327 for data 02H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB(63) = 9858 . See Figure 9 for a simplified diagram of the equivalent RDAC circuit. When RWB is used, the A-terminal can be let floating or tied to the wiper.
100 RWA RWB
For example, the following output resistance values will be set for the following RDAC latch codes with VDD = 5 V (applies to RAB = 10 k Digital Potentiometers):
Table VII. RWA(D) at Selected Codes for RAB = 10 k
D (DEC) RWA(D) ( )
RWA(D), RWB(D), - % of Full-Scale RAB
Output State Full-scale Mid-scale 1 LSB Zero-scale
75
63 32 1 0
171 5015 9858 10015
50
Channel-to-channel RAB matching is better than 1%. The change in RAB with temperature has a 600 ppm/C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
25
0
0
16
32 CODE - Decimal
48
63
Figure 10. RWA(D) and RWB(D) vs. Decimal Code
The general equation, which determines the programmed output resistance between W and B, is: D R WB( D ) = x RAB + R W (1) 64 Where D is the decimal equivalent of the data contained in the RDAC register, RAB is the Nominal Resistance between terminals A-and-B, and RW is the wiper resistance. For example, the following output resistance values will be set for the following RDAC latch codes with VDD = 5 V (applies to RAB = 10 k Digital Potentiometers):
Table VI. RWB(D) at Selected Codes for RAB = 10 k
The digital potentiometer can be configured to generate an output voltage at the wiper terminal which is proportional to the input voltages applied to terminals A and B. For example connecting A-terminal to 5 V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at 0 V up to 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 2N position resolution of the potentiometer divider. Since AD5233 can also be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any given input voltages applied to terminals A and B is: VW ( D ) = D x VAB + VB 64 (3)
D (DEC) 63 32 1 0
RWB(D) ( ) 9858 5015 171 15
Output State Full-scale Mid-scale 1 LSB Zero-scale (Wiper contact resistance)
Equation 3 assumes VW is buffered so that the effect of wiper resistance is nulled. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors and not the absolute value, therefore, the drift improves to 15 ppm/C. There is no voltage polarity restriction between terminals A, B, and W as long as the terminal voltage (VTERM) stays within VSS < VTERM < VDD.
PROGRAMMING EXAMPLES
Note that in the zero-scale condition a finite wiper resistance of 15 is present. Care should be taken to limit the current flow REV. 0
The following programming examples illustrate the typical sequence of events for various features of the AD5233. Users should refer to Table III for the instructions and data word format. The Instruction numbers, addresses, and data appearing at SDI and SDO pins are displayed in hexadecimal format in the following examples. -15-
AD5233
Table VIII. Scratch Pad Programming Table XIV. Reading Back Wiper Settings
SDI B010H
SDO
Action
SDI B020H C0XXH A0XXH
SDO XXXXH B020H C0XXH
Action Sets RDAC1 to mid-scale Doubles RDAC1 from mid-scale to full-scale (Left Shift Instruction) Prepares reading wiper setting from RDAC1 register Readback full-scale value from RDAC1 register
XXXXH Loads data 10H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position
Table IX. Incrementing RDAC1 Followed by Storing the Wiper Setting to EEMEM1
XXXXH A03FH
SDI B010H E0XXH E0XXH 20XXH
SDO XXXXH B010H E0XXH XXXXH
Action Loads data 10H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position Increments RDAC1 register by one to 11H Increments RDAC1 register by one to 12H Continue until desired wiper position reached Saves RDAC1 register data into EEMEM1 Optionally tie WP to GND to protect EEMEM values
FLASH/EEMEM RELIABILITY
The Flash/EE Memory array on the AD5233 is fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as: 1. Initial page erase sequence 2. Read/verify sequence 3. Byte program sequence 4. Second read/verify sequence During reliability qualification Flash/EE memory is cycled from 00H to 3FH until a first fail is recorded signifying the endurance limit of the on-chip Flash/EE memory. As indicated in the specification pages of this data sheet, the AD5233 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of -40C to +85C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the AD5233 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (T J = 55C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full-specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 V, will derate with TJ as shown in Figure 11. For example, the data is retained for 100 years at 55oC operation, but reduces to 15 years at 85oC operation. Beyond such limit, the part must be reprogrammed so that the data can be restored.
Table X. Restoring EEMEM1 Value to RDAC1 Register
EEMEM value for RDAC can be restored by Power On, Strobing PR pin, or two different commands as shown below SDI 10XXH 00XXH 8XXXH SDO XXXXH 10XXH 00XXH Action Restores EEMEM1 value to RDAC1 register NOP. Recommended command to minimize power consumption Reset EEMEM1 value to RDAC1 register
Table XI Using Left Shift by One to Increment 6 dB Step
SDI C0XXH
SDO XXXXH
Action Moves wiper to double the present data contained in RDAC1 register
Table XII. Storing Additional User Data in EEMEM
SDI 35AAH 3655H
SDO XXXXH 35AAH
Action Stores data AAH into spare EEMEM6 location USER1 (Allowable to address in 11 locations with maximum 8 bits of Data) Stores data 55H into spare EEMEM7 location USER2. (Allowable to address 11 locations with maximum 8 bits of data)
Table XIII. Reading Back Data from Various Memory Locations
SDI 95XXH 00XXH
SDO XXXXH 95AAH
Action Prepares data read from USER1 location NOP instruction #0 sends 16-bit word out of SDO where the last 8 bits contain the contents of USER1 location. NOP command ensures device returns to idle power dissipation state
-16-
REV. 0
AD5233
300
Similarly, it is also likely to ring when the switching between two gain values, this is equivalent to a step change at the input. Depending on the op amp GBP, reducing the feedback resistor may extend the Zero's frequency far enough to overcome the problem, a better approach is to include a compensation capacitor C2 to cancel the effect caused by C1. Optimum compensation occurs when R1 C1 = R2 C2. This is not an option because of the variation of R2. As a result, one may use the relationship above and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance when R2 is set at low values. On the other hand, it will avoid the ringing or oscillation at the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of few pF to no more than few tenths of pF is usually adequate for the compensation. Similarly, there are W and A terminal capacitances connected to the output (not shown), their effect at this node is less significant and the compensation can be avoided in most cases.
High Voltage Operation
250
RETENTION - Years
200
150
ADI TYPICAL PERFORMANCE AT TJ = 55 C
100
50
0 40
50
60 70 80 90 TJ JUNCTION TEMPERATURE - C
100
110
Figure 11. Flash/EE Memory Data Retention
APPLICATIONS Bipolar Operation From Dual Supplies
The AD5233 can be operated from dual supplies 2.5 V, which enables control of ground referenced AC signals or bipolar operation. AC signals, as high as VDD/VSS, can be applied directly across terminals A-B with the output taken from terminal W, see Figure 12 for a typical circuit connection.
+2.5V VDD C GND SS SCLK MOSI CS CLK SDI VDD A W GND B VSS 1.25V p-p 2.5V p-p
The Digital Potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across terminals A-B, W-A, or W-B does not exceed |5 V|. When high voltage gain is needed, users should set a fixed gain in an op amp operated at high voltage, and let the digital potentiometer control the adjustable input, Figure 14 shows a simple implementation. Similarly, a compensation capacitor C may be needed to dampen the potential ringing when the digital potentiometer changes steps. This effect is prominent when stray capacitance at the inverting node is augmented by large feedback resistor. In general, a few picofarad capacitor C is adequate to combat the problem.
C R 2R 15V
AD5233
D = MIDSCALE
-2.5V
Figure 12. Bipolar Operation from Dual Supplies
Gain Control Compensation
5V A
- A2 W +
V+ V- VO 0 TO 15V
Digital Potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in Figure 13.
C2 10pF R2 100k B A R1 33.2k C1 35pF Vi U1 W
AD5233
B
Figure 14. 15 V Voltage Span Control
Programmable Voltage Reference
VO
For voltage divider mode operation, Figure 15, it is common to buffer the output of the digital potentiometer unless the load is much larger than RWB. Not only does the buffer serve the purpose of impedance conversion, but also allows heavier loads to be driven.
5V
Figure 13. Typical Noninverting Gain Amplifier
1
Notice that when RDAC B terminal parasistic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/O term with 20 dB/dec whereas a typical opamp GBP has -20 dB/dec characteristics. A large R2 and finite C1 can cause this Zero's frequency to be falling well below the crossover frequency. Hence the rate of closure becomes 40 dB/dec and the system has a 0 phase margin at the crossover frequency. The output may ring or oscillate if an input is a rectangular pulse or step function. REV. 0 -17-
U1 VIN VOUT 3
AD5233
5V A B W V+
GND 2 AD1582
AD8601
V- A1
VO
Figure 15. Programmable Voltage Reference
AD5233
Bipolar Programmable Gain Amplifier
There are several ways to achieve bipolar gain, Figure 16 shows one versatile implementation. Digital potentiometer U1 sets the adjustment range; therefore the wiper voltage VW2 can be programmed between Vi and -KVi at a given U2 setting. Configuring A2 as an noninverting amplifier yields a linear transfer function:
D2 VO R2 = 1 + x 64 x (1 + K ) - K Vi R1
where Q = Q factor, O = resonant frequency, R1 and R2 = RWB1 and RWB2 respectively. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. Users can first select some convenient values for the capacitors, then gang and move R1 and R2 together to adjust -3 dB corner frequency. Instructions #5, #7, #13, and #15 of the AD5233 make these change simple to implement.
C1
(4)
where K is the ratio of RWB /RWA which is set by U1 and D = Decimal Equivalent of the Input Code.
VDD U2 V+ W2 B2 A2 Vi A1 B1 W1 U1 VDD V+ -kVi R1
Vi A
+2.5V R1 B W R R C2 A R2 B W V+
AD8601
V- U1 -2.5V
VO
AD5233
A2
OP2177
V- R2 VSS
VO C
GANGED TOGETHER
Figure 17. Sallen Key Low-Pass Filter
Programmable State-Variable Filter
AD5233
OP2177
V- A1
VSS
Figure 16. Bipolar Programmable Gain Amplifier
In the simpler (and much more usual) case, where K = 1, a pair of matched resistors can replace U1. Equation 4 simplifies to:
2D VO R2 = 1+ x 2 - 1 Vi R1 64
(5)
One of the standard circuits used to generate a low-pass, highpass, or bandpass filter is the state variable active filter. The digital potentiometer AD5233 allows full programmability of the frequency, gain, and the Q of the filter outputs. Figure 18 shows the filter circuit using a 2.5 V virtual ground, which allows a 2.5 Vp input and output swing. RDAC2 and 3 set the LP, HP, and BP cutoff and center frequencies respectively. RDAC2 and RDAC3 should be programmed with the same data (as with ganged potentiometers) to maintain the best circuit Q. The transfer function of the Bandpass Filter is:
VBP Vi AO S2 + O S Q
(9)
Table XV shows the result of adjusting D, with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 64 step resolution.
Table XV. Result of Bipolar Gain Amplifier
=
O 2 S + O Q
D 0 16 32 48 63
R1 = -1 -0.5 0 0.5 0.968
, R2 = 0
R1 = R2 -2 -1 0 1 1.937
R2 = 9R1 -10 -5 0 5 9.680
where AO is the gain. For RWB2(D2) = RWB3(D3), R1 = R2, and C1 = C2:
O =
1 RWB 2C1 RWB1 RWA1
(10) (11) (12)
Programmable Low-Pass Filter
AO = -
Q=
Digital potentiometer AD5233 can be used to construct a second order Sallen Key Low-Pass Filter, Figure 17. The design equations are:
VO = Vi O O 2 2 S+ S + O Q
2
RWA 4 R x WB1 RWB 4 R1
(6)
O = Q=
1 R1R2C1C 2
(7)
1 1 + R1C1 R2C 2
Figure 19 shows the measured filter response at the bandpass output as a function of the RDAC2 and RDAC3 settings which produce a range of center frequencies from 2 kHz to 20 kHz. The filter gain response at the bandpass output is shown in Figure 20. At a center frequency of 2 kHz, the gain is adjusted over -20 dB to +20 dB range determined by RDAC1. Circuit Q is adjusted by RDAC4 and RDAC1. The suitable op amps for this application are OP4177, AD8604, OP279, and AD824.
(8)
-18-
REV. 0
AD5233
RDAC4 VIN B RDAC1 A1 A2 2.5V OP279 2 B RDAC2 A3 B RDAC3 A4 BANDPASS HIGHPASS LOWPASS B R1 10k R2 10k
At resonance, setting
0.01 F 0.01 F
R2 =2 (15) R1 balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure the oscillation can start. On the other hand, the alternate turn-on of the diodes D1 and D2 ensures R2/R1 to be smaller than 2 momentarily and therefore stabilizes the oscillation. Once the frequency is set, the oscillation amplitude can be tuned by R2B since: 2 V = I D R2B + VD 3O (16)
Figure 18. Programmable Stable Variable Filter
40 -16 20k
20
AMPLITUDE - dB
0
*
-20
-40
-60
VO, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium will be reached such that VO converges. R2B can be in series with a discrete resistor to increase the amplitude but the total resistance cannot be too large to saturate the output. In this configuration, R2B can be adjusted from minimum to full scale with amplitude varied from 0.6 V to 0.9 V. Using 2.2 nF for C and C', 10 k dual digital potentiometer, with R and R' set to 8 k, 4 k, and 700 , oscillation occurs at 8.8 kHz, 17.6 kHz, and 100 kHz respectively, see Figure 22. In both circuits in Figure 17 and 21, the frequency tuning requires that both RDACs to be adjusted to the same settings. Since the two channels may be adjusted one at a time, an intermediate state will occur that may not be acceptable for certain applications. Of course, the increment/decrement all instructions #5, #7, #13, #15 can be used. Different devices can also be used in daisy-chained mode so that parts can be programmed to the same setting simultaneously.
FREQUENCY ADJUSTMENT
-80
20
100
1k FREQUENCY - Hz
10k
100k 200k
Figure 19. Programmed Center Frequency Bandpass Response
40 -19.01 2.0k
20
VP AMPLITUDE - dB
C 2.2nF +2.5V
R 10k A W B
0
C 2.2nF
B R 10k A W
-20
*
V+
U1
VO
OP1177
-40
R = R = R2B = 1/4 AD5233 D1 = D2 = 1N4148 VN R2B 10k R1 1k B W A R2A 2.1k D1 D2 V- -2.5V
-60
-80
20
100
1k FREQUENCY - Hz
10k
100k 200k
Figure 20. Programmed Amplitude Bandpass Response
Programmable Oscillator
AMPLITUDE ADJUSTMENT
In a classic Wien-bridge oscillator, Figure 21, the Wien network (R, R', C, C') provides positive feedback, while R1 and R2 provide negative feedback. At the resonant frequency, fO, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. If the op amp is chosen with relatively high gain bandwidth product, the frequency response of the op amp can be neglected. With R = R', C = C', and R2 = R2A // (R2B + RDIODE), the oscillation frequency is:
1 1 or fO = 2RC RC where R is equal RWA such that: O = R= 64 - D RAB 64
Figure 21. Programmable Oscillator with Amplitude Control
1V/DIV
R = 8.06k f = 8.8kHz
1V/DIV R = 4.05k f = 17.6kHz
(13)
1V/DIV
R = 670 f = 102kHz
(14) -19-
Figure 22. Programmable Oscillation
REV. 0
AD5233
Programmable Voltage Source with Boosted Output
For applications require high current adjustment such as laser diode driver or turnable laser, a boosted voltage source can be considered, see Figure 23.
VS 5V VBIAS
125 load. Should higher voltage compliance be needed, users may consider digital potentiometers AD5260, AD5280, and AD7376. Figure 25 shows an alternate circuit for high voltage compliance.
Programmable Bidirectional Current Source
AD5233
A B W A1
R1 10k
P1 SIGNAL CC
For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution, Figure 25. If the resistors are matched, the load current is R2 A + R2 B R1 IL = x VW R2 B
R1 150k R2 15k
RBIAS IBIAS
V+ N1 V-
LD
(17)
A1 = AD8601, AD8605, AD8541 P1 = FDN360P, NDS9430 N1 = FDV301N, 2N7002
Figure 23. Programmable Booster Voltage Source
+15V - +2.5V A V+
C1 10pF
In this circuit, the inverting input of the opamp forces the VBIAS to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the P-Ch FET P1. The N-Ch FET N1 simplifies the opamp driving requirement. A1 needs to be rail-to-rail input type. Resistor R1 is needed to prevent P1 for not turning off once it is on. The choice of R1 is a balance between the power loss of this resistor and the output turn off time. N1 can be any general purpose signal FET; on the otherhand, P1 is driven in the saturation state and therefore its power handling must be adequate to dissipate (VS - VBIAS) IBIAS power. This circuit can source maximum of 100 mA at 5 V supply. Higher current can be achieved with P1 in larger package. Note that a single N-Ch FET can replace P1, N1, and R1 altogether. However, the output swing will be limited unless separate power supplies are used. For precision applications, a voltage reference such as ADR423, ADR292, and AD1584, can be applied at the input of the digital potentiometer.
Programmable 4 mA-to-20 mA Current Source
OP2177
+15V + V+ C2 10pF -15V R1 150k R2A 14.95k VL RL 500 IL + V- A2 R2B 50
AD5233
BW -2.5V
OP2177
- V- A1 -15V
Figure 25. Programmable Bidirectional Current Source
R2B in theory can be made as small as needed to achieve the current needed within A2 output current driving capability. In this circuit OP2177 delivers 5 mA in both directions and the voltage compliance approaches 15 V. If there are no C1 and C2, if can be shown that the output impedance becomes
ZO = R1R2' - R1' ( R2 A + R2B ) R1' R2B ( R1 + R2 A)
(18)
A programmable 4 mA-to-20 mA current source can be implemented with the circuit shown in Figure 24. REF191 is a unique low supply headroom precision reference that can deliver the 20 mA needed at 2.048 V. The load current is simply the voltage across terminals B-to-W of the digital pot divided by RS.
+5V 2 VIN 3 SLEEP VOUT 6 U1 0 TO (2.048 + VL) B C1 1F A +5V - W RS 102
ZO can be infinite if resistors R1' and R2' match precisely with R1 and R2A + R2B respectively. On the other hand, ZO can be negative if the resistors are not matched. As a result, C1 and C2, in the range of 1 F to 10 pF are needed to prevent the oscillation.
Resistance Scaling
REF191
GND 4
AD5233 offers 10 k, 50 k, and 100 k nominal resistance. For users who need lower resistance while maintaining the number of adjustment step, they can parallel multiple devices. For example, Figure 26 shows a simple scheme of paralleling two AD5233 channels. To adjust half of the resistance linearly per step, users need to program both devices coherently with the same settings.
VDD A1
VL RL 100 IL
AD5233
-2.048V TO VL
V+ U2
OP1177
+ V- -5V
A2 W1 B2 W2
B1 LD
Figure 24. Programmable 4-to-20 mA Current Source
Figure 26. Reduce Resistance by Half with Linear Adjustment Characteristics
The circuit is simple, but beware two things. First, dual supply op amps are ideal because the ground potential of REF191 can swing from -2.048 V at zero-scale to VL at full-scale of the potentiometer setting. Although the circuit works under single supply, the programmable resolution of system will be reduced. Second, the voltage compliance at VL is limited to 2.5 V or equivalently a
In voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in Figure 27. The equivalent resistance become: RWBeq = D R1 R2 + RW 64
(
)
(19) REV. 0
-20-
AD5233
D R WAeq = 1 - R1 R2 + RW 64
(
)
B R2 A
(20)
R1* -
W C1
A
AD8601
R2 R1 W
Vi + U1
VO
*REPLACED WITH ANOTHER CHANNEL OF RDAC
B R2 << R1
Figure 27. Lowering the Nominal Resistance
Figure 30. Linear Gain Control with Tracking Resistance Tolerance, and Temperature Coefficient
Figures 26 and 27 show that the digital potentiometer steps change linearly. On the other hand, log taper adjustment is usually preferred in applications like audio control. Figure 28 shows another way of resistance scaling. In this configuration, the smaller the R2 with respect to R1, the more the pseudo log taper characteristic behaves.
Vi A R1 B W R2 VO
Notice the circuit in Figure 31 can also be used to track the tolerance, temperature coefficient, and drift in this particular application. The characteristic of the transfer function is however a pseudologarithmic, rather than a linear, gain function.
ARB W C1
-
AD8601
VO
Figure 28. Resistor Scaling with Pseudo Log Adjustment Characteristics
Doubling The Resolution
Vi
+
U1
Borrowing from ADI's patented RDAC segmentation technique, we can configure three channels of AD5233 as shown in Figure 29 by paralleling a discrete resistor R p (R p = RAB/64) with RDAC3, we can double the resolution of AD5233 from 6-bit to 12-bit. We may think of moving RDAC1 and RDAC2 together forms the coarse 6-bit resolution, then moving RDAC3 forms the finer 6-bit resolution. As a result, the effective resolution becomes 12-bit. Nevertheless, the precision of this circuit remains only 6-bit accurate and the programming can be complicated.
VA A1 RDAC1 B1 RP A2 RDAC2 B2 A3 RDAC3 W3 B3
Figure 31. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift
RDAC CIRCUIT SIMULATION MODEL
RDAC 10k
A CA 35pF
B CB 35pF
CW 35pF W
Figure 32. RDAC Circuit Simulation Model for RDAC = 10 k
Figure 29. Doubling AD5233 from 6-Bit to 12-Bit
Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations
The internal parasitic capacitances and the external load dominate the ac characteristics of the RDACs. Configured as a potentiometer divider the -3 dB bandwidth of the AD5233 (10 k resistor) measures 630 kHz at half scale. TPC 10 provides the large signal BODE plot characteristic. A parasitic simulation model is shown in Figure 32. Listing I provides a macro-model net list for the 10 k RDAC:
Listing I. Macro-model Net List for RDAC .PARAM D=64, RDAC=10E3 * .SUBCKT DPOT (A,W,B) * A 0 35E-12 A W {(1-D/64)*RDAC+15} W 0 35-12 W B {D/64*RDAC+15} B 0 35E-12 * .ENDS DPOT
In the rheostate mode operation such as gain control, Figure 30, the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issue among various systems. Because of the inherent matching of the silicon process, it is practical to apply the dual or multiple channel device in this type of applications. As such, R1 should be replaced by one of the channels of the digital potentiometer and programmed to a specific value. R2 can be used for the adjustable gain. Although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between R1 and R2. In addition, this approach also tracks the resistance drift over time. As a result, all these non-ideal parameters become less sensitive to the system variations.
CA RAW CW RBW CB
REV. 0
-21-
AD5233
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE* Part Number AD5201 Number of VRs per Package 1 Terminal Voltage Range (V) 3, +5.5 Interface Data Control 3-Wire Nominal Resistance (k ) 10, 50 Resolution Power Supply (No. of Wiper Current Positions) (IDD) ( A) Packages 33 40 SOIC-10
Comments Full ac Specs, Dual Supply, Pwr-On-Reset, Low Cost No Rollover, Pwr-On-Reset Single 28 V or Dual 15 V Supply Operation Full ac Specs, Dual Supply, Pwr-On-Reset Full ac Specs 5 V to 15 V or 5 V Operation, TC < 50 ppm/C I2C Compatible, TC < 50 ppm/C Nonvolatile Memory, Direct Program, I/D, 6 dB Settability No Rollover, Stereo, Pwr-On-Reset, TC < 50 ppm/C Full ac Specs, nA Shutdown Current Full ac Specs, Dual Supply, Pwr-On-Reset, SDO Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Nonvolatile Memory, Direct Program, TC < 50 ppm/C I2C Compatible, TC < 50 ppm/C 5 V to 15 V or 5 V Operation, TC < 50 ppm/C
AD5220 AD7376
1 1
5.5 15, +28
UP/DOWN 3-Wire
10, 50, 100 10, 50, 100, 1000 10, 50
128 128
40 100
PDIP, SO-8, SOIC-8 PDIP-14, SOL-16, TSSOP-14 SOIC-10 SO-8 TSSOP-14
AD5200 AD8400 AD5260
1 1 1
3, +5.5 5.5 5, +15
3-Wire 3-Wire 3-Wire
256
40 5 60
1, 10, 50, 100 256 20, 50, 200 256
AD5241 AD5231
1 1
3, +5.5 2.75, +5.5
2-Wire 3-Wire
10, 100, 1000 10, 50, 100
256 1024
50 20
SO-14, TSSOP-14 TSSOP-16
AD5222
2
3, +5.5
UP/DOWN
10, 50, 100, 1000 1, 10, 50, 100 10, 50, 100
128
80
SO-14, TSSOP-14 PDIP, SO-14, TSSOP-14 TSSOP-14
AD8402 AD5207
2 2
5.5 3, +5.5
3-Wire 3-Wire
256 256
5 40
AD5232
2
2.75, +5.5
3-Wire
10, 50, 100
256
20
TSSOP-16
AD5235
2
2.75, +5.5
3-Wire
25, 250
1024
20
TSSOP-16
AD5242 AD5262
2 2
3, +5.5 5, +15
2-Wire 3-Wire
10, 100, 1000 20, 50, 200
256 256
50 60
SO-16, TSSOP-16 TSSOP-16
AD5203 AD5233
4 4
5.5 2.75, +5.5
3-Wire 3-Wire
10, 100 10, 50, 100
64 64
5 20
PDIP, SOL-24, Full ac Specs, nA TSSOP-24 Shutdown Current TSSOP-24 Nonvolatile Memory, Direct Program, I/D, 6 dB Settability
AD5204 AD8403 AD5206
*
4 4 6
3, +5.5 5.5 3, +5.5
3-Wire 3-Wire 3-Wire
10, 50, 100
256
60 5 60
PDIP, SOL-24, Full ac Specs, Dual TSSOP-24 Supply, Pwr-On-Reset PDIP, SOL-24, Full ac Specs, nA TSSOP-24 Shutdown Current PDIP, SOL-24, Full ac Specs, Dual TSSOP-24 Supply, Pwr-On-Reset
1, 10, 50, 100 256 10, 50, 100 256
For the most current information on Digital Potentiometers, check the website at: www.analog.com/DigitalPotentiometers
-22-
REV. 0
AD5233
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Thin Surface Mount TSSOP Package (RU-24)
0.311 (7.90) 0.303 (7.70)
24
13
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 12
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
REV. 0
-23-
-24-
C02794-0-3/02(0)
PRINTED IN U.S.A.

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