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Ordering number : EN*4965
CMOS LSI
LC75741E, 75741W
1/2 Duty VFD Driver for Frequency Displays
Preliminary Overview
The LC75741E and LC75741W are 1/2 duty VFD drivers for use in electronic tuning frequency displays controlled by a microcontroller. These products can directly drive VFD displays with up to 106 segments.
Package Dimensions
unit: mm 3159-QFP64E
[LC75741E]
Functions and Features
* 106 segment outputs * Noise reduction circuit built into the output drivers. * Display and dimmer data communication with the controller using the CCB* format. * High generality, since display data is displayed directly without decoder intervention * All segments can be turned off with the BLK pins. * Package: QFP64E (LC75741E) SQFP64 (LC75741W) Note: * CCB is Sanyo's original bus format with address management for all Sanyo products. unit: mm 3190-SQFP64
[LC75741W]
SANYO: QIP64E
SANYO: SQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
52595TH (OT) No. 4965-1/10
LC75741E, 75741W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VFL max VIN1 VIN2 VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg VDD VFL DI, CL, CE, BLK OSCI S1 to S53, G1, G2 OSCO S1 to S53 G1, G2 Ta = 85C Conditions Ratings -0.3 to +6.5 -0.3 to +21.0 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VFL + 0.3 -0.3 to VDD + 0.3 5 60 400 (LC75741E) 300 (LC75741W) -40 to +85 -50 to +150 Unit V V V V V V mA mA mW mW C C
Input voltage
Output voltage
Output current
Allowable power dissipation Operating temperature Storage temperature
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Supply voltage Symbol VDD VFL VIH1 VIH2 VIL1 VIL2 fOSC ROSC COSC toL toH tds tdh tcp tcs tch tc VDD VFL DI, CL, CE, BLK OSCI DI, CL, CE, BLK OSCI OSCI, OSCO OSCI, OSCO OSCI, OSCO CL: Figure 1 CL: Figure 1 DI, CL: Figure 1 DI, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 BLK, CE: Figure 3 0.5 0.5 0.5 0.5 0.5 0.5 0.5 10 Conditions min 4.5 8 0.8 VDD 0.7 VDD 0 0 0.4 1.6 20 47 typ 5.0 12 max 5.5 18 5.5 VDD 0.2 VDD 0.3 VDD 3.0 Unit V V V V V V MHz k pF s s s s s s s s
Input high level voltage
Input low level voltage Guaranteed oscillator range Recommended external resistance Recommended external capacitance Low level clock pulse width High level clock pulse width Data setup time Data hold time CE wait time CE setup time CE hold time BLK switching time
Electrical Characteristics in the Allowable Operating Ranges
Parameter Input high level current Input low level current Symbol IIH IIL VOH1 Output high level voltage VOH2 VOH3 VOH4 Output low level voltage Oscillator frequency Hysteresis voltage Current drain VOL1 VOL2 fOSC VH IDD Conditions DI, CL, CE, BLK, OSCI: VI = 5.5 V DI, CL, CE, BLK, OSCI: VI = 0 V S1 to S53: IO = 2 mA G1, G2: IO = 25 mA G1, G2: IO = 50 mA OSCO: IO = 0.5 mA S1 to S53, G1, G2: IO = -5 A, Ta = 25C OSCO: IO = -0.5 mA ROSC = 20 k, COSC = 47 pF DI, CL, CE, BLK Output open: fOSC = 1.6 MHz 1.6 0.1 VDD 10 -5 VFL - 0.6 VFL - 0.6 VFL - 1.3 VDD - 2.0 0.25 0.5 2.0 min typ max 5 Unit A A V V V V V V MHz V mA
No. 4965-2/10
LC75741E, 75741W 1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 1 Pin Assignment
No. 4965-3/10
LC75741E, 75741W Block Diagram
Pin Functions
Pin VFL VDD VSS OSCI, OSCO Pin No. 3 60 57 59 58 I/O -- -- -- I/O Function Driver block power supply. A voltage of between 8.0 and 18.0 V must be supplied. Logic block power supply. A voltage of between 4.5 and 5.5 V must be supplied. Power supply. Must be connected to ground. Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor at these pins. Display off control input BLK = low (VSS): Display off (S1 to S53, G1 and G2 = low) BLK = high (VDD): Display on Note that serial data transfers are still allowed when display is turned off using this pin. Serial data transfer inputs. Connect to the system microcontroller. CL: Synchronization clock DI: Transfer data CE: Chip enable Digit outputs. The frame frequency fO is fOSC/4096 Hz. Segment outputs for displaying the display data transferred by serial data input.
BLK
61
I
CL DI CE G1, G2 S1 to S53
63 64 62 1, 2 56 to 4 O O I
No. 4965-4/10
LC75741E, 75741W Serial Data Transfer Format 1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 2 CCB address: DM0 to DM9: Transfer 00100001B as shown in Figure 2. Dimmer data This data controls the duty of the G1 and G2 digit output pins, and consists of 10 bits with DM0 being the LSB. Note that the intensity of the display can be adjusted by controlling the duty of the G1 and G2 digit output pins. SD1 to SD53: Display data for the G1 digit output pin. SDn (n = 1 to 53) = 1: On SDn (n = 1 to 53) = 0: Off SD54 to SD106: Display data for the G2 digit output pin. SDn (n = 54 to 106) = 1: On SDn (n = 54 to 106) = 0: Off
No. 4965-5/10
LC75741E, 75741W Correspondence between Display Data (SD1 to SD106) and Segment Output Pins
Segment output pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 G1 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 G2 SD54 SD55 SD56 SD57 SD58 SD59 SD60 SD61 SD62 SD63 SD64 SD65 SD66 SD67 SD68 SD69 SD70 SD71 SD72 SD73 SD74 SD75 SD76 SD77 SD78 SD79 SD80 Segment output pin S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 G1 SD28 SD29 SD30 SD31 SD32 SD33 SD34 SD35 SD36 SD37 SD38 SD39 SD40 SD41 SD42 SD43 SD44 SD45 SD46 SD47 SD48 SD49 SD50 SD51 SD52 SD53 G2 SD81 SD82 SD83 SD84 SD85 SD86 SD87 SD88 SD89 SD90 SD91 SD92 SD93 SD94 SD95 SD96 SD97 SD98 SD99 SD100 SD101 SD102 SD103 SD104 SD105 SD106
For example, the table below lists the segment output states for the S11 segment output pin.
Display data SD11 0 0 1 1 SD64 0 1 0 1 Segment output pin (S11) state Both segments for the G1 and G2 digit output pins are off Segment for the G2 digit output pin is on Segment for the G1 digit output pin is on Both segments for the G1 and G2 digit output pins are on
BLK and the Display Control Since the LSI internal data (SD1 to SD106 and DM0 to DM9) is undefined when power is first applied, the display is off (S1 to S53, G1 and G2 = low) by setting the BLK pin low at the same time as power is applied. Then, meaningless display at power-on can be prevented by transferring all 144 bits of serial data from the controller while the display is off and setting BLK pin high after the transfer completes. (See Figure 3.) Power Supply Sequence Observe the following sequences when turning the power on and off. (See Figure 3.) * Power on: Logic block power supply (VDD) on Driver block power supply (VFL) on * Power off: Driver block power supply (VFL) off Logic block power supply (VDD) off
No. 4965-6/10
LC75741E, 75741W
Figure 3 Output Waveforms (S1 to S53)
No. 4965-7/10
LC75741E, 75741W Relation between Segment and Digit Outputs
Figure 4 Description 1. Consider the examples shown in Figure 4, where data is set up so that the segment outputs S1 to S53 output a low level on the G1 digit output timing and a high level on the G2 digit output timing. (Here, the G2 side being lighted) 2. The waveforms for G1 and G2 in example 1 are output when the 10 bits of dimmer data (DM0 to DM9) are set to 3FEH. The relation between t1 and the oscillator frequency fOSC is: t1 = 2/fOSC For example, if fOSC is 1.6 [MHz]: t1 = 2/1.6 [MHz] = 1.25 [s]. Note that t1 and t2 will be the same period in example 1. 3. The waveforms for G1 and G2 in example 2 are those when the dimmer data (DM0 to DM9) are set to a smaller value. Although the time t1, which is from the point where digit output falls to segment output changes, does not change, the time t2, which is from the point where segment output changes to the time the digit output rises, becomes longer. When the dimmer data (DM0 to DM9) are set to 0FFH and fOSC is 1.6 [MHz], the frame frequency fframe = 1/(t3 x 2) = fOSC/4096 = 391 [Hz], and t3 = 1.28 [ms].
Therefore, t2 =
(1.28 [ms] - 1.25 [s] x2) x (3FFH - 0FFH) = 0.96 [ms]. 1023
4. When the dimmer data (DM0 to DM9) are set to an even smaller value, the time t2, which is from the point where segment output changes to the time the digit output rises, becomes even longer, as in example 3. Note that t1 does not change here, either.
No. 4965-8/10
LC75741E, 75741W Sample Application Circuit
Usage Notes 1. Segment and digit waveforms
Figure 5 The segment waveform is distorted by the wiring of the VFD panel used, and furthermore, in the case of being used with essentially no dimming as in the digit waveform 1, as shown in Figure 5, the VFD panel glow dimly. By carefully considering the segment waveform, it can be seen that this problem can be resolved by applying an adequate amount of dimming, as shown in digit waveform 2. When fOSC is 1.6 [MHz], we recommend using 10 bits of dimmer data in the range 000H to 3E0H. 2. Serial data transfer Since display data is transferred in two operations as shown in Figure 2, we recommend that all display data be transferred within 30 [ms] to prevent degradation of the visual quality of the displayed image.
No. 4965-9/10
LC75741E, 75741W
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of May, 1995. Specifications and information herein are subject to change without notice. PS No. 4965-10/10

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