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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
PM5342
SPECTRA-155
SPECTRA-155 PROGRAMMER'S REFERENCE
APPLICATION NOTE
ISSUE 1: MARCH 1999
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
REVISION HISTORY Issue No. 1 Issue Date Mar 1999 Details of Change Document created.
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
CONTENTS 1 2 3 REFERENCES ......................................................................................... 1 BACKGROUND ........................................................................................ 2 ALARM, OVERHEAD, AND PAYLOAD INSERTION................................. 3 3.1 3.2 3.3 4 ALARM INSERTION ...................................................................... 4 OVERHEAD INSERTION............................................................... 6 TELECOM PAYLOAD PROCESSING.......................................... 15
INTERRUPTS ......................................................................................... 17 4.1 INTERRUPT OVERVIEW............................................................. 17 4.1.1 INTERRUPTS AND INTERRUPT ENABLES .................... 17 4.1.2 TOP-LEVEL INTERRUPTS ............................................... 18 4.1.3 AUXILIARY INTERRUPTS ................................................ 18 4.2 INTERRUPT CROSS-REFERENCE............................................ 19
5
SONET AND SDH CONFIGURATION.................................................... 29
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
LIST OF FIGURES FIGURE 1 - INTERRUPT GENERATION LOGIC............................................. 17 FIGURE 2 - INTERRUPT CROSS-REFERENCE LEGEND ............................ 19
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 - TRANSMIT ALARM INSERTION.................................................... 4 - DROP ALARM INSERTION ........................................................... 4 - ALARM DESCRIPTIONS ............................................................... 6 - TRANSMIT OVERHEAD INSERTION............................................ 7 - CONSEQUENT RDI-P INSERTION ............................................. 12 - DROP OVERHEAD INSERTION.................................................. 13 - TRANSMIT PAYLOAD PROCESSING ......................................... 15 - DROP PAYLOAD PROCESSING ................................................. 15 - INTERRUPT CROSS-REFERENCE ............................................ 19
TABLE 10 - SDH AND SONET CONFIGURATION VALUES........................... 29
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
1
REFERENCES * Bell Communications Research, Generic Requirements GR-253-CORE - SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995. ITU, Recommendation G.707 - Network Node Interface For the Synchronous Digital Hierarchy, 03/1996. ITU, Recommendation G.783 - Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks, 04/1997. PMC-Sierra PMC-970133 - PM5342 SPECTRA-155 SONET/SDH Payload Extractor Aligner Data Sheet, Issue 5, August 1998.
* * *
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
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BACKGROUND PMC-Sierra's PM5342 SONET/SDH Payload Extractor/Aligner (SPECTRA-155) terminates the transport and path overhead of STS-1 (STM-0/AU-3) and STS-3/3c (STM-1/AU-3/AU-4) streams. This document provides a convenient programmers reference for the SPECTRA155. Although most of the information in this document can also be found in the SPECTRA datasheet, the information is distributed between pin, functional, and register descriptions. This document presents the same information in a reference form that spans functional blocks to quickly answer many software and hardware questions. Although every effort has been taken to ensure that this document is consistent with the datasheet, some errors may occur. Where there are discrepancies with this document, the datasheet and datasheet errata (if any) will take precedence. In this document, the term, "SPECTRA," is used interchangeably with the full product name, "SPECTRA-155."
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
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ALARM, OVERHEAD, AND PAYLOAD INSERTION The SPECTRA-155 is capable of modifying the outgoing transmitted and dropped datastreams in many different ways. Alarms, overhead, and payload are affected by register configuration, pin states, and by detected conditions such as AIS. The following sections summarize the many ways that transmitted and dropped datastreams may be affected by the SPECTRA. SPECTRA is also capable of monitoring and reporting the status of the incoming received and added datastreams. The monitoring and reporting functions are not described in the following sections. Descriptions of alarm, overhead, and payload insertion adhere to several conventions: * * The word "Default" in a table row indicates that the row corresponds to the power-up register configuration of the SPECTRA. Register bit names are prefixed with "r", and pin names are prefixed with "p". For example, "rFTPTR" refers to the FTPTR bit in register 131, 171 or 1B1h. Due to space limitations, register addresses cannot be listed in the table and must be determined from the datasheet. It is intended that this application note will be used in conjunction with a soft copy of the SPECTRA documentation (available from http://www.pmc-sierra.com) for performing text searches on register bit names. Note that the SPECTRA datasheet contains multiple instances of many bit names. In most cases, the duplication is due to replicated functional blocks. For example, there are six instances of the H4BYP bit: three in the RTAL blocks (register 128h,...) and three in the TTAL blocks (register 140h,...). The appropriate instance must be determined from context. * A "n" replaces numbers in replicated register bits. For example, "rTPAIS_EN#n" could refer to the TPAIS_EN#1, TPAIS_EN#2, or TPAIS_EN#3, depending on the STS-1 (AU-3) of interest. Logical operations are indicated by the characters "!", "&", and "+", which represent logical NOT, AND, and OR, respectively. Braces indicate a detected condition. For example, {RX LOP-P} indicates the detection of loss-of-pointer in the receive datastream, while {RCP SENDLAIS} indicates that the SENDLAIS bit on the ring control port is active.
* *
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Abbreviations describe the source of the detected condition: ADD (add bus), RCP (ring control port), and RX (receive line interface). 3.1 Alarm Insertion The following tables describe how the SPECTRA-155 can be configured to insert alarms in the transmit or drop datastreams (Table 1 and Table 2, respectively). Each alarm may be caused by several different conditions. Within the SPECTRA, all of the possible causes are OR'ed together--satisfying any one condition is sufficient to raise the alarm. Table 3 lists all alarms and describes their effect on the datastream. In general, alarms have precedence over overhead insertion from any other source. Table 1
Alarm LOS AIS-L
- Transmit Alarm Insertion
Condition rDLOS rLAIS !rRCP & pTLAIS {RCP SENDLAIS} & rRCP & rRINGEN Comments
AIS-P
pDTPAIS & rTPAIS_EN#n {ADD AIS-P} & rPAISPAIS {ADD LOP-P} & rLOPPAIS {ADD AISC-P} & rPAISCONPAIS {ADD LOPC-P} & rLOPCONPAIS rPAIS {TTAL elastic store error} & rESAIS {ADD ISF} & rTTCTE AIS Asserted for 3 Frames Affected by rFISF
AIS-V
{ADD LOM} & rLOMTUAIS rITUAIS
AIS-V (DS-3)
pSMODE[2:0]=110 & (pDS3TAISn + rDS3AISGEN)
Table 2
Alarm AIS-P (via RLOP)
- Drop Alarm Insertion
Condition !rRCP & pRLAIS {RX AIS-L} & rALLONES Comments
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Alarm AIS-P (cont'd)
Condition {RX TIU-S} & rALLONES & rRTIUINS & rAUTOSTIU1 {RX TIU-S} & rALLONES & rRTIUINS & rAUTOSTIU2 {RX TIM-S} & rALLONES & rRTIMINS {RX LOS} & rALLONES & rLOSINS {RX LOF} & rALLONES & rLOFINS {RX SF} & rALLONES & rSFINS {RX SD} & rALLONES & rSDINS
Comments Mode 1 TIU-S Mode 2 TIU-S
AIS-P
pDTPAISn & !rTPAIS_EN {RX AIS-P} {RX LOP-P} & rLOPPAIS {RX AISC-P} & rPAISCONPAIS {RX LOPC-P} & rLOPCONPAIS {RX TIM-P} & rTIMPAIS {RX TIU-P} & rTIUPAIS & rAUTOPTIU1#n {RX TIU-P} & rTIUPAIS & rAUTOPTIU2#n {RX SLM-P} & rPSLMPAIS {RX SLU-P} & rPSLUAIS rIPAIS {RTAL elastic store error} & rESAIS {RX_ISF} & rTTCTE AIS Asserted for 3 Frames Affected by rFISF Default Mode 1 TIU-P Mode 2 TIU-P Default Default Default
AIS-TC AIS-V
rOTCTE & rISF {RX LOM} & rLOMTUAIS rITUAIS Default
AIS-V (DS3)
pDS3RAIS rDS3AISGEN {RX TIM-P} & rTIMDS3AIS {RX TIU-P} & rTIUDS3AIS & rAUTOPTIU1#n {RX TIU-P} & rTIUDS3AIS & rAUTOPTIU2#n {RX LOP-P} & rLOPDS3AIS {RX SLM-P} & rPSLMDS3AIS {RX SLU-P} & rPSLUDS3AIS ({RX LOS} + {RX LOF} + {RX AIS-L}) & rALMDS3AIS Mode 1 TIU-P Mode 2 TIU-P
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Table 3 Alarm AIS-L AIS-P AIS-TC
- Alarm Descriptions Description Line AIS (MS-AIS). All ones in line overhead, H1 H2 pointer, path overhead, and payload. Path AIS (HP-AIS). All ones in H1 H2 pointer, path overhead, and payload. Tandem connection AIS. All ones in payload. IEC field in Z5 byte indicates ISF (1111b). Tandem connection data link remains active. Error-free path BIP inserted in the B3 byte. Tributary AIS. All ones in payload (but not path overhead). Effectively, this appears as AIS for all tributaries. Tributary AIS. All ones in payload for the affected DS-3. This type of AIS is only applicable when the SPECTRA is operating in DS-3 mode. Loss-of-signal. Transmit all zeros.
AIS-V AIS-V (DS-3)
LOS
3.2
Overhead Insertion SPECTRA is capable of modifying the overhead of the transmitted and dropped datastreams in many different ways. The following tables describe how transport and path overhead bytes are inserted into the transmitted data stream (Table 4) or the dropped data stream (Table 6). For each overhead byte location, the tables describe the inserted value and the condition or conditions under which that value will be inserted. See the Appendix for a brief overview of overhead byte functions. In some overhead bytes, bits are allocated for specific functions. For example, bits 1-4 of the G1 path overhead byte are allocated for the REI-P function. Overhead insertion functions that apply only to allocated bits are indicated separately in the tables. If the table does not identify any allocated bits, then the overhead insertion function applies to the entire overhead byte. Values inserted into overhead bytes may take many forms: constants (e.g. "F6h" or "110b"); register contents (e.g. "reg 1Ah"); all ones or all zeros, according to the value of a single register bit or pin (e.g. "rUNUSED_V"); a default value that has been XORed with an error mask (e.g. "mask FFh"); or streamed in from a serial overhead interface pin (e.g. "pTTOH"). Some special bytes may have other
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
values inserted into them; refer to the bit descriptions in the SPECTRA datasheet for more information. Overhead insertion conditions are generally listed in order of increasing priority. The bottom-most insertion condition usually will take priority over any conditions above it. For example, in the transmit direction, if the TTOHEN pin is active then the D1-D3 overhead bytes will be inserted from the TTOH pin, independent of the state of any other register bits or pins. Some exceptions to this rule occur for the more complicated overhead bytes, such as G1. In these cases, insertion conditions are expanded to describe the full logical hierarchy of insertion values. Some overhead insertion conditions are left blank, indicating that the value will be inserted if all other insertion conditions are false. For example, in the transmit direction, B1 will be calculated based on the previous frame's data if register bit DBIP8 and pin TTOHEN are both false. Table 4
Overhead Byte A1, A2 Bit(s) F6h, 28h 76h, 28h pTTOH J0 01h section trace buffer pTTOH Z0 02h, 03h reg 1Bh pTTOH B1 calculate mask FFh mask pTTOH E1 pTSOW pTOH pTTOH F1 pTSUC pTOH pTTOH D1-D3 rTDLVAL rTOHSEL[2:0]=001 pTTOHEN rTDLSEL rTOHSEL[2:0]=000 pTTOHEN Default rDBIP8 pTTOHEN !rDFP rDFP pTTOHEN !rSTEN rSTEN pTTOHEN & !rSTEN !rZ0INS rZ0INS pTTOHEN Default Error Mask Error Mask Default Default Default Default
- Transmit Overhead Insertion
Value Condition Comments
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Overhead Byte D1-D3 (cont'd) H1, H2 pointer Bit(s)
Value
Condition
Comments
pTSLD pTTOH calculate + justification
!rTDLSEL pTTOHEN
Default
Default rDOPJ1 & !rDOPJ0 Force justification every 4th frame.
- justification
!rDOPJ1 & rDOPJ0
Force justification every 4th frame.
reg 136h, 135h,...
rFTPTR
Pointer substitution without NDF.
NDF
reg 136h,...
{TTAL discontinuous pointer change} + rNDF
SS
reg 136h,... mask pTTOH pTTOHEN rTMODE[1:0]=11 pTTOHEN
Default Error Mask
H1, H2 Concat H3
reg 13Fh, 13Eh mask pTTOH insert pTTOH
Error Mask Default
pTTOHEN Default rDB2 pTTOHEN !rTAPSTAP & rRCP !rTAPSTAP & rAPSREG !rTAPSTAP & !rAPSREG & rTOHSEL[2:0]=100 Default Error Mask Error Mask filtered
B2
calculate mask FFh mask pTTOH
K1, K2
ring control port reg 06h, 07h pTOH
pTTOH pTAD RDI-L 110b 110b 110b 110b
!rTAPSTAP & pTTOHEN rTAPSTAP rLRDI pTLRDI & !rRCP {RX AIS-L} & !rRCP & rLAISINS {RX TIU-S} & !rRCP & rRTIUINS & rAUTOSTIU1 Default Mode 1 TIU-S
110b
{RX TIU-S} & !rRCP & rRTIUINS & rAUTOSTIU2
Mode 2 TIU-S
110b
{RX TIM-S} & !rRCP & rRTIMINS
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Overhead Byte K1, K2 (cont'd) Bit(s) RDI-L (cont'd)
Value
Condition
Comments
110b 110b 110b 110b 110b
{RX LOS} & !rRCP & rLOSINS {RX LOF} & !rRCP & rLOFINS {RX_SF} & !rRCP & rSFINS {RX SD} & !rRCP & rSDINS RCP_SENDLRDI & rRCP & rRINGEN !rTDLSEL rTDLSEL pTTOHEN
Default Default
D4-D12
pTLD pTSLD pTTOH
Default
S1
reg 1Ah pTTOH pTTOHEN !rUNUSED_EN rUNUSED_EN pTTOHEN !rUNUSED_EN rUNUSED_EN pTTOHEN !rAUTOLREI & !rRINGEN rRCP & rRINGEN rAUTOLREI & !rRINGEN & !rBLOCKBIPO rAUTOLREI & !rRINGEN & rBLOCKBIPO pTTOHEN
Default
Z1
00h rUNUSED_V pTTOH
Default
Z2
00h rUNUSED_V pTTOH
Default
M0,M1
REI-L
00h RCP LREI RX B2 count RX B2 pTTOH
Default
E2
pTLOW pTOH pTTOH rTOHSEL[2:0]=010 pTTOHEN !rUNUSED_EN rUNUSED_EN pTTOHEN !rNAT_EN rNAT_EN pTTOHEN !rTDIS & !rTPTBnEN !rTDIS & rTPTBnEN
Default
TOH Unused (not Z1, Z2)
00h rUNUSED_V pTTOH
Default
TOH National (except Z0)
00h rNAT_V pTTOH
Default
J1
reg 137h,... SPTB
Default
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Overhead Byte J1 (cont'd) Bit(s)
Value
Condition
Comments
ADD passthrough rADDUEV pTPOH
rTDISn & !rADDUEn rTDISn & rADDUEn !rTPTBEN & pTPOHEN !rTDISn Default. Affected by rEXCFS.
B3
calculated
calculated w.r.t. Z5 mask FFh ADD passthrough rADDUEV pTPOH
!rTDISn & rTTCTE !rTDISn & rDB3 rTDISn & !rADDUEn rTDISn & rADDUEn rTDIS & pTPOHEN
Affected by rEXCFS. Error Mask
Corrupts B3 unpredictably.
mask pTPOH C2 reg 138h,... ADD passthrough rADDUEV pTPOH G1 ADD passthrough rADDUEV pTPOH REI-P 0000b rPREI[3:0]
!rTDIS & pTPOHEN !rTDISn rTDISn & !rADDUEn rTDISn & rADDUEn pTPOHEN rTDISn & !rADDUEn rTDISn & rADDUEn pTPOHEN
Error Mask Default
Default !rTDISn & !pTPOHEN Inserts REI count in next available G1.
RX B3 count
!rTDISn & rRXSEL[1:0]=00 & rAUTOPREI & !rBLKBIPO
RX B3
!rTDISn & rRXSEL[1:0]=00 & rAUTOPREI & rBLKBIPO
pTAD ADD passthrough 0000b RDI-P RPOP
!rTDISn & rRXSEL[1:0]=01 !rTDISn & rRXSEL[1:0]=10 !rTDISn & rRXSEL[1:0]=11 rEPRDIEN & rEPRDISRC & rRXSEL[1:0]=00
pTAD
rEPRDIEN & rEPRDISRC & rRXSEL[1:0]=01
ADD passthrough
rEPRDIEN & rRXSEL[1:0]=10
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Overhead Byte G1 (cont'd) Bit(s) RDI-P (cont'd)
Value
Condition
Comments
000b
rEPRDIEN & rEPRDISRC & rRXSEL[1:0]=11
pTPOH RDI-P (bit 5) rPRDI
pTPOHEN & !rEPRDIEN (!pTPOHEN & !rEPRDIEN & rRXSEL[1:0]=11) + (rEPRDIEN & !rEPRDISRC & !(rRXSEL[1:0]=10))
rPRDI + RPOP
!pTPOHEN & !rEPRDIEN & rRXSEL[1:0]=00
Default
rPRDI + pTAD
!pTPOHEN & !rEPRDIEN & rRXSEL[1:0]=01
rPRDI + ADD passthrough RDI-P (bit 6) RDI-P (bit 7) bit 8 F2 rG1[0] reg 13Ah,... ADD passthrough rADDUEV pTPOH H4 TTAL mask FFh ADD passthrough rADDUEV mask pTPOH F3/Z3 reg 13Bh,... ADD passthrough rADDUEV pTPOH K3/Z4 reg 13Ch,... ADD passthrough rADDUEV pTPOH rEPRDI7 rEPRDI6
!pTPOHEN & !rEPRDIEN & rRXSEL[1:0]=10 (!pTPOHEN & !rEPRDIEN) + (rEPRDIEN & !rEPRDISRC & !(rRXSEL[1:0]=10)) (!pTPOHEN & !rEPRDIEN) + (rEPRDIEN & !rEPRDISRC & !(rRXSEL[1:0]=10)) !pTPOHEN !rTDISn rTDISn & !rADDUEn rTDISn & rADDUEn pTPOHEN !rTDISn & !rH4BYP !rTDISn & rDH4 rTDISn & rH4BYP & !rADDUEn rTDISn & rH4BYP & rADDUEn pTPOHEN !rTDISn rTDISn & !rADDUEn rTDISn & rADDUEn pTPOHEN !rTDISn rTDISn & !rADDUEn rTDISn & rADDUEn pTPOHEN Default Error Mask Default Default Error Mask Default Default
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Overhead Byte N1/Z5 Bit(s)
Value
Condition
Comments
reg 13Dh,... ADD passthrough rADDUEV IEC TCDL 0000b 0000b pTPOH
!rTDISn rTDISn & !rADDUEn rTDISn & rADDUEn rTTCTE rTTCTE pTPOHEN
Default
The RPOP will source RDI-P values according to the consequent actions that are configured according to Table 5. Table 5
RDI-P Value (G1 bits 5-7) 1xxb 1xxb 1xxb 1xxb 1xxb 1xxb 1xxb 1xxb 1xxb 1xxb x10b x10b x10b x01b x01b x10b x01b x01b x10b x01b {RX TIM-P} & rTIMPRDI {RX TIU-P} & rAUTOPTIU1#n rTIUPRDI {RX TIU-P} & rAUTOPTIU2#n & rTIUPRDI {RX LOP-P} & rLOPPRDI {RX LOPC-P} & rLOPCONPRDI {RX SLM-P} & rPSLMPRDI {RX AIS-P} & rPAISPRDI {RX AISC-P} & rPAISCONPRDI {RX UNEQ-P} & rUNEQPRDI ({RX LOS} + {RX LOF} + {RX AIS-L}) & rALMPRDI {RX TIM-P} & rTIMEPRDI & rEPRDI_EN {RX TIU-P} & rAUTOPTIU1#n & rTIUEPRDI & rEPRDI_EN {RX TIU-P} & rAUTOPTIU2#n & rTIUEPRDI & rEPRDI_EN {RX LOP-P} & rNOLOPEPRDI & rEPRDI_EN {RX LOPC-P} & rNOLOPCONEPRDI & rEPRDI_EN {RX SLM-P} & rPSLMEPRDI & rEPRDI_EN {RX AIS-P} & rNOPAISEPRDI & rEPRDI_EN {RX AISC-P} & rNOPAISCONEPRDI & rEPRDI_EN {RX UNEQ-P} & rUNEQEPRDI & rEPRDI_EN ({RX LOS} + {RX LOF} + {RX AIS-L}) & rNOALMEPRDI & Mode 1 TIU-P Mode 2 TIU-P Default Mode 1 TIU-P Mode 2 TIU-P Default Default Default Default Default Default
- Consequent RDI-P Insertion
Condition Comment
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RDI-P Value (G1 bits 5-7)
Condition
Comment
rEPRDI_EN
Notes: * * * When no error conditions are present, the RPOP will generate a nonenhanced RDI-P code of 0xxb and an enhanced RDI-P code of x01b. The assertion time for all of the above RDI-P consequent actions is affected by the PERSIST register bit (reg 130, 170, 1B0h). Hierarchy of enhanced RDI-P not shown. When multiple enhanced RDI-P conditions occur simultaneously, the "x01" indication has priority over "x10".
Table 6
Overhead Byte A1, A2 J0 Z0 B1 E1 F1 D1-D3 H1, H2
- Drop Overhead Insertion
Value Bit(s) 00h 00h 00h 00h 00h 00h 00h pointer calculate + justification rDOPJ1 & !rDOPJ0 Default Default Default Default Default Default Default Default Force justification every 4th frame. - justification !rDOPJ1 & rDOPJ0 Force justification every 4th frame. hold last value NDF SS 1001b 00b 10b rOTCTE & ({RX LOP} + {RX AIS}) rDLOP !rSSS rSSS Default Default Default Condition Comments
H3 B2
insert 00h
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Overhead Byte K1 K2 D4-D12 S1 Z1 Z2 M0 M1 E2 TOH Unused TOH National J1 B3 Bit(s)
Value
Condition
Comments
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Default Default Default Default Default Default Default Default Default Default
00h
Default
RX passthrough RX passthrough calculated !rTTCTE rTTCTE
Default Default Reflects changes made to Z5.
C2 G1 F2 H4
RX passthrough RX passthrough RX passthrough RX passthrough 00h rH4BYP & pSMODE[2:0]=[000, 001, 010] rH4BYP & pSMODE[2:0]=[011, 100, 101, 110] FC, FD, FE, FFh invert FFh !rH4BYP rDH4 rH4AISB & {RX AIS-P}
Default Default Default
Default Force inverted H4.
F3/Z3 K3/Z4 N1/Z5 IEC
RX passthrough RX passthrough RX passthrough 0000b RX B3 count 1111b !rOTCTE & !rTTCTE !rOTCTE & rTTCTE rOTCTE & !rTTCTE rOTCTE & !rTTCTE & (rISF + {RX LOP-P} + {RX AIS-P}) ???? rOTCTE & rTTCTE
Default Default Default
Illegal
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Overhead Byte Bit(s) TCDL
Value
Condition
Comments
RX passthrough 0000b 1111b RX passthrough
!rOTCTE & !rTTCTE !rOTCTE & rTTCTE rOTCTE & !rTTCTE & !rTCDLT rOTCTE & !rTTCTE & rTCDLT rOTCTE & rTTCTE pRTCENn
Default
N1/Z5 (cont'd)
TCDL (cont'd)
???? pRTCOHn
Illegal
3.3
Telecom Payload Processing In telecom bus mode, the SPECTRA-155 has limited capability to affect the payload data. Transmit and drop payload processing are described in Table 7 and Table 8, respectively. Table 7
Payload Location Fixed Stuff
- Transmit Payload Processing
Value 00h ADD passthrough 00h Condition rCLRFS !rCLRFS (pSMODE[2:0]=[011, 100] & !rTDM_FSEN) + (pSMODE[2:0]=101 & rGAPFS) data DS-3 data pSMODE[2:0]=[011, 100] & rTDM_FSEN pSMODE[2:0]=101 & !rGAPFS !rADDUEn rADDUEn Default Comment
STS-1/AU-3 Payload
ADD passthrough rADDUEV
Table 8
Payload Location Fixed Stuff
- Drop Payload Processing
Value 00h RX passthrough 00h Condition rCLRFS !rCLRFS (pSMODE[2:0]=[011, 100, 101] & !rRDMFSEN) + (pSMODE[2:0]=110 & rGAPFS)) data pSMODE[2:0]=[011, 100, 101] & rRDMFSEN Default Comment
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Payload Location Fixed Stuff (cont'd)
Value DS-3 data
Condition pSMODE[2:0]=110 & !rGAPFS
Comment
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
4
INTERRUPTS The SPECTRA-155 has a single interrupt pin (INTB) which can reflect the status of over 250 independent interrupt sources. This section describes the interrupt hierarchy and then provides a quick cross-reference of all SPECTRA interrupt sources.
4.1
Interrupt Overview Figure 1 shows a portion of the interrupt generation logic. This diagram shows the contribution of the loss-of-signal (LOS) alarm to interrupt generation. Figure 1 - Interrupt Generation Logic
LO S E (A u x) LO S I (A u x) RSO PE RSO PI IN T B LO SE LO S I O O FE O O FI

LO SV
... ...
At the root of each interrupt is an interrupt source. Often, the status of the interrupt source will be reflected with a value bit, or "V" bit. For example, the LOSV bit (reg 011h) reflects the current status of the loss-of-signal detector. When LOS is detected, the LOSV bit will be 1; otherwise, LOSV will be 0. The "V" bits are "real time" and are not latched. Many interrupt sources do not have "V" bits but are reported in other ways. 4.1.1 Interrupts and Interrupt Enables Every interrupt source has an associated interrupt status bit, or "I" bit. The "I" bit is set and latched when the interrupt event occurs, and will be cleared only after processor intervention. Depending on the "I" bit, the interrupt will be cleared either after a CPU read from the register, or after a CPU write of "1" to the interrupt bit. In Figure 1, the LOSI bit (reg 011h) is the interrupt status bit associated with the LOS detector. When the LOS detector changes state (i.e. when LOSV changes value), LOSI will be set. LOSI will be cleared only after the CPU reads from register 011h.
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... ...
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PM5342 SPECTRA-155
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To filter irrelevant interrupts, every "I" bit has an associated interrupt enable bit, or "E" bit. When the "E" bit is set, the associated "I" bit will contribute to the INTB pin or to a top level interrupt status bit (more about top-level interrupts later). When the "E" bit is cleared, the associated "I" bit will have no effect on INTB or top-level interrupts. Note that the "E" bit does not affect the behaviour of the "I" bit itself. For example, the LOSE bit (reg 010h) is the interrupt enable for LOSI. If LOSE is cleared, the LOSI bit will continue to indicate changes in the LOSV bit but will never contribute to an INTB interrupt. 4.1.2 Top-Level Interrupts Most interrupts are grouped under one of several top-level interrupt status bits. These top level "I" bits represent the logical "or" of all enabled interrupts in that group, and allow software to monitor multiple interrupts with a single CPU read. For example, the LOSI interrupt is grouped under the RSOPI top-level interrupt (reg 002h) along with all other RSOP interrupts. RSOPI will assert whenever LOSI and LOSE are both set (or OOFI and OOFE, or ...). Top level interrupts cannot be cleared directly; instead, they will clear when the underlying interrupts are cleared. Some top-level interrupts status bits have an associated enable bit. These bits are identical to the "E" bits for other interrupts. That is, the top-level interrupt will only contribute to INTB if the enable bit is set. As with other "E" bits, the interrupt enable bits for top level interrupts don't change the value of the "I" bit itself. Toplevel interrupts without "E" bits always contribute to INTB. 4.1.3 Auxiliary Interrupts A final type of interrupt is the auxiliary interrupt. Auxiliary interrupts provide a second "I" bit for many commonly used interrupts. The second "I" bit is useful when the SPECTRA-155 is used with software architectures that combine polling and interrupt service routines. With the "clear-on-read" interrupt bits, software can inadvertently clear one or more interrupts by reading from a register containing the "I" bits. The auxiliary interrupts provide a second "clear-on-write" interrupt bit that is easier to deal with in software. As shown in Figure 1, the auxiliary interrupts have a separate enable bit from the main interrupt. Auxiliary interrupts are also cleared independently of the main interrupt. For example, clearing the LOFI interrupt (reg 011h) has no effect on the auxiliary LOFI interrupt (reg 0E6h). All auxiliary interrupts contribute directly to INTB, without going through a top-level interrupt.
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4.2
Interrupt Cross-Reference Table 9 shows the entire SPECTRA-155 interrupt hierarchy, including interrupt status bits, auxiliary interrupts, and interrupt enables. The format of Table 9 is described in Figure 2. Figure 2 - Interrupt Cross-Reference Legend
inte rrup t status b it register cle ar type (R =clea r-on-read , W =cle ar-o n w rite)
In te rr u p t H iera r c h y
IN T B C R S II ( 0 0 2 ) C R S IE (0 01 ) D O O L I (0 4 0 , R ) D O O L E (0 40 ) R O O L I (0 4 0 , R ) R O O L E (0 40 ) C S P II ( 0 0 2 ) C S P IE (0 01 ) R O O L I (0 4 2 , R ) R O O L E (0 42 )
S ta te B it
D O O L V (0 4 0 ) R O O L V (0 4 0 )
A u x iliary
RDO O L I (0E 6, W ) R D O O L IE N (0 F 7 )
R O O L V (0 4 2 )
T R O O L I (0 E 6 , W ) T R O O L IE N (0F 7)
v alue b it
associa ted a uxiliary interrupt
inte rrup t ena ble b it and re gister top -le vel in terru pt and e nable
Table 9
- Interrupt Cross-Reference
Interrupt Hierarchy State Bit Auxiliary
INTB
CRSII (002) CRSIE (001)
DOOLI (040, R) DOOLE (040) ROOLI (040, R) ROOLE (040)
DOOLV (040)
RDOOLI (0E6, W) RDOOLIEN (0F7)
ROOLV (040)
CSPII (002) CSPIE (001) RASEI (002) RASEE (001)
ROOLI (042, R) ROOLE (042) COAPSI (021, R) COAPSE (020) PSBFI (021, R) PSBFE (020) SDBERI (021, R) SDBERE (020) SFBERI (021, R) SFBERE (020)
ROOLV (042)
TROOLI (0E6, W) TROOLIEN (0F7)
PSBFV (021)
SDBERV (021)
SFBERV (021)
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PM5342 SPECTRA-155
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Interrupt Hierarchy
State Bit
Auxiliary
RASEI (cont'd)
Z1/S1I (021, R) Z1/S1E (020)
RLOPI (002) RLOPE (001)
BIPEI (009, R) BIPEE (009) LAISI (009, R) LAISE (009) LRDII (009, R) LRDIE (009) LREII (009, R) LREIE (009) LRDIV (008) LAISV (008) LAISI (0E6, W) LAISIEN (0F7) LRDII (0E6, W) LRDIIEN (0F7)
RSOPI (002) RSOPE (001)
BIPEI (011, R) BIPEE (010) LOFI (011, R) LOFE (010) LOSI (011, R) LOSE (010) OOFI (011, R) OOFE (010) OOFV (011) LOSV (011) LOFV (011) LOFI (0E6, W) LOFIEN (0F7) LOSI (0E6, W) LOSIEN (0F7) OOFI (0E6, W) OOFIEN (0F7) RTIMV (039)
SSTBI (002) SSTBE (001)
RTIMI (039, R) RTIMIE (038) RTIUI (039, R) RTIUIE (038) SCPIFI[0] (01F, W) SCPIFE[0] (015) SCPIFI[1] (01F, W) SCPIFE[1] (015) SCPIRI[0] (01F, W) SCPIRE[0] (015) SCPIRI[1] (01F, W) SCPIRE[1] (015) ABUS_SYNCI (07B, R) ABUS_SYNCE (07A) DBUS_SYNCI (07B, R) DBUS_SYNCE (079) PTIU2I#1 (0EB, R) PTIU2IE#1 (0EB) PTIU2I#2 (0EB, R) PTIU2IE#2 (0EB)
RTIUV (039)
SCPIV[0] (01F)
SCPIV[1] (01F)
SCPIV[0] (01F)
SCPIV[1] (01F)
ABUS_SYNCV (07A)
DBUS_SYNCV (079)
PTIU2V#1 (0EC)
TIU2I#1 (0EA, W) TIU2I#1EN (0FB)
PTIU2V#2 (0EC)
TIU2I#2 (0EA, W) TIU2I#2EN (0FB)
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Interrupt Hierarchy
State Bit
Auxiliary
PTIU2I#3 (0EB, R) PTIU2IE#3 (0EB) STIU2I (0EB, R) STIU2IE (0EB) D3MA[3:1]I (103) OFLI (095, R) OFLIEN (096) UFLI (095, R) UFLIEN (096) OFLI (09D, R) OFLIEN (09B) UFLI (09D, R) UFLIEN (09B) OFLI (0A5, R) OFLIEN (0A6) UFLI (0A5, R) UFLIEN (0A6) D3MD[3:1]I (103) OFLI (091, R) OFLIEN (092) UFLI (091, R) UFLIEN (092) OFLI (099, R) OFLIEN (09A) UFLI (099, R) UFLIEN (09A) OFLI (0A1, R) OFLIEN (0A2) UFLI (0A1, R) UFLIEN (0A2) TPIP1I (103) NEWPTRI (0B0, R) NEWPTRE (0B0) BIPEI (0B1, R) BIPEE (0B3) LOPCONI (0B1, R) LOPCONE (0B3) LOPI (0B1, R) LOPE (0B3) PAISCONI (0B1, R) PAISCONE (0B3) PAISI (0B1, R) PAISE (0B3)
PTIU2V#3 (0EC)
TIU2I#3 (0EA, W) TIU2I#3EN (0FB)
STIU2V (0EC)
LOPCONV (0B0)
LOPV (0B0)
PAISCONV (0B0)
PAISV (0B0)
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Interrupt Hierarchy
State Bit
Auxiliary
TPIP1I (cont'd)
PREII (0B1, R) PREIE (0B3) CONCATI (0B2, R) CONCATE (0B4) DISCOPAI (0B2, R) DISCOPAE (0B4) ILLJREQI (0B2, R) ILLJREQE (0B4) INVNDFI (0B2, R) INVNDFE (0B4) NDFI (0B2, R) NDFE (0B4) NSEI (0B2, R) NSEE (0B4) PSEI (0B2, R) PSEE (0B4) COMAI (0BC, R) COMAE (0BC) LOMI (0BC, R) LOME (0BC) LOMV (0BC)
TPIP2I (103)
NEWPTRI (0C0, R) NEWPTRE (0C0) BIPEI (0C1, R) BIPEE (0C3) LOPCONI (0C1, R) LOPCONE (0C3) LOPI (0C1, R) LOPE (0C3) PAISCONI (0C1, R) PAISCONE (0C3) PAISI (0C1, R) PAISE (0C3) PREII (0C1, R) PREIE (0C3) CONCATI (0C2, R) CONCATE (0C4) DISCOPAI (0C2, R) DISCOPAE (0C4) ILLJREQI (0C2, R) ILLJREQE (0C4) PAISV (0C0) PAISCONV (0C0) LOPV (0C0) LOPCONV (0C0)
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Interrupt Hierarchy
State Bit
Auxiliary
TPIP2I (cont'd)
INVNDFI (0C2, R) INVNDFE (0C4) NDFI (0C2, R) NDFE (0C4) NSEI (0C2, R) NSEE (0C4) PSEI (0C2, R) PSEE (0C4) COMAI (0CC, R) COMAE (0CC) LOMI (0CC, R) LOME (0CC) LOMV (0CC)
TPIP3I (103)
NEWPTRI (0D0, R) NEWPTRE (0D0) BIPEI (0D1, R) BIPEE (0D3) LOPCONI (0D1, R) LOPCONE (0D3) LOPI (0D1, R) LOPE (0D3) PAISCONI (0D1, R) PAISCONE (0D3) PAISI (0D1, R) PAISE (0D3) PREII (0D1, R) PREIE (0D3) CONCATI (0D2, R) CONCATE (0D4) DISCOPAI (0D2, R) DISCOPAE (0D4) ILLJREQI (0D2, R) ILLJREQE (0D4) INVNDFI (0D2, R) INVNDFE (0D4) NDFI (0D2, R) NDFE (0D4) NSEI (0D2, R) NSEE (0D4) PSEI (0D2, R) PSEE (0D4) PAISV (0D0) PAISCONV (0D0) LOPV (0D0) LOPCONV (0D0)
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PM5342 SPECTRA-155
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Interrupt Hierarchy
State Bit
Auxiliary
TPIP3I (cont'd)
COMAI (0DC, R) COMAE (0DC) LOMI (0DC, R) LOME (0DC) LOMV (0DC)
RPOP1I (104)
NEWPTRI (110, R) NEWPTRE (110) BIPEI (111, R) BIPEE (113) ERDII (111, R) ERDIE (113) LOPCONI (111, R) LOPCONE (113) LOPI (111, R) LOPE (113) PAISCONI (111, R) PAISCONE (113) PAISI (111, R) PAISE (113) PRDII (111, R) PRDIE (113) PREII (111, R) PREIE (113) CONCATI (112, R) CONCATE (114) DISCOPAI (112, R) DISCOPAE (114) ILLJREQI (112, R) ILLJREQE (114) INVNDFI (112, R) INVNDFE (114) NDFI (112, R) NDFE (114) NSEI (112, R) NSEE (114) PSEI (112, R) PSEE (114) COMAI (11C, R) COMAE (11C) LOMI (11C, R) LOME (11C) LOMV (11C) LOMI (0E7, W) LOMIEN (0F8) PRDIV (110) PAISV (110) PAISCONV (110) LOPV (110) LOPCONV (110) ERDIV[2:0] (110) EPRDII#1 (0EA, W) EPRDII#1EN (0FB) LOPCONI (0EA, W) LOPCONIEN (0FB) LOPI (0E7, W) LOPIEN (0F8) PAISCONI (0EA, W) PAISCONIEN (0FB) PAISI (0E7, W) PAISEN (0F8) PRDII (0E7, W) PRDIEN (0F8)
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Interrupt Hierarchy
State Bit
Auxiliary
RPOP2I (104)
NEWPTRI (150, R) NEWPTRE (150) BIPEI (151, R) BIPEE (153) ERDII (151, R) ERDIE (153) LOPCONI (151, R) LOPCONE (153) LOPI (151, R) LOPE (153) PAISCONI (151, R) PAISCONE (153) PAISI (151, R) PAISE (153) PRDII (151, R) PRDIE (153) PREII (151, R) PREIE (153) CONCATI (152, R) CONCATE (154) DISCOPAI (152, R) DISCOPAE (154) ILLJREQI (152, R) ILLJREQE (154) INVNDFI (152, R) INVNDFE (154) NDFI (152, R) NDFE (154) NSEI (152, R) NSEE (154) PSEI (152, R) PSEE (154) COMAI (15C, R) COMAE (15C) LOMI (15C, R) LOME (15C) LOMV (15C) LOMI (0E8, W) LOMIEN (0F9) PRDIV (150) PAISV (150) PAISI (0E8, W) PAISEN (0F9) PRDII (0E8, W) PRDIEN (0F9) PAISCONV (150) LOPV (150) LOPI (0E8, W) LOPIEN (0F9) LOPCONV (150) ERDIV[2:0] (150) EPRDII#2 (0EA, W) EPRDII#2EN (0FB)
RPOP3I (104)
NEWPTRI (190, R) NEWPTRE (190) BIPEI (191, R) BIPEE (193)
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PM5342 SPECTRA-155
APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Interrupt Hierarchy
State Bit
Auxiliary
RPOP3I (cont'd)
ERDII (191, R) ERDIE (193) LOPCONI (191, R) LOPCONE (193) LOPI (191, R) LOPE (193) PAISCONI (191, R) PAISCONE (193) PAISI (191, R) PAISE (193) PRDII (191, R) PRDIE (193) PREII (191, R) PREIE (193) CONCATI (192, R) CONCATE (194) DISCOPAI (192, R) DISCOPAE (194) ILLJREQI (192, R) ILLJREQE (194) INVNDFI (192, R) INVNDFE (194) NDFI (192, R) NDFE (194) NSEI (192, R) NSEE (194) PSEI (192, R) PSEE (194) COMAI (19C, R) COMAE (19C) LOMI (19C, R) LOME (19C)
ERDIV[2:0] (190)
EPRDII#3 (0EA, W) EPRDII#3EN (0FB)
LOPCONV (190)
LOPV (190)
LOPI (0E9, W) LOPIEN (0FA)
PAISCONV (190)
PAISV (190)
PAISI (0E9, W) PAISEN (0FA)
PRDIV (190)
PRDII (0E9, W) PRDIEN (0FA)
LOMV (19C)
LOMI (0E9, W) LOMIEN (0FA)
RTAL1I (104)
ESEI (129, R) ESEE (128) NPJI (129, R) DPJEE (128) PPJI (129, R) DPJEE (128) ISFI (12A, R) ISFE (128) ISFV (12A)
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Interrupt Hierarchy
State Bit
Auxiliary
RTAL2I (104)
ESEI (169, R) ESEE (168) NPJI (169, R) DPJEE (168) PPJI (169, R) DPJEE (168) ISFI (16A, R) ISFE (168) ISFV (16A)
RTAL3I (104)
ESEI (1A9, R) ESEE (1A8) NPJI (1A9, R) DPJEE (1A8) PPJI (1A9, R) DPJEE (1A8) ISFI (1AA, R) ISFE (1A8) ISFV (1AA)
SPTB1I (105)
RTIMI (149, R) RTIMIE (149) RTIUI (149, R) RTIUIE (149) UNEQI (149, R) UNEQIE (14D) RPSLMI (14D, R) RPSLMIE (14D) RPSLUI (14D, R) RPSLUIE (14D)
RTIMV (149)
TIMI (0E7, W) TIMIEN (0F8)
RTIUV (149)
TIUI (0E7, W) TIUIEN (0F8)
UNEQV (149)
RPSLMV (14D)
PSLMI (0E7, W) PSLMIEN (0F8)
RPSLUV (14D)
PSLUI (0E7, W) PSLUIEN (0F8)
SPTB2I (105)
RTIMI (189, R) RTIMIE (189) RTIUI (189, R) RTIUIE (189) UNEQI (189, R) UNEQIE (18D) RPSLMI (18D, R) RPSLMIE (18D) RPSLUI (18D, R) RPSLUIE (18D)
RTIMV (189)
TIMI (0E8, W) TIMIEN (0F9)
RTIUV (189)
TIUI (0E8, W) TIUIEN (0F9)
UNEQV (189)
RPSLMV (18D)
PSLMI (0E8, W) PSLMIEN (0F9)
RPSLUV (18D)
PSLUI (0E8, W) PSLUIEN (0F9)
SPTB3I (105)
RTIMI (1C9, R) RTIMIE (1C9)
RTIMV (1C9)
TIMI (0E9, W) TIMIEN (0FA)
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APPLICATION NOTE PMC-980901 ISSUE 1 SPECTRA-155 PROGRAMMER'S REFERENCE
Interrupt Hierarchy
State Bit
Auxiliary
SPTB3I (cont'd)
RTIUI (1C9, R) RTIUIE (1C9) UNEQI (1C9, R) UNEQIE (1CD) RPSLMI (1CD, R) RPSLMIE (1CD) RPSLUI (1CD, R) RPSLUIE (1CD)
RTIUV (1C9)
TIUI (0E9, W) TIUIEN (0FA)
UNEQV (1C9)
RPSLMV (1CD)
PSLMI (0E9, W) PSLMIEN (0FA)
RPSLUV (1CD)
PSLUI (0E9, W) PSLUIEN (0FA)
TTAL1I (105)
ESEI (141, R) ESEE (140) NPJI (141, R) PJEE (140) PPJI (141, R) PJEE (140) ISFI (142, R) ISFE (140) ISFV (142)
TTAL2I (105)
ESEI (181, R) ESEE (180) NPJI (181, R) PJEE (180) PPJI (181, R) PJEE (180) ISFI (182, R) ISFE (180) ISFV (182)
TTAL3I (105)
ESEI (1C1, R) ESEE (1C0) NPJI (1C1, R) PJEE (1C0) PPJI (1C1, R) PJEE (1C0) ISFI (1C2, R) ISFE (1C0) API (109, R) APE (109) ISFV (1C2)
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5
SONET AND SDH CONFIGURATION The following table lists the major configuration differences in the SPECTRA-155 for all SDH and SONET applications. This list is not exhaustive, and all configuration values should be checked to ensure they meet current standards requirements. Not shown in the table are configuration registers that are application dependent, like the C2 byte. Also not shown are registers that require real-time processor intervention, such as the K1, K2 bytes which are monitored and updated according to the APS status. Table 10 - SDH and SONET Configuration Values
SDH Value 0 or 1 SONET Value 0 Standards References G.783 (04/97) 2.2.2.7 GR-253-CORE (Issue 2) R6-184 LAISDET (08) 0 or 1 0 G.783 (04/97) 5.2.2 GR-253-CORE (Issue 2) R6-147 RASE Block see datasheet SDH settings LEN16 (38, 148, 188, 1C8) PER5 (38, 148, 188, 1C8) PSL5 (110, 150, 190) 1 ? 1 see datasheet SONET settings 0 ? 1 G.783 (04/97) 2.2.2.5 GR-253-CORE (Issue 2) 5.3.3 G.783 (04/97) 9.2.2.2 not defined G.783 (04/97) 2.2.2.2 GR-253-CORE (Issue 2) R6-119 RDI10 (116, 156, 196) 0 0 or 1 G.783 (04/97) 2.2.2.15 GR-253-CORE (Issue 2) R6-197, R6-198 DISFS (BD, CD, DD, 11D, 15D, 19D) ENSS (BD, CD, DD, 11D, 15D, 19D) SSS (128, 168, 1A8) 1 0 1 0 1 0 G.707 (03/96) 9.3.1.2 GR-253-CORE (Issue 2) R3-21 G.783 (04/97) Annex C GR-253-CORE (Issue 2) 3.5.1 G.783 (04/97) Annex C GR-253-CORE (Issue 2) 3.5.1 PERSIST (130, 170, 1B0) 0 1 G.783 (04/97) under discussion GR-253-CORE (Issue 2) O6-193 EXCFS (130, 170, 1B0) 1 0 G.707 (03/96) 9.3.1.2 GR-253-CORE (Issue 2) R3-21
Register Bit (address) LRDIDET (08)
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Register Bit (address) S[1:0] (135, 175, 1B5)
SDH Value 10b
SONET Value xxb (usually 00b)
Standards References G.707 (03/96) 8.1.2 GR-253-CORE (Issue 2) 3.5.1
CONCAT[11:10] (13F)
xxb (usually 10b)
xxb (usually 00b)
G.707 (03/96) 8.1.2 GR-253-CORE (Issue 2) 3.5.1.4
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APPENDIX: OVERHEAD BYTES The figure below gives a map of all overhead bytes. This map shows the names given to overhead bytes in both SONET and SDH. Where the two standards give different names to the bytes, the SONET name is shown on top and the SDH name on the bottom. Unused bytes are not named. Figure - SONET and SDH Overhead Bytes
A1
Section RSOH
A1
A1
A2 E1 D2
A2
A2
J0 F1 D3
Z0 Nat Nat
Z0 Nat Nat
J1 B3 C2
B1 D1
AU
H1 H1* H1* H2 H2* H2* H3 B2 B2 B2 K1 D5 D8 D11
Z1 Z1 Z2 Z2
H3
H3
Path
G1 F2 H4
Z3 F3 Z4 K3
K2 D6 D9 D12 M1 E2
Nat Nat
Line MSOH
D4 D7 D10 S1
Z5 N1
Transport Overhead A1, A2 Framing. The framing bytes contain constant F6, 28h values which allow network equipment to determine the start of a frame in the serial datastream. BIP-8. Bit interleaved parity for error monitoring at the Section (Regenerator Section) level. BIP-mx8. Bit interleaved parity for error monitoring at the Line (Multiplex Section) level. Data Communications Channels. Separated into two separate channels: a 192kb/s Section (Regenerator Section) DCC consisting of D1-D3, and a 578kb/s Line (Multiplex
B1 B2 D1 - D12
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Section) DCC consisting of D4-D12. The DCC channels normally contain alarm, maintenance, and control information using a complex message-based protocol contained within HDLC frames. E1, E2 F1 H1, H2 H3 Orderwire. 64kbit/s voice channels (8-bit PCM encoded) for craftsperson communications. User Channel. Reserved for use by the network provider. Pointer. The pointer value bytes locate the start of the SPE (VC-4 or VC-3) within the frame. Pointer Action. The pointer action byte contains payload when a negative stuff event occurs, and is undefined at all other times. Section Trace/Multiplex Section Trace. In older systems, J0 was known as C1, and contained a 01h to identify the first STS-1 (AU-3) within a multiplexed datastream. This byte has since been redefined to contain a 64 byte (16 byte in SDH) trace identifier message. Automatic Protection Switching (APS) Channel. The K1 and K2 bytes are allocated for signalling in Line (Multiplex Section) protection schemes. In addition, bits 6, 7, and 8 of the K2 byte are used to convey Line (Multiplex Section) RDI and AIS signals. STS-1 (STM-0) REI. Not defined in STS-3 (STM-1) and higher rates. Bits 5-8 provide a count of far-end B2 errors (formerly known as FEBEs). Bits 1 through 4 are currently undefined. STS-N REI (MS-REI). Provides a count of far-end B2 errors (formerly known as FEBEs). National Use (SDH only). Reserved for national use. Synchronization Status Byte. The S1 byte provides the synchronization status byte. Bits 5 through 8 of the synchronization status byte identifies the synchronization source of the STS-3c/1 (STM-1) signal. Bits 1 through 4 are currently undefined.
J0
K1, K2
M0
M1 Nat S1
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Z0 Z1, Z2 Path Overhead B3 C2
Section Growth (SONET only). Reserved for future growth. Growth (SONET only). Reserved for future growth.
Path BIP-8. Bit interleaved parity for monitoring at the Path level. Signal Label. A code identifying the content or status of the payload. For example, the value 02 indicates a VT (TUG) structured payload. Path User Channel. Reserved for communications between path terminating network equipment. Path User Channel (SDH only). Reserved for communications between path terminating network equipment. Path Status. Bits 1-4 provide a count of far-end B3 errors. (REI, formerly FEBE). Bit 5 provides a remote defect indication (RDI). Bits 6 and 7 optionally contribute to the RDI to form an enhanced RDI code in which the type of defect may be communcated. Bit 8 is undefined. Position Indicator. Payload-specific position indicator. For VT (TUG) structured payloads, this byte is used as a multiframe phase indicator. Path Trace. A 64 byte (16 byte in SDH) trace identifier message. Automatic Protection Switching (APS) Channel (SDH only). Allocated for signalling in Path protection schemes. Network Operator Byte (SDH only). Used for the Tandem Connection function. Path Growth (SONET only). Reserved for future growth.
F2 F3
G1
H4
J1 K3 N1 Z3 - Z5
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PMC-961079 (R5) ref PMC-xxxxxx (Rx) Issue date: May 1998
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