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| PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PM7344 S/UNI-MPH S/UNI-MPH with QDSX Reference Design Issue 2: June 1997 PMC-Sierra, Inc.105 - 8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415 6000 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONTENTS CONTENTS ....................................................................................................................... i LIST OF FIGURES ...........................................................................................................iii LIST OF TABLES..............................................................................................................iv REFERENCES ................................................................................................................. 1 Changes to This Issue ...................................................................................................... 2 OVERVIEW....................................................................................................................... 3 FUNCTIONAL DESCRIPTION.......................................................................................... 4 Block Diagram ............................................................................................................... 4 PM7344 S/UNI-MPH ..................................................................................................... 5 PM4314 QDSX.............................................................................................................. 7 Dual-Port RAM .............................................................................................................. 8 Memory Map.............................................................................................................. 8 Mailbox Communication .......................................................................................... 10 PIC16C74 Microcontroller ........................................................................................... 19 Firmware ..................................................................................................................... 20 External Memory Accesses ..................................................................................... 20 Initialization .............................................................................................................. 21 Dual-Port Mailboxes ................................................................................................ 21 Datalink Service Routines (RFDL/XFDL)................................................................. 21 Maintenance Functions............................................................................................ 22 Performance Monitoring .......................................................................................... 24 IMPLEMENTATION DESCRIPTION............................................................................... 26 Hardware..................................................................................................................... 26 PIC16C74 Microcontroller........................................................................................ 26 Dual-Port RAM......................................................................................................... 28 S/UNI-MPH Functional Block................................................................................... 29 QDSX Functional Block ........................................................................................... 29 Line Interface Circuitry ................................................................................................ 30 Timing Distribution ................................................................................................... 30 100-Pin Connector P1: Host Interface ..................................................................... 30 100-Pin Connector P21: SCI-PHY Interface ............................................................ 32 20-Pin Connector P22: SCI-PHY MultiPHY Interface .............................................. 33 Firmware ..................................................................................................................... 34 The P16C74.INC File............................................................................................... 35 The MACROS.INC File ............................................................................................ 35 i PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface The MPH.ASM File .................................................................................................. 35 APPENDIX A: DESIGN CONSIDERATIONS ................................................................ 47 Power Supply Voltage Transients ............................................................................... 47 Ground Noise .............................................................................................................. 47 Noise-Bypassing at Power Pins .................................................................................. 47 Values of Noise-Bypassing Capacitors ....................................................................... 47 Placement of Noise-Bypassing Capacitors ................................................................. 48 Ferrite Beads............................................................................................................... 49 Unused CMOS Inputs ................................................................................................. 49 APPENDIX B: MATERIAL LIST..................................................................................... 50 APPENDIX C: SCHEMATICS........................................................................................ 51 APPENDIX D: FIRMWARE............................................................................................ 52 CONTACTING PMC-SIERRA....................................................................................... 110 NOTES..........................................................................................................................112 ii PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface LIST OF FIGURES Figure 1. Block Diagram of PIC16C74 Connections ...................................................... 20 Figure 2. PIC16C74 Port Map......................................................................................... 26 iii PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface LIST OF TABLES Table 1. Dual-port RAM Memory Map .............................................................................. 8 Table 2. RFDL Memory block of 80H bytes ...................................................................... 9 Table 3. XFDL Memory block of 80H bytes .................................................................... 10 Table 4. PMON Memory block of 13H bytes................................................................... 10 Table 5. Host-to-PIC16C74 Mailbox Codes .................................................................... 11 Table 6. PIC16C74-to-Host Mailbox Codes .................................................................... 15 Table 7. Performance Report Packet Format ................................................................ 24 Table 8. Performance Report Data Byte Structure ........................................................ 25 Table 9. 100-Pin P1Connector: Host Interface Pin Definitions ...................................... 30 Table 10. 100-Pin Connector P21: SCI-PHY Interface Pin Definitions .......................... 32 Table 11. 20-Pin Connector P22: Multi-PHY Interface Pin Definitions........................... 34 Table 12. Macros in MACROS.INC................................................................................ 35 Table 13. Description of Macros in MPH.ASM................................................................ 36 Table 14. S/UNI-MPH Initialization Register Values ...................................................... 40 Table 15. QDSX Initialization Register Values............................................................... 42 iv PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface REFERENCES * * * American National Standards for Telecommunications, ANSI T1.107 (1988), "Digital Hierarchy - Formats Specifications" American National Standards for Telecommunications, ANSI T1.107 (Draft 1995), "Digital Hierarchy - Formats Specifications" American National Standards for Telecommunications, ANSI T1.231 (1993), "Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring" American National Standards for Telecommunications, ANSI T1.403 (1994), "Network-to-Customer Installation -- DS1 Metallic Interface" Integrated Device Technology, Data Book (1995), "Specialized Memories, FIFOs & Modules" Microchip Technology Inc., Data Book (1994) Microchip Technology Inc., DS00566A (1993), "Using the Port B Interrupt-onChange as an External Interrupt" Microchip Technology Inc., DS300271 (1995), "MPSIM User's Guide" Microchip Technology Inc., DS33014D (1995), "MPASM User's Guide" PMC-Sierra, Data Book (Issue 6), "PM7344 S/UNI-MPH Saturn Quad T1/E1 Multi-PHY User Network Interface", PMC-940873 PMC-Sierra, Data Book (Issue 2) "PM4314 QDSX Quad T1/E1 Line Interface Device", PMC-950739 PMC-Sierra, Reference Design (October 1995), "D3MX Module of PM4944 M13 Reference Design", PMC-951046 PMC-Sierra, Reference Design (January 1996), "RCMP Reference Design", PMC-960148 PMC-Sierra, "Saturn compatible interface for ATM PHY layer and ATM layer devices, Level 2", PMC-940102 ATM Forum, "User Network Interface specification", Ver 3.1 * * * * * * * * * * * * 1 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Changes to This Issue * The schematic diagram in Appendix C have been changed to reflect an error in Issue 1 of this document. The Issue 1 schematics indicated to tie ALE of the PM-7344 S/UNI-MPH and the PM-4314 QDSX to ground. The correct operation is to tie ALE high to VDD_D. The register initialization in Table 14 sets up the S/UNI-MPH for single rail mode, as does the initialization routine in the firmware in Appendix D. The schematic diagram also indicates a design for single rail mode. However, the description of Table 14 indicated that the initialization was for dual rail mode. That description has been changed to read single rail. The register initialization in Table 14 and the initialization firmware in Appendix D indicate to set register 0x04 in the S/UNI-MPH to a value of 0x48. It should read 0x08. Table 14 and the initialization firmware in Appendix D have been changed to reflect this. * * 2 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface OVERVIEW This document describes a possible implementation of the S/UNI-MPH with QDSX reference design. The S/UNI-MPH with QDSX Reference Design embodies PMC-Sierra's guidelines and suggestions for designing an interface for DSX-1 signals to a SCI-PHYTM Multi-PHY ATM cell bus using PMC-Sierra products (such as the PM7344 S/UNI-MPH and the PM4314 QDSX). In addition to the PM7344 S/UNI-MPH and the PM4314 QDSX devices, the MPH Module incorporates an on-board microcontroller (Microchip PIC16C74) for providing the local maintenance functions -- including termination of the ESF datalink in the DS1 overhead. The DSX-1 line interface functions are provided by the QDSX and the DS-1 framing functions are provided by the S/UNI-MPH. The S/UNI-MPH also provides the ATM cell processing functions associated with the PHY layer, including the implementation of a SCI-PHY multi-PHY interface to the ATM layer device(s). The physical connection is provided through 100-pin and 20-pin connectors, pin-compatible with the RCMP reference design (PMC-960148). The S/UNI-MPH Module communicates with a host system using a 100-pin connector. The pin-out of this connector is compatible for connection with the D3MX Module. The host does not have a direct connection to the microprocessor port of the S/UNI-MPH. Rather, a dual-port RAM, shared by the host and the local PIC16C74, is used to pass control and status information about the S/UNI-MPH to and from the host, where the actual register accesses to the S/UNI-MPH are performed by the PIC16C74. The advantage to this architecture is that the host system is not burdened by the lowlevel monitoring and control functions. 3 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface FUNCTIONAL DESCRIPTION Block Diagram 1 0 0 - Pi n Connect or 2 0 - Pi n Connect or SC I-PHY AT M Cell bus TM Addres s/ Cont rol Bus S CI-PHY Multi-PHY AT M Cell bus TM PM7 3 4 4 S / U NI - MPH Data Bus PI C1 6 C7 4 C Tx S erial 4 DS 1s 4 Rx S erial DS 1s DS X-1 L ine Int erface Connectors Tx Rx 4 4 PM4 3 1 4 QX DS Dual - Por t S RA M Addres s/ Cont rol Bus Data Bus 1 0 0 - Pi n Connect or 4 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PM7344 S/UNI-MPH The PM7344 SATURN Quad T1/E1 Multi-PHY User Network Interface (S/UNI-MPH) is a monolithic integrated circuit that implements the T1/E1 processing and ATM mapping functions for four 1.544 Mbit/s or 2.048 Mbit/s ATM User Network Interfaces. It can also be used in conjunction with external framing devices, to implement ATM user network interfaces for other bit rates. For example, a quad J2 (6.312 Mbit/s) interface can be realized with four external J2 framers and a single S/UNI-MPH. It is fully compliant with both ANSI and ITU requirements and ATM Forum UNI specifications. The S/UNI-MPH is software configurable, allowing feature selection without changes to external wiring. On the receive side, when configured for T1 processing, the S/UNI-MPH recovers clock and data and can be configured to frame to either of the common DS-1 signal formats; SF or ESF. Clock recovery may also be bypassed. The S/UNI-MPH also supports detection of various alarm conditions such as loss of signal, pulse density violation, red alarm, yellow alarm, and AIS alarm. The S/UNI-MPH detects and indicates the presence of yellow and AIS patterns and also integrates yellow, red, and AIS alarms as per industry specifications. Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events is provided. The S/UNI-MPH also detects the presence of in-band loopback codes, ESF bit oriented codes, and detects and terminates HDLC messages on the ESF data link. On the receive side, when configured for E1 processing, the S/UNI-MPH recovers clock and data and can be configured to frame to a basic G.704 2048 kbit/s signal or also frame to the signaling multiframe alignment signal and the CRC multiframe alignment signal. Clock recovery may also be bypassed. The S/UNI-MPH also supports detection of various alarm conditions such as loss of signal, loss of frame, loss of signaling multiframe, loss of CRC multiframe, and reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and timeslot 16 alarm indication signal. The S/UNI-MPH detects and indicates the presence of remote alarm and AIS patterns and also integrates red and AIS alarms as per industry specifications. Performance monitoring with accumulation of CRC-4 errors, far end block errors, framing bit errors, and line code violation is provided. The S/UNI-MPH also detects and terminates HDLC messages on a data link. The data link may be extracted from timeslot 16 or may be extracted from the national bits. For both T1 and E1 configurations, the S/UNI-MPH interprets the received frame alignment and extracts the transmission format payload which carries the received ATM cell payload. 5 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface The S/UNI-MPH frames to the ATM payload using cell delineation. HCS error correction is optionally provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. Valid, assigned cells are written to a four cell FIFO buffer. These cells are read from the FIFO using a synchronous 8 bit wide datapath interface with a cell-based handshake. Counts of received ATM cell headers that are errored and uncorrectable, those that are errored and correctable and all passed cells are accumulated independently for performance monitoring purposes. A multi-PHY interface allows the four receive FIFOs (one for each T1 or E1 port) to be serviced via a single 8 bit wide bus, address, and control lines. On the transmit side, when configured for T1 processing, the S/UNI-MPH generates framing for SF and ESF DS1 formats. The S/UNI-MPH can also generate in-band loopback codes, ESF bit oriented codes, and transmit HDLC messages on the ESF data link. On the transmit side, when configured for E1 processing, the S/UNI-MPH generates framing for a basic G.704 2048 kbit/s signal. The signaling multiframe alignment signal may be optionally inserted and the CRC multiframe structure may be optionally inserted. HDLC messages on a data link can be transmitted. The data link may be inserted into timeslot 16 or may be inserted into the national bits. For both T1 and E1 configurations, the S/UNI-MPH generates the transmitted frame and inserts the transmit ATM cell payload into the transmission format payload appropriately. ATM cells are written to an internal programmable-length 4-cell FIFO using a synchronous 8 bit wide datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. The S/UNI-MPH generates of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed. A multiPHY interface allows the four transmit FIFOs (one for each T1 or E1 port) to be serviced via a single 8 bit wide bus, address, and control lines. The S/UNI-MPH is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-MPH also provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. For a complete description of the S/UNI-MPH, please refer to PMC-Sierra's PM7344 databook (document number PMC-940873). 6 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PM4314 QDSX The PM4314 QDSX Quad T1/E1 Line Interface Device is a monolithic integrated circuit that supports DSX-1 and CEPT E1 compatible transmit and receive interfaces for four 1.544 Mbit/s or 2.048 Mbit/s data streams. In the receive direction, clock and data are recovered from the received signal using a digital phase-locked loop that provides excellent high frequency jitter accommodation. The recovered data is decoded using B8ZS, HDB3, or AMI line code rules. Loss of signal and line code violations are detected. Line code violations are accumulated in internal counters. In the transmit direction, each quadrant of the QDSX can transmit either a DS-1/E1 stream encoded using B8ZS, HDB3, or AMI line code rules. The digital data is converted to high drive, dual rail RZ pulses that drive the DSX-1/E1 interface through a coupling transformer. The shape of the pulses is programmable to ensure that the DSX1/E1 pulse template is met after the signal is passed through different cable lengths or types. Driver performance monitoring is provided and can generate interrupts upon driver failure. A jitter attenuation function comprised of a digital phase-locked loop and data FIFO is available for use in either the transmit or receive path of each channel. Diagnostic loopback is provided and the loopback may be invoked past the analog transmit outputs using the driver performance monitors or invoked prior to the conversion to analog. Line loopback with jitter attenuation is provided and may be enabled for automatic operation based on detected inband loopback codes. The QDSX detects framed or unframed inband loopback code sequences from the received input pulses. Any arbitrary code from three to eight bits in length can be declared to be the activate and deactivate codes by writing to configuration registers. The inband loopback code detector can optionally be moved to the transmit side where it detects inband loopback codes in the unipolar input transmit data stream. For framed inband loopback code sequences, it is expected that the framing bit overwrites the inband loopback code bit. The QDSX may insert unframed inband loopback code sequences (programmable codes from three to eight bits in length) into the transmit or receive path of each channel. The QDSX detects framed or unframed inband loopback code sequences in either the transmit or receive path of each channel. Two arbitrary codes can be searched for simultaneously, each programmable between three to eight bits in length. The QDSX may insert an unframed 215-1 O.151 compatible pseudo-random bit sequence into the transmit or receive path of each channel. The QDSX can detect an 7 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface unframed 215-1 O.151 compatible pseudo-random bit sequence in either the transmit or receive path of each channel. The QDSX operates in conjunction with external line coupling transformers, resistors, and capacitors. An external crystal oscillator may be used for high speed timing generation. The QDSX is configured, controlled, and monitored using registers that are accessed via a generic microprocessor interface. Internal high speed timing for all quadrants of the QDSX is provided by a common 37.056 MHz or 49.152 MHz master clock. This master clock rate is required for applications where QDSX provides jitter attenuation. For a complete description of the QDSX, please refer to PMC-Sierra's QDSX Data Book (document number PMC-950857). Dual-Port RAM This reference design uses a high-speed 2K by 8-bit dual-port static RAM with internal interrupt logic (for inter-processor communications). Many manufacturers (such as Integrated Device Technology, and Cypress Semiconductors) produce pin-compatible versions of this device. The dual-port RAM has two ports with separate control, address and data pins that permit independent, asynchronous access for both reads and writes to any location in memory. Memory Map Tables 1 to 4 define the memory map for the dual-port RAM. The memory map is organized to provide a generic flexible interface to the S/UNI-MPH physical layer control and status functionality. Table 1. Dual-port RAM Memory Map Ram Address (hex) 000 080 100 180 200 280 300 Function (length) RFDL receive buffer and status, quadrant 1 (80h) RFDL receive buffer and status, quadrant 2 (80h) RFDL receive buffer and status, quadrant 3 (80h) RFDL receive buffer and status, quadrant 4 (80h) XFDL transmit buffer and status, quadrant 1 (80h) XFDL transmit buffer and status, quadrant 2 (80h) XFDL transmit buffer and status, quadrant 3 (80h) 8 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Ram Address (hex) 380 400 413 426 439 496 497 498 499 7DE 7DF 7E0 7F0 7F1 7F8 7F9 7FA 7FB 7FC 7FD 7FE 7FF Function (length) XFDL transmit buffer and status, quadrant 4 (80h) PMON shadow registers, quadrant 1 (13h) PMON shadow registers, quadrant 2 (13h) PMON shadow registers, quadrant 3 (13h) PMON shadow registers, quadrant 4 (13h) New signaling value (HOST->PIC) Quadrant to affect with signaling command (HOST->PIC) DS0 channel to affect with signaling command (HOST->PIC) New idle code (HOST->PIC) Contains firmware revision # Contains firmware version # Specifies BOC to transmit (HOST->PIC) Interrupting quadrant (PIC->HOST) Latest received BOC (PIC->HOST) Current RFDL interrupting quadrant (PIC->HOST) Current XFDL interrupting quadrant (PIC->HOST) Quadrant on which to transmit BOC (HOST->PIC) Register R/W data (HOST<->PIC) Register R/W address LSB (HOST<->PIC) Register R/W address MSB (HOST<->PIC) Host Mailbox (PIC->HOST) PIC16C74 Mailbox (HOST->PIC) Table 2. RFDL Memory block of 80H bytes Relative Address (hex) 00 - 7D 7E 7F Function Packet Data (maximum 126 bytes) Channel Status Packet Length 9 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Table 3. XFDL Memory block of 80H bytes Relative Address (hex) 00 - 7E 7F Function Packet Data (maximum 127 bytes) Packet Length Table 4. PMON Memory block of 13H bytes Relative Address (hex) 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 Function Frame error count Far end block error count LSB Far end block error count MSB CRC count LSB CRC count MSB Line code violation count LSB Line code violation count MSB RXCP uncorrectable HCS error count LSB RXCP uncorrectable HCS error count MSB RXCP correctable HCS error count LSB RXCP correctable HCS error count MSB RXCP idle/unassigned cell count LSB RXCP idle/unassigned cell count MSB RXCP receive cell count LSB RXCP receive cell count MSB TXCP transmit cell count LSB TXCP transmit cell count MSB Reserved Reserved Mailbox Communication Each port has one address location assigned as a "mailbox." When a port writes to its mailbox, the other port will be interrupted. This interrupt is cleared when the mailbox is read by the interrupted port. These mailboxes can be used as a control and status channel. By defining functions for certain values passed in the mailbox, each port can initiate actions of the other port. Additionally, a port can pass high-priority status information through the mailbox. 10 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface HOST-TO-PIC16C74 COMMUNICATION The host sends control commands through the microcontroller's mailbox (location 7FF). Table 5 shows the mailbox codes for host-to-PIC16C74 messaging. Following the table is a description of each command and further processing (if necessary) required of the host. Table 5. Host-to-PIC16C74 Mailbox Codes Code (hex) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 Function Read S/UNI-MPH register Write S/UNI-MPH register Start FDL packet transmission Start BOC transmission Stop BOC transmission Reserved Reserved Reserved Reserved Reserved Reserved Line Loopback Activate Line Loopback Deactivate Payload Loopback Activate Payload Loopback Deactivate Reserved Reserved Diagnostic Loopback Activate Diagnostic Loopback Deactivate Start AIS transmission Stop AIS transmission Read QDSX register Write QDSX register 11 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface READ S/UNI-MPH REGISTER (01) This function is useful for diagnostic purposes to read the value of a S/UNI-MPH register. To read a value from a specific S/UNI-MPH register perform the following steps: 1. 2. 3. 4. Write the LSB of the address of the register to RAM location 7FC. Write the MSB of the address of the register to RAM location 7FD. Write the mailbox command 01 to the PIC16C74 Mailbox (location 7FF). When the Requested S/UNI-MPH Register I/O Complete code (FF) is received in the Host Mailbox (7FE), the read register value will be available in RAM location 7FB. WRITE S/UNI-MPH REGISTER (02) This function is useful for diagnostic purposes to write a S/UNI-MPH register with a value. To write a value from a specific S/UNI-MPH register perform the following steps: 1. 2. 3. 4. Write the LSB of the address of the register to RAM location 7FC. Write the MSB of the address of the register to RAM location 7FD. Write the data byte value to RAM location 7FB. Write the mailbox command 02 to the PIC16C74 Mailbox (location 7FF). START FDL PACKET TRANSMISSION (03) After FDL packet data (up to 127 bytes) is placed in a quadrant's XFDL transmit buffer (in dual-port RAM), this command can be used to initiate transmission. Once initiated the packet transmission will be handled by the PIC16C74. To transmit an FDL packet perform the following steps: 1. Write the packet data to the quadrant's XFDL transmit buffer. 2. Write the packet's length to the Packet Length byte of the quadrant's XFDL transmit buffer. 3. Write the mailbox command 03 to the PIC16C74 Mailbox (location 7FF). START BIT-ORIENTED CODE TRANSMISSION (04) To send a bit-oriented code on a quadrant's facility data link perform the following steps: 1. Write the 6-bit BOC (least significant bit transmitted first) to RAM location 7E0. 2. Write the quadrant number (0-3) to RAM location 7FA. 3. Write the mailbox command 04 to the PIC16C74 Mailbox (location 7FF). The bit-oriented code will be transmitted until stopped using the Stop Bit-Oriented Code Transmission command. 12 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface STOP BIT-ORIENTED CODE TRANSMISSION (05) To stop the transmission of a bit-oriented code on a quadrant's facility data link perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 05 to the PIC16C74 mailbox (location 7FF). LINE LOOPBACK ACTIVATE (0C) To activate line loopback perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 0C to the PIC16C74 mailbox (location 7FF). LINE LOOPBACK DEACTIVATE (0D) To deactivate line loopback perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 0D to the PIC16C74 mailbox (location 7FF). PAYLOAD LOOPBACK ACTIVATE (0E) To activate payload loopback perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 0E to the PIC16C74 mailbox (location 7FF). PAYLOAD LOOPBACK DEACTIVATE (0F) To deactivate payload loopback perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 0F to the PIC16C74 mailbox (location 7FF). DIAGNOSTIC LOOPBACK ACTIVATE (12) To activate diagnostic loopback perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 12 to the PIC16C74 mailbox (location 7FF). 13 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface DIAGNOSTIC LOOPBACK DEACTIVATE (13) To deactivate diagnostic loopback perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 13 to the PIC16C74 mailbox (location 7FF). START AIS TRANSMISSION (14) To start AIS transmission perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 14 to the PIC16C74 mailbox (location 7FF). STOP AIS TRANSMISSION (15) To stop AIS transmission perform the following steps: 1. Write the quadrant number (0-3) to RAM location 7FA. 2. Write the mailbox command 15 to the PIC16C74 mailbox (location 7FF). READ QDSX REGISTER (16) This function is useful for diagnostic purposes to read the value of a QDSX register. To read a value from a specific QDSX register perform the following steps: 1. 2. 3. 4. Write the LSB of the address of the register to RAM location 7FC. Write the MSB of the address of the register to RAM location 7FD. Write the mailbox command 16 to the PIC16C74 Mailbox (location 7FF). When the Requested QDSX Register I/O Complete code (FF) is received in the Host Mailbox (7FE), the read register value will be available in RAM location 7FB. WRITE QDSX REGISTER (17) This function is useful for diagnostic purposes to write a QDSX register with a value. To write a value from a specific QDSX register perform the following steps: 1. 2. 3. 4. Write the LSB of the address of the register to RAM location 7FC. Write the MSB of the address of the register to RAM location 7FD. Write the data byte value to RAM location 7FB. Write the mailbox command 17 to the PIC16C74 Mailbox (location 7FF). 14 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PIC16C74 TO HOST COMMUNICATION The microcontroller sends alarm and status information to the host through the host's mailbox (location 7FE). Table 6 shows the mailbox codes for microcontroller-to-host messaging. Following the table is a description of each message and further processing (if necessary) required of the host. Because the PIC16C74 takes a finite time to process information, it will only indicate one interrupt at a time. The host must process the mailbox before the next mailbox code is written by the PIC16C74. With the current code, the shortest delay between consecutive mailbox interrupts occurs when multiple channels indicate a simple alarm (e.g. RED). Therefore, the host must process all mailbox interrupts within approximately 50 s, otherwise some information will be lost (overwritten). Table 6. PIC16C74-to-Host Mailbox Codes Code (hex) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 20 21 22 Meaning Reserved Reserved Reserved Reserved Reserved AIS asserted AIS cleared YELLOW alarm asserted YELLOW alarm cleared Reserved Reserved Reserved Reserved Valid BOC detected Return to idle BOC detected New FDL packet received (Q1) New FDL packet received (Q2) New FDL packet received (Q3) New FDL packet received (Q4) In-Band Line-Loopback-Activate Detected In-Band Line-Loopback-Deactivate Detected FDL packet has been successfully transmitted (Q1) FDL packet has been successfully transmitted (Q2) FDL packet has been successfully transmitted (Q3) 15 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Code (hex) 23 25 26 27 28 29 2A 2B FF 80 AIS ASSERTED (06) Meaning FDL packet has been successfully transmitted (Q4) Loss of clock activity asserted Loss of clock activity cleared Loss of cell delineation asserted Loss of cell delineation cleared Transmit FIFO overrun Receive FIFO overrun Change of cell alignment Requested S/UNI-MPH or QDSX register I/O completed PMON statistics updated This message is sent when the S/UNI-MPH detects that an AIS is being received. The originating quadrant can be determined by reading RAM location 7F0. The AIS detection will take 1.5 seconds to integrate in the presence of a continuously received AIS pattern. AIS CLEARED (07) This message is sent when the S/UNI-MPH detects that AIS is no longer being received. The originating quadrant can be determined by reading RAM location 7F0. The AIS clear will take 16.8 seconds to integrate in the presence of a continuously received framed pattern. YELLOW ALARM ASSERTED (08) This message is sent when the S/UNI-MPH detects that an ESF YELLOW alarm is being received. The originating quadrant can be determined by reading RAM location 7F0. The YELLOW detection will take 425 ms to integrate in the presence of a continuously received YELLOW pattern. YELLOW ALARM CLEARED (09) This message is sent when the S/UNI-MPH detects that the YELLOW alarm is no longer being received. The originating quadrant can be determined by reading RAM location 7F0. The YELLOW clear will take 425 ms to integrate in the presence of continuously received frames not containing the YELLOW pattern. 16 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface VALID BOC DETECTED (0E) This message is sent when the S/UNI-MPH detects a valid BOC on the received FDL. The originating quadrant can be determined by reading RAM location 7F0. The received BOC can be read from RAM location 7F1. A BOC is considered valid if it is repeated at least 8 times in a window of 10 consecutively received BOCs. If the BOC matches a standardized loopback activate or deactivate command, the PIC16C74 will automatically respond by putting the quadrant into the appropriate mode. Note that as specified in ANSI T1.403, a quadrant will not be put into the Line Loopback mode until the Line-Loopback-Activate BOC has been removed (to ensure that the loopback command is not looped back itself). For a list of the standardized loopback commands, see the Extended Superframe Loopbacks subsection of the functional description for the firmware. IDLE BOC DETECTED (0F) This message is sent when the S/UNI-MPH decides that no valid BOC is being received on the FDL. The originating quadrant can be determined by reading RAM location 7F0. NEW HDLC PACKET RECEIVED (10, 11, 12, OR 13) This message is sent when the S/UNI-MPH is finished receiving a new HDLC packet. A separate code is assigned to each originating quadrant. The packet length, channel status and packet data can be read from the quadrant's RFDL receive buffer. FINISHED TRANSMITTING HDLC PACKET (20, 21, 22, OR 23) This message is sent when the S/UNI-MPH has finished transmitting an HDLC packet. This allows the host to know when it may construct another packet for transmission. A separate code is assigned to each originating quadrant. IN-BAND LINE-LOOPBACK-ACTIVATE DETECTED (14) This message is sent when the S/UNI-MPH detects a standardized in-band LineLoopback-Activate request. The originating quadrant can be determined by reading RAM location 7F0. The PIC16C74 will automatically respond to the request, putting the quadrant into a Line Loopback mode. 17 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface IN-BAND LINE-LOOPBACK-DEACTIVATE DETECTED (15) This message is sent when the S/UNI-MPH detects a standardized in-band LineLoopback-Deactivate request. The originating quadrant can be determined by reading RAM location 7F0. The PIC16C74 will automatically respond to the request, taking the quadrant out of the Line Loopback mode. LOSS OF CLOCK ACTIVITY ASSERTED (25) This message is sent when the S/UNI-MPH indicates a loss of clock activity on any of the XCLKA, RCLKIxA, TCLKIA, TFCLKA, RFCLKA inputs. The PIC microcontroller polls the clock activity register in the S/UNI-MPH (register 0EH) to determine clock status. The message is only sent once. LOSS OF CLOCK ACTIVITY CLEARED (26) This message is sent when the S/UNI-MPH indicates clock activity has been restored to all of the XCLKA, RCLKIxA, TCLKIA, TFCLKA, RFCLKA inputs. The PIC microcontroller polls the clock activity register in the S/UNI-MPH (register 0EH) to determine clock status. LOSS OF CELL DELINEATION ASSERTED (27) This message is sent when the S/UNI-MPH detects a loss of cell delineation. (The receive cell processor of the S/UNI-MPH has been out of cell delineation for the number of cell periods determined by register 84H of the S/UNI-MPH). The originating quadrant can be determined by reading RAM location 7F0. LOSS OF CELL DELINEATION CLEARED (28) This message is sent when the S/UNI-MPH detects that cell delineation has been regained. (The receive cell processor of the S/UNI-MPH has been in cell delineation for the number of cell periods determined by register 84H of the S/UNI-MPH). The originating quadrant can be determined by reading RAM location 7F0. TRANSMIT FIFO OVERRUN (29) This message is sent when the S/UNI-MPH detects that the transmit cell FIFO has overrun. The originating quadrant can be determined by reading RAM location 7F0. RECEIVE FIFO OVERRUN (2A) This message is sent when the S/UNI-MPH detects that the receive cell FIFO has overrun. The originating quadrant can be determined by reading RAM location 7F0. 18 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CHANGE OF CELL ALIGNMENT (2B) This message is sent when the S/UNI-MPH detects a change of cell alignment. The originating quadrant can be determined by reading RAM location 7F0. PMON STATISTICS UPDATED (80) This message is sent following the update of PMON statistics in shadow RAM. REG TRANSFER COMPLETE (FF) This message is sent to indicate that the requested register read of the S/UNI-MPH or QDSX has been completed. PIC16C74 Microcontroller The Microchip PIC16C74 is a low-cost, high-performance, CMOS, fully-static EPROMbased 8-bit microcontroller. It employs a Harvard RISC-like architecture with 14-bit instruction words. Its two stage instruction pipeline allows most instructions to be executed in a single cycle. The PIC16C74 has enhanced core features, an eight-level deep stack, and multiple internal and external interrupt sources. The PIC16C74 has 192 bytes of on-chip user RAM and a 4k by 14-bit EPROM for program memory. It has 33 I/O pins, each of which can source/sink 25mA. The PIC16C74 has multiple timers which can be configured to generate internal interrupts at variable intervals. The PIC16C74 also has a number of peripheral features (A/D converters, capture/compare/PWM modules, and two serial ports) which are not used in this reference design. In the S/UNI-MPH Module, the PIC16C74 is devoted to the local maintenance, performance monitoring, failure monitoring and diagnostic functions related to the four DS1 physical layers terminated by the PM7344 S/UNI-MPH and PM4314 QDSX. 19 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Firmware Example firmware for the PIC16C74 is included in Appendix D. The firmware was developed in Assembly language using Microchip's PC-hosted symbolic assembler, MPASM (v1.30.01), available free from Microchip's bulletin board (MCHIPBBS on Compuserve) or Web site (http://www.microchip.com). The firmware was simulated using MPSIM (v5.20), also available free from Microchip. The PIC16C74 can be programmed on universal programmers from Sprint and Data I/O. Additionally, Microchip sells low cost programmers for this device. External Memory Accesses The PIC16C74 does not have a microprocessor bus suitable to access registers and memory within the S/UNI-MPH and dual-port RAM. Therefore I/O pins on the PIC16C74 are defined to act as the address bus, data bus, chip selects, RDB, WRB and other signals necessary. Since the PIC16C74 is only accessing three external devices, generates the chip selects instead of relying on external decode logic. Figure 1 shows a block diagram of the connections. Figure 1. Block Diagram of PIC16C74 Connections micro bus ( addres s , dat a, contr ol, chip s elect s ) micro bus S/UNI MPH Dual- Por t RAM Interrupts t o Host P Interrupts C Interrupts QDSX Interrupts The firmware in Appendix D includes subroutines that operate dedicated I/O pins as the micro bus during external accesses. Since the interrupt service routines will often alternate between accessing the S/UNI-MPH, QDSX, and the dual-port RAM, it saves instruction cycles to have separate subroutines dedicated to each, where the address would be taken from different pre-defined registers. There are six general access routines: RD_MPH, RD_RAM, RD_QDSX, WR_MPH, WR_RAM, and WR_QDSX. All four routines share a common Data register so that data transfers could be optimized. 20 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Initialization The firmware initializes the S/UNI-MPH to enable the appropriate interrupts, set the framing format, configure the interfaces, set the timing options, and initialize the HDLC serial controllers and the signaling blocks. The S/UNI-MPH is initialized for Extended Superframe Format (ESF) in all quadrants. The QDSX is initialized in much the same way as the S/UNI-MPH. Many of the features of the QDSX are not enabled, however, as they are already available in the S/UNI-MPH. The dual-port RAM is initialized with the version and revision number of the firmware. The microcontroller-side mailbox is read to clear any spurious interrupt. Finally, the initialization routine enables the interrupts within the PIC16C74, and falls into a main loop. Dual-Port Mailboxes The dual-port RAM contains two mailbox registers, one in each direction, for passing data between the two ports. When the micro bus on one port writes a data byte to its mailbox address, the other port is interrupted. Using these mailboxes, a proprietary messaging scheme can be arranged. These interrupts from the dual-port RAM are processed by the PIC16C74. Datalink Service Routines (RFDL/XFDL) The ESF facility datalink is a 4 kbit/s channel provided for three functions: a remote alarm indication (YELLOW Alarm), a bit-oriented code FEAC channel, and an HDLC datalink. The YELLOW Alarm and FEAC processing are explained in the Maintenance Functions subsection. The PM7344 S/UNI-MPH provides detection and generation of the HDLC packet overhead, by using its internal RFDL and XFDL functional blocks. The RFDL and XFDL functional blocks generate interrupt indications on the common INTB output. The procedures for handling the interrupts from the RFDL and XFDL blocks is explained in the Operations section of the S/UNI-MPH data book. The firmware implements these procedures providing routines for initiating the transmission of packets constructed by the host (using the Start FDL Transmission mailbox command) as well as interrupting the host when a complete packet is received (indicated with the New FDL Packet Received mailbox messages). 21 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Additionally, the firmware automatically constructs and transmits ANSI T1.403 one second performance report packets based on performance monitoring data it has collected. If the firmware is already transmitting a packet, the performance report will be transmitted after the current packet is finished. The performance report functionality is further explained in the Maintenance Functions subsection. Maintenance Functions There are a number of maintenance functions specified in ANSI T1.107, T1.231, and T1.403. These include YELLOW Alarm, Alarm Indication Signal (AIS), RED Alarm, Loopbacks, and Performance Monitoring (including Performance Reports). YELLOW ALARM A DS1 YELLOW Alarm must be sent to the remote DS1 equipment in response to a RED Alarm state. This is performed automatically by the S/UNI-MPH. The firmware automatically interrupts the host when a YELLOW Alarm is detected in a receive channel. ALARM INDICATION SIGNAL (AIS) The AIS must be sent upon loss of originating signal, or when any action is taken that would cause service disruption (such as loopbacks). The firmware will not automatically transmit AIS in response to any condition. However, it will interrupt the host when an AIS is detected in a receive channel. LOSS OF CELL DELINEATION The PIC16C74 firmware alerts the host whenever a loss of cell delineation is indicated by the S/UNI-MPH. Loss of cell delineation is determined by counting the number of cell periods for which the receive cell processor is out of delineation, and comparing to the RXCP LCD Count Threshold, register 84H. LOOPBACKS Loopbacks are used by carriers and customers as a maintenance tool to aid problem resolution. The carrier uses loopbacks for trouble isolation, and the customer uses them for CI-to-CI testing. There are two loopbacks defined by ANSI T1.403: Line and Payload. In SF, only Line Loopback is applicable, but in ESF, both loopbacks apply. Both Line and Payload loopbacks are supported in the S/UNI-MPH. 22 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Superframe (SF) Loopbacks In SF, loopbacks are controlled by in-band signaling. There are two in-band codes defined: Loopback Activate and Loopback Deactivate. The Loopback Activate code is a framed "00001..." repeating pattern. The Loopback Deactivate code is a framed "001..." repeating pattern. The IBCD functional block in the S/UNI-MPH can be configured (during initialization) to look for these patterns and interrupt when one is detected. In response to these interrupts, the firmware enables or disables Line Loopback. Extended Superframe (ESF) Loopbacks In ESF, loopbacks are controlled by bit-oriented codes sent over the facility datalink. (Note some provisions are made for framed or unframed in-band codes to control ESF Line Loopbacks.) There are six bit-oriented codes defined relating to loopbacks: * * * * * * Line-Loopback-Activate: Line-Loopback-Deactivate: Payload-Loopback-Activate: Payload-Loopback-Deactivate: Universal-Loopback-Deactivate: Loopback-Retention: 00001110 11111111 00111000 11111111 00010100 11111111 00110010 11111111 00100100 11111111 00101010 11111111 The RBOC TSB in the S/UNI-MPH can detect any valid bit-oriented code, generating an interrupt when one is detected or removed. The Line Loopback should not be activated until the Line-Loopback-Activate code is removed, so that the activate code is not looped back to the network interface (NI). Payload Loopback can be activated immediately on detection of the Payload-LoopbackActivate code since the datalink is regenerated -- hence the bit-oriented codes will not be looped back. The deactivation for both loopbacks can be accomplished in several ways: * * * upon detection of the Universal-Loopback-Deactivate code upon detection of AIS upon the receipt of two occurrences of the one-second performance report messages separated by uninterrupted IDLE code (this is not implemented in firmware). Additionally, the Loopback-Retention code is optionally sent in framed test signals during loopbacks as a positive confirmation of the presence of a Line Loopback. The firmware responds to the loopback codes as required. To transmit loopback codes the host should use the Start BOC Transmission mailbox command. 23 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Performance Monitoring All the DS1 performance monitoring parameters required by ANSI T1.231 are available within registers of the S/UNI-MPH. Therefore, with a timer interrupt setting the accumulation interval, the PIC16C74 can transfer all the performance monitoring indicators and parameters to known memory locations in the dual-port RAM. The host system may then process these parameters. In addition to the performance report, the firmware collects cell performance counters from the S/UNI-MPH and copies them to dual port RAM for use by the host. Additionally, ANSI T1.403 specifies that a performance report should be sent once each second using a bit-assigned structure within a HDLC packet transmitted over the facility datalink. Therefore, a timer interrupt is enabled within the microcontroller to interrupt once each second. The service routine for the timer interrupt collects the required performance parameters and constructs performance report packets which are then automatically transmitted. The PIC16C74 indicates when it is finished its one second functions by sending the PMON Statistics Updated mailbox message. The performance report packet is 15 octets long, including the opening and closing HDLC Flags. The format is shown in Table 7. Table 7. Performance Report Packet Format Octet No. 1 2 3 4 5, 6 7, 8 9, 10 11, 12 13, 14 15 Octet Contents 01111110 00111000 00111010 00000001 00000011 Variable Variable Variable Variable Variable 01111110 Interpretation Opening HDLC Flag From CI: SAPI=14, C/R=0, EA=0 From NI: SAPI=14, C/R=1, EA=0 TEI=0, EA=1 Unacknowledged Frame Data for latest second (T') Data for previous second (T'-1) Data for earlier second (T'-2) Data for earlier second (T'-3) CRC-16 Frame Check Sequence (FCS) Closing HDLC Flag The format for each second's two octets of data (transmitted right to left) is shown in Table 8. 24 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Table 8. Performance Report Data Byte Structure G3 FE Where LV SE G4 LB U1 G1 U2 R G5 G2 SL Nm G6 NI G1=1 indicates that exactly one CRC Error Event occurred during the interval, G2=1 indicates that between two and five (inclusive) CRC Error Events occurred during the interval, G3=1 indicates that between six and ten (inclusive) CRC Error Events occurred during the interval, G4=1 indicates that between 11 and 100 (inclusive) CRC Error Events occurred during the interval, G5=1 indicates that between 101 and 319 (inclusive) CRC Error Events occurred during the interval, G6=1 indicates that more than 319 CRC Error Events occurred during the interval, SE=1 indicates that one or more Severely Errored Framing Events occurred during the interval, FE=1 indicates that one or more Frame Sync Bit Error Events occurred during the interval, LV=1 indicates that one or more Line Code Violation Events occurred during the interval, SL=1 indicates that one or more Slip Events occurred during the interval. This bit is always 0 for the S/UNI-MPH. LB=1 indicates that Payload Loopback is active, U1, U2=0 under study for synchronization, R=0 Reserved NmNI One-second report modulo-4 counter 25 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface IMPLEMENTATION DESCRIPTION The schematic diagram of the S/UNI-MPH Module is contained in Appendix C. This section explains that schematic diagram. Hardware The S/UNI-MPH Module schematic shows four main functional blocks: a PIC16C74 microcontroller, dual-port RAM, a PM4314 QDSX, and a PM7344 S/UNI-MPH. Additionally, the schematic contains connectors, timing sources and miscellaneous "glue" circuitry. PIC16C74 Microcontroller Figure 2 shows how the I/O pins of the PIC16C74 have been defined for this reference design. Figure 2. PIC16C74 Port Map unused unused bit 7 LED 4 bit 7 6 LED 3 6 QDSX CE 5 LED 2 5 RAM CE 4 RAM INT 4 MPH CE 3 LED 1 3 A10 2 A9 1 A8 0 EXT. INT 0 PORTA PORTB unused 2 BUSY 1 PORTC bit A7 7 A6 6 A5 5 A4 4 A3 3 A2 2 A1 1 A0 0 PORTD bit D7 7 D6 6 D5 5 D4 4 D3 3 D2 2 D1 1 D0 0 PORTE bit unused unused unused unused 7 6 5 4 unused unused 3 2 WRB 1 RDB 0 26 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Although the PIC16C74 is a simple microcontroller to program, there are some issues which can cause difficulties for the first-time programmer. Here is a list to be aware of: * The internal register space (data memory) is partitioned into 2 banks. Accessing any particular register requires that the bank bit (bit 5 of the STATUS register) be set accordingly prior to the access. Care must be taken to select the register in the right bank, otherwise bugs which are hard to isolate will occur. Care must also be taken to preserve the state of the bank bit during interrupts. The internal program memory is partitioned into 2 pages. The page that is currently being executed is specified by the page bit (bit 3 of the PCLATH register). When a branch or call is made, the page bit is copied into the program counter. When making cross-page subroutine calls, the page bit must be set according to the location of the subroutine. The entire program counter is pushed onto the stack when a call is made, so when returning there is no need to program the page bit. This means that if a subroutine which manipulates the page bit is called, the state of the page bit may not be known upon return from that subroutine. Therefore, it is good programming practice to explicitly restore the page bit upon returning from a cross-page subroutine call to reflect the page from which the call was made. * The PIC16C74 has four I/O pins (bits 4-7 of PORTB) which have an interrupt-onchange feature. They can be used as edge-triggered external interrupts. Each time the port is read (with any read or read-modify-write instruction) the state of these pins is latched into comparison logic. If at any time there is a pin transition such that a mismatch between the previous latched value and the current value occurs, an interrupt is asserted. The proper procedure for clearing the mismatch condition is explained in a Microchip application note (document number DS00566A) entitled "Using the Port B Interrupt on Change as an External Interrupt." There is a shortcoming in the interrupt logic of the PIC16C74 which makes it possible that transitions on the pins are occasionally missed. To work around this issue the interrupt-on-change pins should be occasionally polled for changes. * Care must be taken when globally disabling interrupts because there exists the possibility that an interrupt will occur while the global interrupt enable bit is being cleared. To ensure that interrupts have been disabled, the following code fragment is recommended: INTCON, GIE INTCON, GIE DISABLEINTS * DISABLEINTS BCF BTFSC GOTO 27 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ... * Because of complications involving register file bank swapping and preservation of the zero (Z) bit in the STATUS register, the following code fragment is the recommended procedure for state preservation in an interrupt service routine: TEMP_W STATUS, W STATUS, RP0 TEMP_STATUS PCLATH, W TEMP_PCLATH MOVWF SWAPF BCF MOVWF MOVF MOVWF And the following code is recommended to restore the saved registers before returning from an interrupt service routine: MOVF MOVWF SWAPF MOVWF SWAPF SWAPF TEMP_PCLATH, W PCLATH TEMP_STATUS, W STATUS TEMP_W, F TEMP_W, W Dual-Port RAM The dual-port RAM is shared by the host system and the local PIC16C74 microcontroller. The PIC16C74 performs all the local maintenance functions (including termination of the facility datalink), while the dual-port RAM is used to pass information to and from the host system. This arrangement greatly reduces the real-time burden on the host system. The dual-port RAM holds, as a minimum, the following information: * * * * packets received by the S/UNI-MPH over the ESF facility datalink packets to be transmitted by the S/UNI-MPH over the ESF facility datalink, including T1.403 performance reports constructed by the PIC16C74. status of the S/UNI-MPH. This includes performance monitoring indications and parameters as specified in ANSI T1.231. channel-associated signaling for each of the received DS0 channels. Each S/UNI-MPH Module has been given 2 kB of space because they must accumulate information on four S/UNI-MPH channels. For example, permanent allocation of 128 bytes per facility datalink (for each of transmit and receive) uses up 1 kB alone. The remaining 1 kB of memory should be sufficient for the status and performance monitoring information. 28 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface The two ports on the dual-port RAM are denoted the "Left" and "Right" ports. In this design, the Left Port is connected to the 100-pin connector which carries the host microprocessor bus (which is decoded, de-multiplexed and buffered on the D3MX Module). The Right Port is connected to the PIC16C74's microprocessor bus (shared with the microprocessor port of the S/UNI-MPH). The two ports are entirely independent from each other and allow asynchronous Read and Write accesses from either port. Each port also has an interrupt indication line used for processing a "mailbox" communications channel within the dual-port RAM. Each port has a memory location, which, when it is written to, alerts the other port via the interrupt indication signal. Therefore, a protocol can be used to pass information through these mailboxes. Using the mailboxes allows: * * * * the host to "peek" and "poke" registers in the S/UNI-MPH and QDSX even though it is not directly connected to their microprocessor ports, the host to initiate different configuration routines, the host to initiate different diagnostic routines, and the PIC16C74 to interrupt the host during alarm conditions and when HDLC packets or BOCs are received on the ESF datalink. S/UNI-MPH Functional Block The S/UNI-MPH is a full-featured quadruple ATM User Network Interface which provides most standard DS1 framing functions and performance monitoring. The full register set of the S/UNI-MPH, including Test Mode registers are accessible to the PIC16C74 block. For a full description of these registers, refer to the S/UNI-MPH Data Book (PMC-940873). The backplane signals of the S/UNI-MPH are connected to SCI-PHY multi-PHY ATM Cell bus, where the transport stream can be further processed. QDSX Functional Block The QDSX is a full-featured quadruple T1/E1 line interface unit which provides a G.703compliant interface for 1544 kbit/s and 2048 kbit/s rates. The full register set of the QDSX, including Test Mode registers are accessible to the PIC16C74 block. For a full description of these registers, refer to the QDSX Data Book (PMC-950739). In this reference design, the QDSX is being used solely to provide a DSX-1 interface for the four duplex DS-1 serial data streams. 29 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Line Interface Circuitry The line interface circuitry consists of the transformers, connectors and passive networks necessary to interface the QDSX device to cables carrying G.703-compliant 1544 kbit/s signals. This circuitry reflects recommendations in the QDSX data book. The transformer shown is a new product, the T1008 from Pulse Engineering. Other manufacturers which produce suitable transformers are BH Electronics, Filtran, Midcom, and Schott. The characteristics of the transformer should match those recommended in the QDSX data book. Timing Distribution The high-speed timing to the S/UNI-MPH Module is sourced from an on board oscillator, or optionally from the host 100-pin connector. The Utopia interface timing is sourced from the 100-pin connector P2. The S/UNI-MPH and QDSX require a 37.056MHz high-speed clock. The PIC16C74 requires a high-speed clock, with 20MHz being the maximum frequency. It is recommended that all clocks be sourced from a host circuit, since that provides the lowest cost solution. 100-Pin Connector P1: Host Interface This 100-pin connector is used to connect the S/UNI-MPH Module to a Host device. This connector carries a microprocessor control, address, and data bus, as well as power to the S/UNI-MPH Module. The signals are defined in the following table. In Table 9, the signal type is one of: I (input), O (output), I/O (bi-directional), N/C (noconnect), PWR (power), or GND (ground). The direction of the signal is with reference to this design. Table 9. 100-Pin P1Connector: Host Interface Pin Definitions Pin Name GND N/C INTB TFPI Type GND N/C O I Pin A1, A2 A3 A4 A5 Function Ground No connection Interrupt indication (active low). Transmit frame position. This is an 8kHz signal used to synchronize the frame alignment of the framer backplanes for synchronous switching applications. Transmit clock input. This is a clock (either 1.544MHz or 2.048MHz) used to synchronize the timing of the framer backplanes for synchronous switching applications. Ground TCLKI I A6 GND GND A7, A8 30 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Pin Name N/C VCC N/C GND N/C N/C GND N/C N/C GND N/C N/C GND N/C N/C GND N/C N/C GND N/C N/C GND N/C N/C VDD N/C RSTB N/C N/C GND A[3:0] GND A[5, 4] VDD A[7, 6] GND A[10:8] N/C GND N/C GND RWB N/C VDD CSB N/C GND Type N/C PWR N/C GND I I GND I I GND I I GND I I GND O O GND O O GND O O PWR N/C I O O GND I GND I PWR I GND I N/C GND N/C GND I N/C PWR I N/C GND Pin A9-A14 A15, A16 A17, A18 A19, A20 A21 A22 A23, A24 A25 A26 A27, A28 A29 A30 A31, A32 A33 A34 A35, A36 A37 A38 A39, A40 A41 A42 A43, A44 A45 A46 A47, A48 A49 A50 A51 A52 A53, A54 A55-A58 A59, A60 A61, A62 A63, A64 A65, A66 A67, A68 A69-A71 A72 A73, A74 A75-A78 A79, A80 A81 A82 A83, A84 A85 A86 A87, A88 Function No connection +5V No connection Ground No connection No connection Ground No connection No connection Ground No connection No connection Ground No connection No connection Ground No connection No connection Ground No connection No connection Ground No connection No connection +5V No connection Hardware Reset (active low) No connection No connection Ground Address Bus [3:0] Ground Address Bus [5, 4] +5V Address Bus [7, 6] Ground Address Bus [10:8] No connection Ground No connection Ground Read/Write Bar signal of the microprocessor control bus. No connection +5V Chip Select (active low). Selects the dual-port RAM's Left Port on the S/UNI-MPH Module for microprocessor access. No connection Ground 31 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Pin Name D[3:0] GND D[7:4] XCLK EXT MCLK Type I/O GND I/O I I Pin A89-A92 A93, A94 A95-A98 A99 A100 Function Data Bus [3:0] Ground Data Bus [7:4] High-Speed Clock (37.056MHz) for S/UNI-MPH High-Speed Clock (20.000MHz) for PIC16C74 100-Pin Connector P21: SCI-PHY Interface This 100-pin connector is used to connect the S/UNI-MPH Module to a SCI-PHY MultiPHY device such as the RCMP reference design. This connector carries an 8-bit bidirectional PHY bus interface and power for optional use by the devices on the S/UNIMPH Module. In Table 10, the signal type is one of: I (input), O (output), I/O (bi-directional), N/C (noconnect), PWR (power), or GND (ground). The direction of the signal is with reference to this design. Table 10. 100-Pin Connector P21: SCI-PHY Interface Pin Definitions Pin Name GND TDAT[0] TDAT[4] TDAT[1] TDAT[5] VDD_D TDAT[2] TDAT[6] TDAT[3] TDAT[7] GND TXPRTY TSOC GND GND N/C N/C GND TFCLK N/C GND GND N/C GND GND RDAT[4] RDAT[0] Type GND I I I I PWR I I I I GND I I GND GND N/C N/C GND I N/C GND GND N/C GND GND O O Pin A1, A2 A3 A4 A5 A6 A7, A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20,A21 A22 A23 A24, A25 A26 A27 A28 A29 A30 A31 Function Ground Transmit Cell Data Transmit Cell Data Transmit Cell Data Transmit Cell Data Decoupled VCC Transmit Cell Data Transmit Cell Data Transmit Cell Data Transmit Cell Data Ground Transmit bus parity Transmit start of cell Ground Ground No Connection No Connection Ground Transmit FIFO write clock No Connection Ground Ground No Connection Ground Ground Receive Cell data Receive Cell data 32 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Pin Name RDAT[5] RDAT[1] RXPRTY VDD_D RDAT[2] RDAT[6] RDAT[3] RDAT[7] GND N/C RSOC GND N/C GND RFCLK N/C GND N/C GND N/C VDD_D N/C GND N/C GND N/C GND N/C VDD_D N/C GND N/C GND N/C GND GND Type O O O PWR O O O O GND N/C O GND N/C GND O N/C GND N/C GND N/C PWR N/C GND N/C GND N/C GND N/C PWR N/C GND N/C GND N/C GND GND Pin A32 A33 A34 A35, A36 A37 A38 A39 A40 A41 A42 A43 A44,A45 A46,A47 A58,A49 A50 A51 A52,A53 A54,A55 A56,A57 A58-A62 A63, A64 A65-A68 A69, A70 A71-A74 A75, A76 A77, A80 A81,A82 A83, A84 A85, A86 A87-A89 A90, A91 A92, A93 A94, A95 A96-A98 A99 A100 Function Receive Cell data Receive Cell data Receive bus parity Decoupled VCC Receive Cell data Receive Cell data Receive Cell data Receive Cell data Ground No Connection Receive start of cell Ground No Connection Ground Receive FIFO read clock No Connection Ground No Connection Ground No Connection Decoupled VCC No Connection Ground No Connection Ground No Connection Ground No Connection Decoupled VCC No Connection Ground No Connection Ground No Connection Ground Ground 20-Pin Connector P22: SCI-PHY MultiPHY Interface This 20-pin connector is used to address multiple PHYs on the S/UNI-MPH Module This connector carries addressing and protocol information. In Table 11, the signal type is one of: I (input), O (output), I/O (bi-directional), N/C (noconnect), PWR (power), or GND (ground). The direction of the signal is with reference to this design. 33 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Table 11. 20-Pin Connector P22: Multi-PHY Interface Pin Definitions Pin Name N/C RCAMPH RRDMPH N/C RRA1 N/C RRA0 TWA0 N/C TWA1 N/C TWRMPHB TCAMPH N/C Type N/C I/O I N/C I N/C I I N/C I N/C I I N/C Pin A1, A2 A3 A4 A5-A7 A8 A9 A10 A11 A12 A13 A14-16 A17 A18 A19,20 Function Not Connected Receive multiPHY cell available Active low receive multiPHY read enable Not Connected Receive read address MSB Not Connected Receive read address LSB Transmit write address LSB Not Connected Transmit write address MSB Not Connected active low Transmit MultiPHY write enable Transmit multiPHY cell available Not Connected Firmware Appendix D contains the source code listing of the assembly language firmware used to program the PIC16C74. This section gives a brief overview of the code in Appendix D, describing the functional routines and associated implementation issues. Note: The source code in Appendix D is meant as a proof-of-concept that an inexpensive, simple microcontroller is capable of handling all the physical layer functions associated with the four DS1 channels of a PM7344 S/UNI-MPH device. It is the responsibility of the person(s) using or adapting the example code to ensure that the resulting system operation complies with both standardized and proprietary requirements. The manufacturer of the PIC16C74, Microchip, provides free firmware development software for the assembler (MPASM) and simulator (MPSIM). The firmware for this reference design was developed and tested using that free software. An efficient way of processing events that may have a low frequency of occurrence is to use interrupt-driven routines (instead of polling). The events (alarm conditions, timers, datalink servicing, and dual-port mailbox events) on the S/UNI-MPH and the dual-port RAM will, on average, be low frequency. Therefore, the PIC16C74 firmware developed for this reference design is based on an interrupt-driven scheme. 34 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface When the PIC16C74 detects an interrupt indication on its external interrupt input pins, it determines the source of the interrupt by polling its internal interrupt source register to determine if it was the S/UNI-MPH, QDSX or the dual-port RAM that interrupted. If it was the S/UNI-MPH or QDSX, then the registers of both devices need to be further polled to determine what event caused the interrupt. Once the PIC16C74 has determined the interrupt source, it can jump to a routine specific to that interrupt. The P16C74.INC File The p16C74.inc file is the standard include file for the PIC16C74 provided by Microchip which contains labels for all the special registers and bits of the microcontroller. The MACROS.INC File The macros.inc file defines some macros which are generally useful when using the PIC16C74. MACROS Table 12 describes the macros defined in the macros.inc file. Table 12. Macros in MACROS.INC Macro BANK0 BANK1 PAGE0 PAGE1 INTSOFF Arguments none none none none none Description Selects the Bank 0 register space. Selects the Bank 1 register space Selects Page 0 of program memory Selects Page 1 of program memory Disables all interrupts by clearing the global interrupt enable, and testing to ensure that it is cleared. Enables all interrupts by setting the global interrupt enable. INTSON The MPH.ASM File none The mph.asm file is the main source file containing the macros, constants and routines specific to this reference design. 35 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANTS The first portion of the mph.asm code contains a number of CBLOCK and CONSTANT statements which assign labels to the following: * * * * * * user registers within the Bank 0 register space. external LEDs driven by bits in the Port B register. S/UNI-MPH direct access registers. QDSX direct access registers. S/UNI-MPH and QDSX indirect access registers. dual-port RAM memory locations as per memory map Following this are CONSTANT statements defining dual-port RAM mailbox codes for host to microcontroller and microcontroller to host communication and FEAC bit-oriented codes. Also included here are a number of miscellaneous constant definitions whose purpose is explained in the code. MACROS Table 13 describes the macros used to perform I/O operations with the S/UNI-MPH, QDSX, and the dual-port RAM. Table 13. Description of Macros in MPH.ASM Macro WR_RAM WR_RAM_L Arguments address, value Description Writes value (byte) to the address in the dual-port RAM. Only the lower 11 bits of address are used. Writes value (byte) to quadrant specific RAM. Only the lower 7 bits are used, the upper 4 bits in the RAM address register (bit 7 of ADDR_RAM_LO and bits 0-3 of ADDR_RAM_HI) must be setup prior to invoking this macro. Writes the value in the data register (DATA_REG) to the address in the dual-port RAM. Only the lower 11 bits of the address argument are used. Writes the value in the data register to quadrant specific RAM. Only the lower 7 bits are used, the upper 4 bits in the RAM address register must be setup prior to invoking this macro. Writes value (byte) to the register in the MPH. Only the lower 9 bits of the register argument are used. Writes value (byte) to a MPH register in a particular quadrant. Only the lower 7 bits are used, the upper 2 bits in the MPH address register (bit 7 of ADDR_MPH_LO and bit 0 of ADDR_MPH_HI) must be setup prior to invoking this macro. register, value WR_RAM_D address WR_RAM_DL register WR_MPH WR_MPH_L register, value register, value 36 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Macro WR_MPH_DL Arguments register WR_QDSX WR_QDSX_L register, value register, value WR_QDSX_DL register RD_RAM address RD_RAM_L register RD_MPH register RD_MPH_L register RD_QDSX register RD_QDSX_L register Description Writes the value in the data register to a MPH register in a particular quadrant. Only the lower 7 bits are used, the upper 2 bits in the MPH address register must be setup prior to invoking this macro. Writes value (byte) to the register in the QDSX. Only the lower 9 bits of the register argument are used. Writes value (byte) to a QDSX register in a particular quadrant. Only the lower 6 bits are used, the upper 3 bits in the QDSX address register (bits 6&7 of ADDR_QDSX_LO and bit 0 of ADDR_QDSX_HI) must be setup prior to invoking this macro. Writes the value in the data register to a QDSX register in a particular quadrant. Only the lower 6 bits are used, the upper 3 bits in the QDSX address register (bits 6&7 of ADDR_QDSX_LO and bit 0 of ADDR_QDSX_HI) must be setup prior to invoking this macro. Reads from the address in the dual-port RAM. Only the lower 11 bits of the address argument are used. The value is returned in the data register and the W register. Reads from quadrant specific RAM. Only the lower 7 bits are used, the upper 4 bits in the RAM address register (bit 7 of ADDR_RAM_LO and bits 0-3 of ADDR_RAM_HI) must be setup prior to invoking this macro. The value is returned in the data register and the W register. Reads from the register in the MPH. Only the lower 9 bits of the register argument are used. The value is returned in the data register and the W register. Reads from a MPH register in a particular quadrant. Only the lower 7 bits are used, the upper 2 bits in the MPH address register must be setup prior to invoking this macro. The value is returned in the data register and the W register. Reads from the register in the QDSX. Only the lower 9 bits of the register argument are used. The value is returned in the data register and the W register. Reads from a QDSX register in a particular quadrant. Only the lower 6 bits are used, the upper 3 bits in the QDSX address register must be setup prior to invoking this macro. The value is returned in the data register and the W register. 37 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ROUTINES The following subsections describe each of the routines in the mph.asm file. Main Loop The processor loops infinitely waiting for the 1s time flag to be set. The 1s timer flag is set by a routine which is invoked using the internal timer interrupt. During each loop, it also checks the clock activity monitor for loss of clock activity. It must poll this activity because the clock activity monitor has no interrupt. When the 1s flag is set the processor executes the PMON subroutine, updating performance monitoring statistic and cell performance statistic shadow registers in RAM, and returns to the main loop. Here also the watchdog timer is cleared. Performance Monitoring Shadowing of performance monitoring statistics in the dual-port RAM and construction of one second performance reports (for transmission on the facility datalink) is done by the PMON subroutine. The PMON subroutine writes to the Global PMON Update register of the MPH to trigger the update of performance statistics. The routine then polls the S/UNI-MPH waiting for the PMON block of the S/UNI-MPH to indicate that it has updated the performance statistics. When the S/UNI-MPH is ready, the routine reads the data from the S/UNI-MPH registers to local PIC registers. The GENERATE_PRM subroutine is called to construct the performance report for each quadrant. These performance reports are formatted as specified in the ANSI T1.403 standard. The GENERATE_PRM subroutine reads the performance monitoring statistics from the S/UNI-MPH PMON registers and constructs the octet pair for the last second accordingly. Besides the S/UNI-MPH PMON data, the GENERATE_PRM subroutine also reads the Diagnostics register (to see if the quadrant is currently in a Payload Loopback mode). An eight-byte circular buffer is maintained for each quadrant such that the octets for the previous three seconds are available (in addition to the current second's octets), kept in the proper order. The GENERATE_PRM subroutine also copies the performance monitoring and cell performance statistics to RAM for use by the host system. A modulo-4 counter is copied into the Nl and Nm bits in the performance report. This helps the far end equipment handle packet corruption (the performance reports use an unacknowledged packet protocol). Once constructed, the performance reports will be transmitted by the XFDL interrupt service routine. Because of possible contention between one second performance reports and other host-initiated HDLC packets, if the datalink is busy (i.e. already 38 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface transmitting a packet) then the performance report is flagged pending and will be automatically transmitted when the datalink becomes available. The same protocol is also used when the host initiates packet transmission while a one second performance report is currently in transmission (i.e. the host-initiated packet will pend until the one second performance report is finished transmission). Read Access to S/UNI-MPH The READ_MPH subroutine is used by the RD_MPH and RD_MPH_L macros. The address for the MPH register is copied to the address latch (PORT C and bits 0-2 of PORT A) and the control lines WRB and CSB2 are toggled to perform a read cycle. The data bus (PORT D) is latched into the data register (DATA_REG). Read Access to QDSX The READ_QDSX subroutine is used by the RD_QDSX and RD_QDSX_L macros. The address for the QDSX register is copied to the address latch (PORT C and bits 0-2 of PORT A) and the control lines WRB and CSB3 are toggled to perform a read cycle. The data bus (PORT D) is latched into the data register (DATA_REG). Read Access to Dual-Port RAM The READ_RAM subroutine is used by the RD_RAM and RD_RAM_L macros. The RAM address is copied to the address latch (PORT C and bits 0-2 of PORT A) and the control lines WRB and CSB1 are toggled to perform a read cycle. The data bus (PORT D) is latched into the data register (DATA_REG). Write Access to S/UNI-MPH The WRITE_MPH subroutine is used by the WR_MPH, WR_MPHL and WR_MPH_DL macros. The address for the S/UNI-MPH register is copied to the address latch (PORT C and bits 0-2 of PORT A) and the data register (DATA_REG) is copied to the data bus (PORTD). The control lines WRB and CSB2 are toggled to perform a write cycle. Write Access to QDSX The WRITE_QDSX subroutine is used by the WR_QDSX, WR_QDSXL and WR_QDSX_DL macros. The address for the QDSX register is copied to the address latch (PORT C and bits 0-2 of PORT A) and the data register (DATA_REG) is copied to the data bus (PORTD). The control lines WRB and CSB3 are toggled to perform a write cycle. 39 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Write Access to Dual-Port RAM The WRITE_RAM subroutine is used by the WR_RAM, WR_RAM_D, WR_RAM_DL, and WR_RAM_L macros. The RAM address is copied to the address latch (PORT C and bits 0-2 of PORT A) and the data register (DATA_REG) is copied to the data bus (PORTD). The control lines WRB and CSB1 are toggled to perform a write cycle. Initialize Microcontroller The INIT_MICRO routine makes all control pins inactive, turns off the LEDs and clears the user registers. Timer 0 is configured and the 1 second timer counter is initialized The input/output state of each pin is set. PORT A is configured as a digital input (can be a A/D port). PORT B is read to initialize the interrupt on change logic. Initialize Dual-Port RAM The INIT_RAM routine reads the micro's dual-port RAM mailbox to clear any spurious interrupt. The version and revision numbers are copied to their respective locations in RAM. Initialize S/UNI-MPH The S/UNI-MPH is first initialized by writing to bit 7 of register 0x0C. Note that the bit must be explicitly set and then cleared to complete the reset operation. The INIT_MPH routine is called four times on start-up, once per quadrant. Table 14 shows the S/UNIMPH registers initialized and the value to which they are set. The S/UNI-MPH is initialized for the Extended Superframe Format (ESF) for all channels. Table 14. S/UNI-MPH Initialization Register Values Register Receive configuration Transmit configuration Receive interface config Transmit interface config Transmit timing options Source selection CDRC configuration CDRC interrupt enable ALMI configuration ALMI interrupt status T1 FRMR configuration RBOC Enable IBCD interrupt enable IBCD activate code IBCD decativate code T1 TRAN config Location 00 01 03 04 07 0D 10 11 14 15 1C 30 3D 3E 3F 40 Value 00* 10 04 08 00* 00* 00* 00 10 07 10 05 30 08 24 30 40 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Register RXCP control RXCP framing control RXCP interrupt enable RXCP Idle/unassigned cell pat RXCP Idle/unassigned cell pat RXCP Idle/unassigned cell pat RXCP Idle/unassigned cell pat RXCP Idle/unassigned mask RXCP Idle/unassigned mask RXCP Idle/unassigned mask RXCP Idle/unassigned mask RXCP user cell pattern RXCP user cell pattern RXCP user cell pattern RXCP user cell pattern RXCP user mask RXCP user mask RXCP user mask RXCP user mask TXCP control TXCP interrupt enable TXCP idle cell pattern TXCP idle cell pattern TXCP idle cell pattern TXCP idle cell pattern TXCP idle cell pattern TXCP idle cell payload Location 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 88 89 8A 8B 8C 8D 8E 8F Value 2C 40 20 00* 00* 00* 00* FF FF FF FF 00* 00* 00* 00* FF FF FF FF A4 40 00* 00* 00* 00* 551 6A * This value is already defaulted to upon reset. 1 This is the correct HCS for an unassigned cell header of 00(H1) 00(H2) 00(H3) 00 (H4). The correct HCS for an idle cell header of 00(H1) 00(H2) 00(H3) 01(H4) is 52H. To summarize, the above register settings configure the S/UNI-MPH for T1 single rail, B8ZS, ESF, NRZ, and an idle/unassigned ATM header pattern of 00H, 00H, 00H, 00H, 55H. Initialize QDSX The QDSX is first initialized by writing to bit 7 of register 0x07. Note that the bit must be explicitly set and then reset to complete the reset operation. The INIT_QDSX routine is called four times on start-up, once per quadrant. Table 15 shows the QDSX registers initialized and the value to which they are set. The QDSX is initialized for the Extended Superframe Format (ESF) for all channels. 41 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Table 15. QDSX Initialization Register Values Register CDRC Config IBCD Config XPLS Config IBCD activate code IBCD decativate code Location 10 20 2C 22 23 Value 64 04 40 08 24 Interrupt Service The INTHDLR routine deals with interrupts asserted by the S/UNI-MPH, QDSX, dual-port RAM and internally by timer 0. Each source's interrupt flag is polled in turn, and if asserted the corresponding interrupt service routine is called. Those registers saved on entry into the service routine are restored on exit. The external (S/UNI-MPH or QDSX) interrupt is serviced as long as it is asserted to minimize latency when there are multiple pending S/UNI-MPH or QDSX interrupts. This is important because the interrupts are edge-triggered. The RAM interrupt pin is also polled as a work-around to solve the problem that the interrupt-on-change logic of the PIC16C74 can occasionally miss edges. S/UNI-MPH Interrupt Service The MPH_INT routine determines the source of an S/UNI-MPH interrupt, both quadrant and block, and then branches to the appropriate service routine. ALMI Interrupt Service The ALMI interrupt status register is examined to determine if an AIS, YELLOW alarm, or RED alarm has been asserted or cleared. A message is written to the host's mailbox accordingly. In the case that an AIS has been asserted, all loopbacks are cleared. CDRC Interrupt Service The CDRC interrupt status register is examined to determine if an LOS has been asserted or cleared, or if a pulse density violation has been detected. Response to these interrupts has been commented out of the code to minimize the amount of messages sent to the host. However, it should be noted that the LOS defect will still be integrated to a RED alarm by other firmware. 42 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface FRMR Interrupt Service The FRMR interrupt status register is examined to determine if the quadrant has gone in or out of frame, a framing error or severe framing error has occurred. Response to these interrupts has been commented out of the code to minimize the amount of messages sent to the host. As with the CDRC interrupt service, the OOF defect will still be integrated to a RED alarm by other firmware. Framing errors are counted as performance statistics. RBOC Interrupt Service The RBOC interrupt status register is examined to determine if a valid BOC has been detected or if the channel has gone idle. A message is written to the host's mailbox accordingly. In the case that a new valid BOC has been detected, the BOC is copied to RAM and is tested to see if it is a loopback related request. Line loopback deactivate, payload loopback activate and deactivate and universal loopback deactivate are dealt with immediately. If a line loopback activate request is received, a bit flag is set using the routine QUAD_BIT_SET. In the case the link has gone from transmitting a valid BOC to transmitting flags (idle state) the host is notified via its mailbox. If the line loopback bit flag is set then a line loopback is initiated. IBCD Interrupt Service The IBCD interrupt status register is examined to determine if an in-band line loopback activate or deactivate request has been received. The line loopback is initiated or cleared accordingly and a message is written to the host's mailbox. RFDL Interrupt Service The RFDL Receive Data register is read and stored locally. The RFDL Status register is read to determine if an overrun or abort has occurred. In the case of an overrun the overrun bit in the RAM copy of the RFDL status register is set. If an abort has occurred, the local link status is made inactive and the status and packet length count are reset. If the link has gone from inactive to active then the link status is set to active and the packet length counter is reset in preparation for a new packet. If this is the next byte of a packet currently being received, then the byte is copied into the RAM receive buffer, packet length counter incremented and the end of message bit in the RFDL status register is tested. If this byte is the end of the current message then the CRC error bit and NVB bits of the RAM RFDL status register are updated, local link status made inactive and packet length copied to RAM. If the packet length is greater than 3 (which 43 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface all valid packets with CRC enabled will be) then the host is notified of the new packet through its mailbox. XFDL Interrupt Service An XFDL interrupt will occur when either the XFDL needs another data byte for transmission, or if an underrun has occurred in the XFDL FIFO. When an XFDL interrupt occurs, a flag (in the Q#_FLAGS register) is tested to see whether a performance report or a host-initiated packet is currently being transmitted so that the firmware knows from where to source the data. * If a host-initiated HDLC packet is being transmitted, the XFDL Interrupt Status register is examined to determine if an underrun has occurred. > If an underrun has occurred the XFDL UDR bit is cleared and the packet is restarted (unless retransmission has already been attempted 10 times in which case the firmware will give up attempting to retransmit the packet). Note that the XFDL will automatically transmit an HDLC ABORT sequence during an underrun condition. > If an underrun has not occurred, the data pointer is compared with the packet length to determine if the end of message has been reached. If the end of message has been reached, the EOM bit is set and a flag is tested to see if a performance report is pending. If a report is pending, a flag is programmed to indicate that a performance report is being transmitted. If a report is not pending, the XFDL interrupts are disabled and the FDL busy bit in the flags register is cleared. The host is notified through its mailbox that the host-initiated packet has finished transmitting. If the end of message has not been reached, the next data byte is copied from the dual-port RAM to the XFDL Transmit Data register, and the data pointer is advanced. * If a performance report is being transmitted, the XFDL interrupt status register is examined to determine if an underrun has occurred. > If an underrun occurred, the XFDL UDR bit is cleared and the transmission is aborted. The firmware will not attempt to retransmit the packet because each performance report contains three seconds worth of history (i.e. up to three 44 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface consecutive performance information). reports can be corrupted without losing any > If an underrun has not occurred, a counter variable is examined to determine which octet of the performance report to transmit next. The first three octets (containing the LAPD overhead fields) are constants. The fourth through eleventh octets are taken from the circular buffer. If the eleventh octet has been transmitted then the EOM bit is set and the flags register is tested to see if a hostinitiated HDLC packet is pending. If a host-initiated packet is pending, a flag is programmed to indicate a hostinitiated packet is being transmitted. If a packet is not pending, the XFDL interrupts are disabled and the FDL busy bit in the flags register is cleared. RXCP Interrupt Service The RXCP interrupt status register is examined to determine if a receive FIFO overrun or loss of cell delineation has occurred, and the appropriate mailbox code is sent to the host. TXCP Interrupt Service The TXCP interrupt status register is examined to determine if a transmit FIFO overrun or change of cell alignment has occurred, and the appropriate mailbox code is sent to the host. QDSX Interrupt Service The QDSX_INT routine determines the source of a QDSX interrupt, both quadrant and block, and then branches to the appropriate service routine. DJAT Interrupt Service This routine currently takes no action. CDRC Interrupt Service This routine currently takes no action. LCV Interrupt Service This routine currently takes no action. 45 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PRSM Interrupt Service This routine currently takes no action. IBCD Interrupt Service This routine currently takes no action. XPLS Interrupt Service This routine currently takes no action. RLSC Interrupt Service This routine currently takes no action. Dual-Port Mailbox Interrupt Service The micro's mailbox is read to determine the request issued by the host. If a valid code is read the corresponding routine is executed. Timer Interrupt Service The 3ms flag is set and 1s timer counter decremented. If the 1s counter has reached zero then the 1s flag is also set and the timer LED (LED 4) is toggled. 46 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface APPENDIX A: DESIGN CONSIDERATIONS Power Supply Voltage Transients High currents drawn during IC switching causes power supply voltage transients due to the inductance of the power lines. The magnitude of the noise voltage can be reduced by minimizing the inductance of the power lines and by decreasing the magnitude of the transient currents. The power line inductance can be minimized by using a power plane. The transient currents on the power rails can be minimized by supplying the power from a local source such as a de-coupling capacitor near the circuit drawing the current. The de-coupling capacitance and the inductance of the connection between the capacitor and the power pin determine the noise voltage at the power pin. The effectiveness of the de-coupling capacitor depends on the frequencies of the transients. Large "bulk" de-coupling capacitors are used to supply the low-frequency current variations and the small "noise-bypassing" capacitors are used to supply the highfrequency transient current that is required when the circuit is switching. Ground Noise Return currents and power supply transients during high current consumption produce most of the ground noise. Since ground noise cannot be controlled by de-coupling capacitors, the only way to minimizing the effect of ground noise is to minimize ground impedance. The best way to minimize ground impedance is to use a ground plane. It is not advisable to use ferrite beads in the ground path as this will inhibit the return currents from leaving and raise the ground noise level. Noise-Bypassing at Power Pins The S/UNI-MPH can generate a lot of simultaneous switching noise, especially if the line rate clocks are synchronous. It is important to provide a noise-bypassing capacitor at every power pin so that the switching currents can be supplied locally, thereby reducing the noise introduced into the power plane. Values of Noise-Bypassing Capacitors A rule of thumb is that the bulk noise-bypassing capacitor (placed where the power enters the circuit board) should have 10 times the value of all the noise-bypassing capacitors combined. Capacitors with low internal inductance should be used such as a tantalum electrolytic. Stay away from aluminum electrolytic as their inductances are an order of magnitude larger than tantalum capacitors. 47 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface The noise-bypassing capacitors (placed near the power pins) must be able to supply all the switching current. The minimum capacitance can be calculated by: C = , W9 The transient voltage drop V in the supply voltage is caused by the transient current I occurring over time t. This equation shows that the voltage drop will be minimized as the capacitance is increased. However, using capacitors that are too large should be avoided due to their resonance characteristics. Since all capacitors have some stray inductance in series with the capacitance, there will be a self-resonance at a certain frequency given by the equation: f= 1 2 LC Note that the larger the capacitance (for the same inductance) the lower the resonant frequency. If the capacitor is too large, the self-resonance will be too low to be an effective bypass but if the capacitor is not large enough, there will be insufficient current to supply the transient current during switching. The smallest value capacitor to satisfy the above equations should be used. It is rarely necessary that a capacitor larger than 0.01 F be used. Placement of Noise-Bypassing Capacitors The de-coupling capacitor should be placed as close to the IC power pin as possible reduce the wiring inductance. There are five sources of inductance: the parasitic inductance of the capacitor, the inductance of the wiring between the capacitor and the IC power pin, the power pin lead inductance inside the IC, the ground pin lead inductance inside the IC, and the ground inductance between the IC pin and ground. The capacitor inductance is negligible if the correct capacitor is used. There is no control over the lead frame inductance. To keep the inductance low, both the power lead and the ground lead should be keep as short as possible (less than 1.5 inches). The inductance for a trace is given by: L = 0.005log -1 h H inch 2 w where h is the height between the power or ground lead and the ground plane and w is the width of the power or ground lead. Note that doubling the width of the trace or reducing h will only decrease L approximately by 20%, but decreasing the length by 50% will decrease the inductance by 50%. A typical PCB trace has about 15nH of inductance per inch. 48 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Ferrite Beads Ferrite beads are mainly used on power rails to pass DC current but to attenuate the higher frequency noise that is riding on the DC rail. The impedance of ferrite beads increases with frequency; at DC the ferrite bead is like a short but at higher frequency the impedance of a ferrite bead can increase to over 100 ohms (depending on the bead and frequency). Ferrite beads attenuate high frequency noise from the power supply from getting into a circuit, but they also stop high frequency switching currents required by digital ICs. It is important, therefore, to use proper noise bypass capacitors when using ferrite beads to provide a local source of switching current. Ferrite beads should be avoided on CMOS I/O power pins as the high current switching of the CMOS circuits causes a It noise to be introduced into the power rail. This noise is induced because the ferrite beads "starve" the digital circuitry, causing the voltage to fluctuate locally. Ferrite beads should also be avoided on the ground bus as this inhibits the return currents. Unused CMOS Inputs "Floating" CMOS inputs (those that are left unconnected) may switch unpredictably, causing unwanted noise and power consumption. Therefore, all unused inputs should be connected to their inactive state: to ground or to the power rail (Vcc). Unused bidirectionals should be "pulled" through a series resistor (4.7k or greater) to avoid shortcircuits occuring if the bi-directionals are erroneously configured as outputs. 49 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface APPENDIX B: MATERIAL LIST Item No. Part Name - Value JEDEC Type Reference Designator Qty 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 BANTAM-BASE CAP-.68UF,METAL POLY CAP-0.001UF CAP-100000PF CAP-10000PF CAP-1000PF,NPO_805 CAP-47000PF BANTAM CAP200 SMDCAP805 SMDCAP120 SMDCAP805 SMDCAP805 SMDCAP1206 J91-J98 C37-C40 C8,C9,C27,C29, C30 C12-C19, C21C24,C45-C48 C1-C7,C10, C58-C73 C42-C44,C83 C53-C56 C49-C52 C11,C20,C57 P1,P3 P2 U11 JP1,JP2 L1-L8 U22 U27 U18 U13 U1 J6 U24 R1,R4,R5,R7 8 4 5 16 24 4 4 4 3 2 1 1 2 8 1 1 1 1 1 1 1 4 CAPACITOR POL-0.47UF, 25V, SMDTANCAP_A TANT A CAPACITOR POL-10UF, SMDTANCAP_C 16V,TANT TEH CONN100-AMP_103911-8 AMP_103911-8 CONN20-AMP_103911-2 CY7C136_-BASE HEADER3-BASE INDUCTOR-FB,50, FAIR RITE LED10-RED,25MA,2.1V MPH-BASE AMP_103911-2 PLCC52 JUMPER3 INDUCTOR_FB DIP20_LED PQFP128 OSC_TTL_DIP-20.0000MHZ,100 CRYS14 PPMA OSC_TTL_DIPCRYS14 37.056MHZ,32/50 PPA PIC16C74-BASE PIC16C74 PWRBLOCK_2-BASE QDSX-BASE RESISTOR-0,5% CONN2END PQFP128 SMDRES805 50 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface APPENDIX C: SCHEMATICS 51 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface APPENDIX D: FIRMWARE This appendix contains the source code for the firmware. Note: It is the responsibility of the person(s) using or adapting this code to ensure that the resulting system operation complies with both standardized and proprietary requirements. MACROS.INC file ;******************************************* ;* Commonly used general macro definitions * ;******************************************* ; select BANK 0 internal registers BANK0 MACRO BCF STATUS, RP0 ; select bank 0 (00h-7Fh) ENDM ; select BANK 0 internal registers BANK1 MACRO BSF STATUS, RP0 ; select bank 1 (80h-FFh) ENDM ; select program memory PAGE 0 PAGE0 MACRO BCF PCLATH, 3 ; select page 0 (000h-7FFh) ENDM ; select program memory PAGE 1 PAGE1 MACRO BSF PCLATH, 3 ; select page 1 (800h-FFFh) ENDM ; disable all interrupts INTSOFF MACRO LOCAL CLEAR CLEAR BCF INTCON, GIE ; clear global interrupt enable bit BTFSC INTCON, GIE ; make sure it was cleared GOTO CLEAR ; (could have been interrupted) ENDM ; enable all interrupts INTSON MACRO BSF INTCON, GIE ENDM PIC16C74.INC file LIST ; P16C74.INC Standard Header File, Version 1.00 NOLIST Microchip Technology, Inc. ; This header file defines configurations, registers, and other useful bits of 52 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ; information for the PIC16C74 microcontroller. ; the data sheets as closely as possible. These names are taken to match ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; ; ; ; ; 1. Command line switch: C:\ MPASM MYFILE.ASM /PIC16C74 2. LIST directive in the source file LIST P=PIC16C74 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: ;1.00 Date: Reason: 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C74 MESSG "Processor-header file mismatch. ENDIF Verify selected processor." ;========================================================================== ; ; Register Definitions ; ;========================================================================== W F EQU EQU H'0000' H'0001' ;----- Register Files-----------------------------------------------------INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU H'0000' H'0001' H'0002' H'0003' H'0004' H'0005' H'0006' H'0007' H'0008' H'0009' H'000A' H'000B' H'000C' H'000D' H'000E' H'000F' H'0010' 53 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 OPTION_REG TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PCON PR2 SSPADD SSPSTAT TXSTA SPBRG ADCON1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU H'0011' H'0012' H'0013' H'0014' H'0015' H'0016' H'0017' H'0018' H'0019' H'001A' H'001B' H'001C' H'001D' H'001E' H'001F' H'0081' H'0085' H'0086' H'0087' H'0088' H'0089' H'008C' H'008D' H'008E' H'0092' H'0093' H'0094' H'0098' H'0099' H'009F' ;----- STATUS Bits -------------------------------------------------------IRP RP1 RP0 NOT_TO NOT_PD Z DC C EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- INTCON Bits -------------------------------------------------------GIE PEIE T0IE INTE RBIE T0IF INTF RBIF EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- PIR1 Bits ---------------------------------------------------------PSPIF ADIF RCIF TXIF EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' 54 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface SSPIF CCP1IF TMR2IF TMR1IF EQU EQU EQU EQU H'0003' H'0002' H'0001' H'0000' ;----- PIR2 Bits ---------------------------------------------------------CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------T1CKPS1 T1CKPS0 T1OSCEN NOT_T1SYNC T1INSYNC TMR1CS TMR1ON EQU EQU EQU EQU EQU EQU EQU H'0005' H'0004' H'0003' H'0002' H'0002' H'0001' H'0000' ; Backward compatibility only ;----- T2CON Bits --------------------------------------------------------TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 EQU EQU EQU EQU EQU EQU EQU H'0006' H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- SSPCON Bits -------------------------------------------------------WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- CCP1CON Bits ------------------------------------------------------CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 EQU EQU EQU EQU EQU EQU H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- RCSTA Bits --------------------------------------------------------SPEN RX9 RC9 NOT_RC8 RC8_9 SREN CREN FERR OERR EQU EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0006' H'0006' H'0006' H'0005' H'0004' H'0002' H'0001' ; Backward compatibility only ; Backward compatibility only ; Backward compatibility only 55 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface RX9D RCD8 EQU EQU H'0000' H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 EQU EQU EQU EQU EQU EQU H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- ADCON0 Bits -------------------------------------------------------ADCS1 ADCS0 CHS2 CHS1 CHS0 GO NOT_DONE GO_DONE ADON EQU EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' H'0003' H'0002' H'0002' H'0002' H'0000' ;----- OPTION Bits -------------------------------------------------------NOT_RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- TRISE Bits --------------------------------------------------------IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISE0 EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' H'0002' H'0001' H'0000' ;----- PIE1 Bits ---------------------------------------------------------PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0005' H'0004' H'0003' H'0002' H'0001' H'0000' ;----- PIE2 Bits ---------------------------------------------------------CCP2IE EQU H'0000' 56 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ;----- PCON Bits ---------------------------------------------------------NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------D I2C_DATA NOT_A NOT_ADDRESS D_A DATA_ADDRESS P I2C_STOP S I2C_START R I2C_READ NOT_W NOT_WRITE R_W READ_WRITE UA BF EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU H'0005' H'0005' H'0005' H'0005' H'0005' H'0005' H'0004' H'0004' H'0003' H'0003' H'0002' H'0002' H'0002' H'0002' H'0002' H'0002' H'0001' H'0000' ;----- TXSTA Bits --------------------------------------------------------CSRC TX9 NOT_TX8 TX8_9 TXEN SYNC BRGH TRMT TX9D TXD8 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU H'0007' H'0006' H'0006' H'0006' H'0005' H'0004' H'0002' H'0001' H'0000' H'0000' ; Backward compatibility only ; Backward compatibility only ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------PCFG2 PCFG1 PCFG0 EQU EQU EQU H'0002' H'0001' H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3F8F' 57 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface _CP_75 _CP_50 _CP_OFF _PWRTE_ON _PWRTE_OFF _WDT_ON _WDT_OFF _LP_OSC _XT_OSC _HS_OSC _RC_OSC LIST EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU H'3F9F' H'3FAF' H'3FBF' H'3FBF' H'3FB7' H'3FBF' H'3FBB' H'3FBC' H'3FBD' H'3FBE' H'3FBF' MPH.ASM file ;******************************************************* ;* S/UNI-MPH Module PIC Firmware * ;* Version 0.00 : Octoher 1, 1996 * ;* Author: Greg Wynans * ;* Revision history: * ;* 960924: Interface routines added for QDSX * ;* * ;* Copyright 1996 PMC-Sierra, Inc * ;******************************************************* TITLE "PIC ASSEMBLY SOURCE CODE FOR MPH MODULE" PROCESSOR PIC16C74 INCLUDE "p16c74.inc" INCLUDE "macros.inc" ERRORLEVEL 0,-306,-302 ; suppress page-crossing and ; argument out of range messages ;********************************* ;* SPECIAL FEATURES FUSE SETTING * ;********************************* __CONFIG _CP_OFF&_PWRTE_ON&_WDT_OFF&_XT_OSC ;************************ ;* WR_MPH_L DEFINITIONS * ;************************ ;********************** ;* Revision constants * ;********************** CONSTANT CONSTANT __IDLOCS VER=0x00 REV=0x00 0x0000 ; version number ; revision number ;****************************************** ;* PIC microcontroller register constants * ;****************************************** ; define BANK 0 of microcontroller user registers 58 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface REGISTERS CBLOCK 20 DATA_REG ADDR_MPH_HI ADDR_MPH_LO ADDR_RAM_HI ADDR_RAM_LO TEMP_W TEMP_STATUS TEMP_PCLATH TIME_COUNT_H TIME_COUNT_L SCRATCH WORK WORK1 WORK2 ; WORK3 ; WORK4 ; WORK5 ; ; TIMEFLAG QUADRANT ; ; ; data register for micro-bus transfers ; MSB of address reg for MPH accesses ; LSB of address reg for MPH accesses ; MSB of address reg for RAM accesses ; LSB of address reg for RAM accesses ; temporary copy of working register ; temporary copy of status register ; temporary copy of PCLATH register ; MSB of 1 second timer counter ; LSB of 1 second timer counter ; used as a macro scratch pad and general reg. ; general working register ; general working register ; general working register NOT to be used in interrupt handling ; general working register NOT to be used in interrupt handling ; general working register NOT to be used in interrupt handling ; general working register NOT to be used in interrupt handling NOTE that SETUP_MADDR uses this register ; bit 0: set every sec. by timer int. ; used to store the interrupting quadrant (0-3) is set at the beginning of the MPH int. handler and is used through the routine INT1, INT2 ; first and second interrupt source ; from the MPH. INT1 is also used for QDSX INT_STATUS ; interrupt status byte for a block in MPH or QDSX TEMP_RFDL_DATA ; stores data byte read from MPH TEMP_RFDL_STATUS ; stores status byte read from MPH INT_STATUS_SP ; temporary copy of INT_STATUS TEMP_DATA_REG ; temporary copy of DATA_REG TEMP_FSR ; temporary copy of FSR reg PRM_COUNTER ; PMON report message modulo 4 counter Q1_FLAGS ; quadrant 1 bit flags (see bit field constants) Q2_FLAGS ; quadrant 2 bit flags Q3_FLAGS ; quadrant 3 bit flags Q4_FLAGS ; quadrant 4 bit flags SEF ; indicate SEF. bit n set if Qn has SEF (for PMON) SEFQUAD ; indicate quadrant with bit n for Qn CLKSTAT ;indicate status of clock for clock activity monitoring ADDR_QDSX_HI ; MSB of address reg for QDSX accesses ADDR_QDSX_LO ; LSB of address reg for QDSX accesses ENDC ; Bit field for quadrant bit flags CBLOCK 0 RFDL_ACTIVE ; is this quadrant's RFDL block active? LL_REQ ; used to store a line loopback request ; until link is idled XFDL_BUSY ; is this quadrant's XFDL busy transmitting ; a packet (user or performance report)? XFDL_PENDING ; is a packet pending (user or performance ; report)? XFDL_USR_OR_PRM ; is the currently transmitting packet 59 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ; a user packet or a performance report? ; 0 = user, 1 = PRM ENDC CBLOCK 40 Q1_RFDL_STAT Q2_RFDL_STAT Q3_RFDL_STAT Q4_RFDL_STAT Q1_RFDL_PLEN Q2_RFDL_PLEN Q3_RFDL_PLEN Q4_RFDL_PLEN Q1_XFDL_PLEN Q2_XFDL_PLEN Q3_XFDL_PLEN Q4_XFDL_PLEN Q1_XFDL_RPTR Q2_XFDL_RPTR Q3_XFDL_RPTR Q4_XFDL_RPTR Q1_XFDL_TO Q2_XFDL_TO Q3_XFDL_TO Q4_XFDL_TO ENDC CBLOCK 54 Q1_PRM_PTR Q2_PRM_PTR Q3_PRM_PTR Q4_PRM_PTR ENDC CBLOCK 60 Q1_PRM_1B1 Q1_PRM_1B2 Q1_PRM_2B1 Q1_PRM_2B2 Q1_PRM_3B1 Q1_PRM_3B2 Q1_PRM_4B1 Q1_PRM_4B2 Q2_PRM_1B1 Q2_PRM_1B2 Q2_PRM_2B1 Q2_PRM_2B2 Q2_PRM_3B1 Q2_PRM_3B2 Q2_PRM_4B1 Q2_PRM_4B2 Q3_PRM_1B1 Q3_PRM_1B2 Q3_PRM_2B1 Q3_PRM_2B2 Q3_PRM_3B1 Q3_PRM_3B2 Q3_PRM_4B1 Q3_PRM_4B2 Q4_PRM_1B1 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RFDL RFDL RFDL RFDL RFDL RFDL RFDL RFDL XFDL XFDL XFDL XFDL XFDL XFDL XFDL XFDL XFDL XFDL XFDL XFDL packet status packet status packet status packet status packet length packet length packet length packet length packet length packet length packet length packet length RAM pointer RAM pointer RAM pointer RAM pointer packet restart packet restart packet restart packet restart timeout timeout timeout timeout ; ; ; ; pointer pointer pointer pointer to to to to next next next next PRM PRM PRM PRM byte byte byte byte to to to to xmit xmit xmit xmit ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Performance Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report Report 1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4 1 (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte (byte 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 60 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface Q4_PRM_1B2 Q4_PRM_2B1 Q4_PRM_2B2 Q4_PRM_3B1 Q4_PRM_3B2 Q4_PRM_4B1 Q4_PRM_4B2 ENDC ;*************************** ;* PORTB bit LED constants * ;*************************** CONSTANT CONSTANT CONSTANT CONSTANT LED1=3 LED2=5 LED3=6 LED4=7 ; ; ; ; ; ; ; Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant Quadrant 4 4 4 4 4 4 4 Performance Performance Performance Performance Performance Performance Performance Report Report Report Report Report Report Report 1 2 2 3 3 4 4 (byte (byte (byte (byte (byte (byte (byte 2) 1) 2) 1) 2) 1) 2) ; ; ; ; LED1 LED2 LED3 LED4 bit bit bit bit ;**************************** ;* MPH Register constants * ;**************************** ; MPH initialization registers CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT RECV_CONFIG=0x00 XMIT_CONFIG=0x01 RINT_CONFIG=0x03 XINT_CONFIG=0x04 XCLK_OPTION=0x07 CDRC_CONFIG=0x10 FRMR_CONFIG=0x1C XFDL_CONFIG=0x34 RFDL_CONFIG=0x3C IBCD_CONFIG=0x3C T1TRAN_CONFIG=0x40 ALMI_CONFIG=0x14 RXCP_CONTROL=0x70 RXCP_FRAME_CONTROL=0x71 TXCP_CONTROL=0x88 ; see the MPH data book ; for more detailed ; information about these ; registers. ;was XBAS_CONFIG in TQUAD ; MPH interrupt enable registers CONSTANT CDRC_IE=0x11 CONSTANT FRMR_IE=0x1D CONSTANT RBOC_IE=0x30 CONSTANT ALMI_IE=0x15 CONSTANT IBCD_IE=0x3D CONSTANT RFDL_IE=0x39 CONSTANT RXCP_IE=0x72 CONSTANT TXCP_IE=0X89 ; MPH PMON Registers CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT FER1=0x049 FER2=0x149 FER3=0x249 FER4=0x349 FEBEL1=0x04A FEBEL2=0x14A FEBEL3=0x24A 61 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT FEBEL4=0x34A FEBEM1=0x04B FEBEM2=0x14B FEBEM3=0x24B FEBEM4=0x34B CRCL1=0x04C CRCL2=0x14C CRCL3=0x24C CRCL4=0x34C CRCM1=0x04D CRCM2=0x14D CRCM3=0x24D CRCM4=0x34D LCVL1=0x04E LCVL2=0x14E LCVL3=0x24E LCVL4=0x34E LCVM1=0x04F LCVM2=0x14F LCVM3=0x24F LCVM4=0x34F RXCP_UHCSL1=0x64 RXCP_UHCSL2=0x164 RXCP_UHCSL3=0x264 RXCP_UHCSL4=0x364 RXCP_UHCSM1=0x65 RXCP_UHCSM2=0x165 RXCP_UHCSM3=0x265 RXCP_UHCSM4=0x365 RXCP_CHCSL1=0x68 RXCP_CHCSL2=0x168 RXCP_CHCSL3=0x268 RXCP_CHCSL4=0x368 RXCP_CHCSM1=0x69 RXCP_CHCSM2=0x169 RXCP_CHCSM3=0x269 RXCP_CHCSM4=0x369 RXCP_IDLEL1=0x6A RXCP_IDLEL2=0x16A RXCP_IDLEL3=0x26A RXCP_IDLEL4=0x36A RXCP_IDLEM1=0x6B RXCP_IDLEM2=0x16B RXCP_IDLEM3=0x26B RXCP_IDLEM4=0x36B RXCP_RECVL1=0x6C RXCP_RECVL2=0x16C RXCP_RECVL3=0x26C 62 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT RXCP_RECVL4=0x36C RXCP_RECVM1=0x6D RXCP_RECVM2=0x16D RXCP_RECVM3=0x26D RXCP_RECVM4=0x36D TXCP_XMITL1=0x6E TXCP_XMITL2=0x16E TXCP_XMITL3=0x26E TXCP_XMITL4=0x36E TXCP_XMITM1=0x6F TXCP_XMITM2=0x16F TXCP_XMITM3=0x26F TXCP_XMITM4=0x36F ; MPH interrupt status registers CONSTANT INT_ID=0x00D CONSTANT INT1_1=0x008 CONSTANT INT2_1=0x009 CONSTANT ALMI_IS=0x016 CONSTANT CDRC_IS=0x012 CONSTANT FRMR_IS=0x01E CONSTANT RBOC_IS=0x031 CONSTANT IBCD_IS=0x3D CONSTANT RFDL_IS=0x39 CONSTANT XFDL_IS=0x35 ; CONSTANT ELST_IS=0x1D CONSTANT RXCP_IS=0x72 CONSTANT TXCP_IS=0x89 CONSTANT RXCPFC_IS=0x71 ; other MPH registers CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT H1 octet CONSTANT H2 octet CONSTANT H3 octet CONSTANT H4 octet CONSTANT H1 octet CONSTANT H2 octet ; ; ; ; ; ; ; ; ; ; shows which quadrant interrupted interrupt source 1 interrupt source 2 ALMI interrupt status CDRI interrupt status FRMR interrupt status RBOC interrupt/code status IBCD interrupt status RFDL interrupt status XFDL interrupt status ; ELST interrupt enable/status ; RXCP interrupt enable/status ; TXCP interrupt enable/status/control ; RXCP framing control (for LCD int) T1TRAN_ALM=0x41 ; transmit yellow or AIS alarm CLKAMON=0x0E ; clock activity monitor GLOBAL_PMON=0x0C ; global PMON update MSTR_DIAG=0x0A ; master diagnostic reg. DL_OPT=0x02 ; datalink options reg. RFDL_DATA=0x3B ; RFDL reveived data reg. RFDL_STATUS=0x3A ; RFDL received data status reg. XFDL_DATA=0x36 ; XFDL data register XBOC_CODE=0x57 ; XBOC code register IBCD_AC=0x3E ; IBCD activate code IBCD_DC=0x3F ; IBCD deactivate code RXCP_IDLEPAT_H1=0x73 ; RXCP Idle/unassigned pattern RXCP_IDLEPAT_H2=0x74 RXCP_IDLEPAT_H3=0x75 RXCP_IDLEPAT_H4=0x76 RXCP_IDLEMASK_H1=0x77 RXCP_IDLEMASK_H2=0x78 ; RXCP Idle/unassigned pattern ; RXCP Idle/unassigned pattern ; RXCP Idle/unassigned pattern ; RXCP Idle/unassigned mask ; RXCP Idle/unassigned mask 63 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANT H3 octet CONSTANT H4 octet CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT H1 octet CONSTANT H2 octet CONSTANT H3 octet CONSTANT H4 octet CONSTANT H5 octet CONSTANT payload RXCP_IDLEMASK_H3=0x79 RXCP_IDLEMASK_H4=0x7A RXCP_USERPAT_H1=0x7B RXCP_USERPAT_H2=0x7C RXCP_USERPAT_H3=0x7D RXCP_USERPAT_H4=0x7E RXCP_USERMASK_H1=0x7F RXCP_USERMASK_H2=0x80 RXCP_USERMASK_H3=0x81 RXCP_USERMASK_H4=0x82 TXCP_IDLEPAT_H1=0x8A TXCP_IDLEPAT_H2=0x8B TXCP_IDLEPAT_H3=0x8C TXCP_IDLEPAT_H4=0x8D TXCP_IDLEPAT_H5=0x8E TXCP_IDLEPAY=0x8F ; ; ; ; ; RXCP Idle/unassigned mask ; RXCP Idle/unassigned mask RXCP user pattern H1 octet RXCP user pattern H2 octet RXCP user pattern H3 octet RXCP user pattern H4 octet ; RXCP user mask H1 octet ; RXCP user mask H2 octet ; RXCP user mask H3 octet ; RXCP user mask H4 octet ; TXCP Idle/unassigned pattern ; TXCP Idle/unassigned pattern ; TXCP Idle/unassigned pattern ; TXCP Idle/unassigned pattern ; TXCP Idle/unassigned pattern ; TXCP Idle/unassigned cell ;**************************** ;* QDSX Register constants * ;**************************** ; Constants are suffixed with a Q to differentiate from MPH counterparts ; QDSX initialization registers CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT RECV_CONFIGQ=0x00 XMIT_CONFIGQ=0x01 TOPS_CONFIGQ=0x09 TOPS_TM_CONFIGQ=0x0A LCODE_CONFIGQ=0x0B CDRC_CONFIGQ=0x10 DJAT_CONFIGQ=0x1F IBCD_CONFIGQ=0x20 XIBC_CONTROLQ=0x24 PRSG_CONFIGQ=0x27 PRSM_CONTROLQ=0x29 XPLS_CONFIGQ=0x2C XPLS_CONTROLQ=0x2D RSLC_CONFIGQ=0x30 ; see the QDSX data book ; for more detailed ; information about these ; registers. ; QDSX interrupt enable registers CONSTANT CDRC_IEQ=0x11 CONSTANT LCV_PMON_IEQ=0x14 CONSTANT IBCD_IEQ=0x21 CONSTANT RSLC_IEQ=0x31 ; QDSX PMON Registers CONSTANT CONSTANT CONSTANT CONSTANT GLOBAL_PMONQ=0x007 DIAGQ=0x005 MTESTQ=0x006 LCVL1Q=0x01A 64 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT LCVL2Q=0x05A LCVL3Q=0x09A LCVL4Q=0x0DA LCVM1Q=0x01B LCVM2Q=0x05B LCVM3Q=0x09B LCVM4Q=0x0DB PRSML1Q=0x02A PRSML2Q=0x06A PRSML3Q=0x0AA PRSML4Q=0x0EA PRSMM1Q=0x02B PRSMM2Q=0x06B PRSMM3Q=0x0AB PRSMM4Q=0x0EB ; QDSX interrupt status registers CONSTANT INT_IDQ=0x008 ; shows which quadrant interrupted CONSTANT INTQ=0x003 ; interrupt source CONSTANT CDRC_ISQ=0x012 ; CDRC interrupt status CONSTANT LCV_PMON_ISQ=0x014 ; LCV_PMON interrupt status CONSTANT DJAT_ISQ=0x01C ; RBOC interrupt/code status CONSTANT IBCD_ISQ=0x21 ; IBCD interrupt status CONSTANT PRSM_ISQ=0x29 ; PRSM interrupt status CONSTANT XPLS_ISQ=0x2D ; XPLS interrupt status CONSTANT RLSC_ISQ=0x31 ; RLSC interrupt status ; Other QDSX registers CONSTANT IBCD_ACQ=0x22 CONSTANT IBCD_DCQ=0x23 ; IBCD activate code for QDSX ; IBCD deactivate code for QDSX ;****************************************** ;* RAM memory location/register constants * ;****************************************** ; PMON Registers ; these memory locations reflect their MPH counterparts ; see the associated MPH register description for more info. CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT FER1_RAM=0x400 FER2_RAM=0x413 FER3_RAM=0x426 FER4_RAM=0x439 FEBEL1_RAM=0x401 FEBEL2_RAM=0x414 FEBEL3_RAM=0x427 FEBEL4_RAM=0x43A FEBEM1_RAM=0x402 FEBEM2_RAM=0x415 FEBEM3_RAM=0x428 FEBEM4_RAM=0x43B CRCL1_RAM=0x403 CRCL2_RAM=0x416 65 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CRCL3_RAM=0x429 CRCL4_RAM=0x43C CRCM1_RAM=0x404 CRCM2_RAM=0x417 CRCM3_RAM=0x42A CRCM4_RAM=0x43D LCVL1_RAM=0x405 LCVL2_RAM=0x418 LCVL3_RAM=0x42B LCVL4_RAM=0x43E LCVM1_RAM=0x406 LCVM2_RAM=0x419 LCVM3_RAM=0x42C LCVM4_RAM=0x43F RXCP_UHCSL1_RAM=0x407 RXCP_UHCSL2_RAM=0x41A RXCP_UHCSL3_RAM=0x42D RXCP_UHCSL4_RAM=0x440 RXCP_UHCSM1_RAM=0x408 RXCP_UHCSM2_RAM=0x41B RXCP_UHCSM3_RAM=0x42E RXCP_UHCSM4_RAM=0x441 RXCP_CHCSL1_RAM=0x409 RXCP_CHCSL2_RAM=0x41C RXCP_CHCSL3_RAM=0x42F RXCP_CHCSL4_RAM=0x442 RXCP_CHCSM1_RAM=0x40A RXCP_CHCSM2_RAM=0x41D RXCP_CHCSM3_RAM=0x430 RXCP_CHCSM4_RAM=0x443 RXCP_IDLEL1_RAM=0x40B RXCP_IDLEL2_RAM=0x41E RXCP_IDLEL3_RAM=0x431 RXCP_IDLEL4_RAM=0x444 RXCP_IDLEM1_RAM=0x40C RXCP_IDLEM2_RAM=0x41F RXCP_IDLEM3_RAM=0x432 RXCP_IDLEM4_RAM=0x445 RXCP_RECVL1_RAM=0x40D RXCP_RECVL2_RAM=0x420 RXCP_RECVL3_RAM=0x433 RXCP_RECVL4_RAM=0x446 RXCP_RECVM1_RAM=0x40E RXCP_RECVM2_RAM=0x421 RXCP_RECVM3_RAM=0x434 RXCP_RECVM4_RAM=0x447 TXCP_XMITL1_RAM=0x40F TXCP_XMITL2_RAM=0x422 66 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT TXCP_XMITL3_RAM=0x435 TXCP_XMITL4_RAM=0x448 TXCP_XMITM1_RAM=0x410 TXCP_XMITM2_RAM=0x423 TXCP_XMITM3_RAM=0x436 TXCP_XMITM4_RAM=0x449 ; RAM RXDL/XFDL register CONSTANT RAM_CHAN_STAT=0x7E CONSTANT RAM_PCT_LEN=0x7F ; Version/Revision number CONSTANT VER_ADDR=0x7DE CONSTANT REV_ADDR=0x7DF ; FDL channel status ; FDL packet length ; address in RAM to store version # ; address in RAM to store revision # ; Ram comm. registers CONSTANT MAILIN=7FF ; RAM mailbox reg. (HOST->PIC) CONSTANT MAILOUT=7FE ; RAM mailbox reg. (PIC->HOST) CONSTANT INT_QUAD=7F0 ; this register reflects the ; the interrupting quadrant ; from the PIC->HOST CONSTANT RAM_RBOC=7F1 ; storage location BOCs PIC->HOST CONSTANT RAM_XBOC=7E0 ; storage location BOCs HOST->PIC CONSTANT RFDL_QUAD=7F8 ; current RFDL interrupting quad. CONSTANT XFDL_QUAD=7F9 ; current XFDL interrupting quad. CONSTANT SERVICE_QUAD=7FA ; this is the RAM location ; used to communicate from HOST->PIC ; for send boc and idle boc commands ; Register access. registers ; these are the registers in RAM that are used to communicate ; between the MPH and the host when performing individual ; register reads and writes. CONSTANT REG_DATA=0x7FB ; data xfer reg. CONSTANT REG_ADR_LO=0x7FC ; low reg. address CONSTANT REG_ADR_HI=0x7FD ; hi reg. address ; Timer interrupt constants (for 1 second period) CONSTANT ONE_SEC_L=0x01 CONSTANT ONE_SEC_H=0x00 ; FDL Constants CONSTANT MAX_FDL_PLEN=0x7C CONSTANT XFDL_MAX_RESTARTS=0x0A ; max packet length ; max packet Tx restarts ; MailBox communication constants: PIC -> HOST ; the _A postfix indicates an assertion signal ; the _C postfix indicates a clear signal ; eg. LOS_A is the code for LOS asserted ; LOS_C is the code for LOS cleared CONSTANT PDV=0x01 ; pulse density violation CONSTANT LOS_A=0x02 ; LOS asserted CONSTANT LOS_C=0x03 ; LOS cleared CONSTANT INFR_A=0x04 ; INFR asserted CONSTANT INFR_C=0x05 ; INFR cleared CONSTANT AIS_A=0x06 ; AIS asserted CONSTANT AIS_C=0x07 ; AIS cleared CONSTANT YEL_A=0x08 ; YELLOW alarm asserted 67 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT YEL_C=0x09 ; YELLOW alarm cleared FER=0x0A ; Framing error SFER=0x0B ; Severe framing error RED_A=0x0C ; RED alarm asserted RED_C=0x0D ; RED alarm cleared BOC_VALID=0x0E ; indicates a valid BOC BOC_IDLE=0x0F ; indicates a return to idle code RFDL_NEW_Q1=0x10 ; indicates a new packet ; has arrived on quadrant 1 RFDL_NEW_Q2=0x11 ; indicates a new packet ; has arrived on quadrant 2 RFDL_NEW_Q3=0x12 ; indicates a new packet ; has arrived on quadrant 3 RFDL_NEW_Q4=0x13 ; indicates a new packet ; has arrived on quadrant 4 IBC_LLA=0x14 ; indicates line loopback ; activated because in-band ; code detected IBC_LLD=0x15 ; indicates line loopback ; deactivated because in-band ; code detected XFDL_DONE_Q1=0x20 ; indicates an XFDL has been ; successfully xmitted from quadrant 1 XFDL_DONE_Q2=0x21 ; indicates an XFDL has been ; successfully xmitted from quadrant 2 XFDL_DONE_Q3=0x22 ; indicates an XFDL has been ; successfully xmitted from quadrant 3 XFDL_DONE_Q4=0x23 ; indicates an XFDL has been ; successfully xmitted from quadrant 4 LOCA_A=0x25 ;loss of clock activity asserted LOCA_C=0x26 ;loss of clock activity cleared LCD_A=0x27 ;loss of cell delineation asserted LCD_C=0x28 ;loss of cell delineation cleared XFFO_A=0x29 ;transmit FIFO overrun asserted RFFO_A=0x2A ;recieve FIFO overrun asserted COCA_A=0x2B ;change of cell allignment PMON_UPDATE=0x80 ; PMON counters updated RW_DONE=0xFF ; reg. R/W complete ; MailBox communication constants: HOST -> PIC CONSTANT READ_REG=0x01 ; MPH Reg Read Command CONSTANT WRITE_REG=0x02 ; MPH Reg Write Command CONSTANT XFDL_START=0x03 ; XFDL packet ready to send CONSTANT XBOC_START=0x04 ; begin sending a BOC CONSTANT XBOC_STOP=0x05 ; stop sending BOC CONSTANT TIMER_ON=0x06 ; enable timer ints CONSTANT TIMER_OFF=0x07 ; disable timer ints CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT LLBA=0x0C ; LLBD=0x0D ; PLBA=0x0E ; PLBD=0x0F ; DLBA=0x12 ; DLBD=0x13 ; XAIS_START=0x14 XAIS_STOP=0x15 READ_REG_QDSX=0x16 WRITE_REG_QDSX=0x17 line loopback activate line loopback deactivate payload loopback activate payload loopback deactivate diagnostic loopback activate diagnostic loopback deactivate ; start transmit AIS signal ; stop transmit AIS signal ; QDSX read command ; QDSX write command 68 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ; Bit Oriented Code (BOC) constants CONSTANT BOC_LLA=0x07 ; Line loopback activate CONSTANT BOC_LLD=0x1C ; Line loopback deactivate CONSTANT BOC_PLA=0x0A ; Payload loopback activate CONSTANT BOC_PLD=0x19 ; Payload loopback deactivate CONSTANT BOC_ULD=0x12 ; Universal loopback deactivate CONSTANT BOC_YELI=0x00 ; YELLOW alarm indication CONSTANT BOC_TERMINATE=0xFF ; terminate code ; used to tell MPH it should stop ; sending current BOC ; Performance Report Message Bitmap CBLOCK 0 PRM_G6, PRM_SL, PRM_G5, PRM_U2, PRM_U1, PRM_G4, PRM_LV, PRM_G3 ENDC CBLOCK 0 PRM_NL, PRM_NM, PRM_G2, PRM_R, PRM_G1, PRM_LB, PRM_SE, PRM_FE ENDC ; LAPD Address and Control bytes for PRMs CONSTANT CONSTANT CONSTANT LAPD_ADDR_BYTE1=0x38 ; address byte 1, ; SAPI=14, C/R=0 (CI), EA=0 LAPD_ADDR_BYTE2=0x01 ; TEI=0, EA=1 LAPD_CNTRL_BYTE=03 ;************************* ;* I/O MACRO DEFINITIONS * ;************************* ; write to RAM ; takes address and value WR_RAM MACRO ADDRESS, VALUE BANK0 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF PAGE0 CALL ENDM VALUE DATA_REG LOW ADDRESS ADDR_RAM_LO HIGH ADDRESS ADDR_RAM_HI WRITE_RAM ; setup data register ; setup address registers ; perform write ; end of macro ; write to quadrant-specific RAM area ; Only changes the lower 7 address bits ; the upper 2 address bits are assumed valid WR_RAM_L MACRO REGISTER, VALUE BANK0 MOVLW MOVWF MOVLW ANDWF MOVLW IORWF VALUE DATA_REG ; setup data register 0x80 ; setup address registers ADDR_RAM_LO, 1 (LOW REGISTER) & 0x7F ADDR_RAM_LO, 1 69 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PAGE0 CALL ENDM WRITE_RAM ; perform write ; end of macro ; write DATA_REG to ram ; takes RAM address WR_RAM_D MACRO ADDRESS BANK0 MOVLW MOVWF MOVLW MOVWF PAGE0 CALL ENDM LOW ADDRESS ADDR_RAM_LO HIGH ADDRESS ADDR_RAM_HI WRITE_RAM ; setup address registers ; perform write ; end of macro ; write DATA_REG to quadrant-specific RAM register ; Only changes the lower 7 address bits ; the upper 2 address bits are assumed valid WR_RAM_DL MACRO REGISTER BANK0 MOVLW ANDWF MOVLW IORWF PAGE0 CALL ENDM 0x80 ; setup address registers ADDR_RAM_LO, 1 (LOW REGISTER) & 0x7F ADDR_RAM_LO, 1 WRITE_RAM ; perform write ; end of macro ; write DATA_REG to quadrant-specific PMON RAM register ; PRE: WORK2 contains the quadrant to access WR_RAM_DP MACRO ADDRESS BANK0 MOVLW MOVWF MOVLW MOVWF MOVF PAGE0 CALL CALL ENDM ; write to MPH direct register WR_MPH MACRO REGISTER, VALUE BANK0 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF VALUE DATA_REG LOW REGISTER ADDR_MPH_LO HIGH REGISTER ADDR_MPH_HI ; setup data register ; setup address registers LOW ADDRESS ADDR_RAM_LO HIGH ADDRESS ADDR_RAM_HI WORK2, W SETUP_RADDR_PMON WRITE_RAM ; end of macro ; setup address registers 70 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PAGE0 CALL ENDM WRITE_MPH ; perform write ; end of macro ; write to MPH direct register ; takes register and value ; Only changes the lower 8 address bits ; the upper 3 address bits are assumed valid WR_MPH_L MACRO REGISTER, VALUE BANK0 MOVLW MOVWF MOVLW MOVWF PAGE0 CALL ENDM VALUE DATA_REG LOW REGISTER ADDR_MPH_LO WRITE_MPH ; setup data register ; perform write ; end of macro ; write DATA_REG to MPH direct register ; Only changes the lower 7 address bits ; the upper 2 address bits are assumed valid WR_MPH_DL MACRO REGISTER BANK0 MOVLW MOVWF PAGE0 CALL ENDM LOW REGISTER ADDR_MPH_LO WRITE_MPH ; perform write ; end of macro ; read from RAM ; takes address and returns contents in both W and DATA_REG RD_RAM MACRO ADDRESS BANK0 MOVLW MOVWF MOVLW MOVWF PAGE0 CALL ENDM LOW ADDRESS ADDR_RAM_LO HIGH ADDRESS ADDR_RAM_HI READ_RAM ; setup address registers ; perform read ; end of macro ; read from quadrant-specific RAM area ; Only changes the lower 7 address bits ; the upper 2 address bits are assumed valid RD_RAM_L MACRO REGISTER BANK0 MOVLW ANDWF MOVLW IORWF PAGE0 CALL 0x80 ; setup address registers ADDR_RAM_LO, 1 (LOW REGISTER) & 0x7F ADDR_RAM_LO, 1 READ_RAM ; perform read 71 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ENDM ; end of macro ; read from MPH ; takes register address and returns contents in both W and DATA_REG RD_MPH MACRO REGISTER BANK0 MOVLW MOVWF MOVLW MOVWF PAGE0 CALL ENDM LOW REGISTER ADDR_MPH_LO HIGH REGISTER ADDR_MPH_HI READ_MPH ; setup address registers ; perform read ; end of macro ; read from MPH ; takes register address and returns contents in both W and DATA_REG ; Only changes the lower 8 address bits ; the upper 3 address bits are assumed valid RD_MPH_L MACRO REGISTER BANK0 MOVLW MOVWF PAGE0 CALL ENDM LOW REGISTER ADDR_MPH_LO READ_MPH ; perform read ; end of macro ; write to QDSX direct register WR_QDSX MACRO REGISTER, VALUE BANK0 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF PAGE0 CALL ENDM VALUE DATA_REG LOW REGISTER ADDR_QDSX_LO HIGH REGISTER ADDR_QDSX_HI WRITE_QDSX ; setup data register ; setup address registers ; perform write ; end of macro ; write to QDSX direct register ; takes register and value ; Only changes the lower 6 address bits ; the upper 2 address bits are assumed valid WR_QDSX_L MACRO REGISTER, VALUE BANK0 MOVLW MOVWF MOVLW ANDWF MOVLW IORWF VALUE ; setup data register DATA_REG 0xC0 ADDR_QDSX_LO, 1 ; setup address registers (LOW REGISTER) & 0x3F ADDR_QDSX_LO, 1 72 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PAGE0 CALL ENDM WRITE_QDSX ; perform write ; end of macro ; write DATA_REG to QDSX direct register ; Only changes the lower 6 address bits ; the upper 2 address bits are assumed valid WR_QDSX_DL MACRO REGISTER BANK0 MOVLW ANDWF MOVLW IORWF PAGE0 CALL ENDM 0xC0 ; setup address registers ADDR_QDSX_LO, 1 (LOW REGISTER) & 0x3F ADDR_QDSX_LO, 1 WRITE_QDSX ; perform write ; end of macro ; read from QDSX ; takes register address and returns contents in both W and DATA_REG RD_QDSX MACRO REGISTER BANK0 MOVLW MOVWF MOVLW MOVWF PAGE0 CALL ENDM LOW REGISTER ADDR_QDSX_LO HIGH REGISTER ADDR_QDSX_HI READ_QDSX ; setup address registers ; perform read ; end of macro ; read from QDSX ; takes register address and returns contents in both W and DATA_REG ; Only changes the lower 6 address bits ; the upper two address bits are assumed valid RD_QDSX_L MACRO REGISTER BANK0 MOVLW ANDWF MOVLW IORWF PAGE0 CALL ENDM ;**************************** ;* Quadrant bit flag macros * ;**************************** BS_QUAD_BIT MOVLW ADDWF MACRO Q1_FLAGS QUAD, W QUAD, BIT 0xC0 ; setup address registers ADDR_QDSX_LO, 1 (LOW REGISTER) & 0x3F ADDR_QDSX_LO, 1 READ_QDSX ; perform read ; end of macro 73 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVWF BSF ENDM BC_QUAD_BIT MOVLW ADDWF MOVWF BCF ENDM BTSS_QUAD_BIT MOVLW ADDWF MOVWF BTFSS ENDM BTSC_QUAD_BIT MOVLW ADDWF MOVWF BTFSC ENDM FSR INDF, BIT ; end of macro MACRO Q1_FLAGS QUAD, W FSR INDF, BIT ; end of macro MACRO Q1_FLAGS QUAD, W FSR INDF, BIT ; end of macro MACRO Q1_FLAGS QUAD, W FSR INDF, BIT ; end of macro QUAD, BIT QUAD, BIT QUAD, BIT ;****************** ;* SET UP VECTORS * ;****************** ; RESET VECTOR ORG 0000 GOTO INIT ; INTERRUPT VECTOR ORG 0004 MOVWF SWAPF BCF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF PAGE0 GOTO TEMP_W STATUS, W STATUS, RP0 TEMP_STATUS PCLATH, W TEMP_PCLATH INT_STATUS, W INT_STATUS_SP DATA_REG, W TEMP_DATA_REG FSR, W TEMP_FSR INTHDLR ; save W and STATUS ; (order of commands is important) ; switch to bank 0 ; save PCLATH ; save INT_STATUS ; save DATA_REG ; save FSR ; initialize on reset ; very important, as this ISR may be ; called from anywhere ; jump to INTHDLR ;****************** 74 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ;* INITIALIZATION * ;****************** INIT CALL INIT_MICRO ; initialize the PIC microcontroller WR_QDSX GLOBAL_PMONQ, 0x80 ; reset QDSX WR_QDSX GLOBAL_PMONQ, 0x00 WR_MPH GLOBAL_PMON, 0x80 ; reset MPH WR_MPH GLOBAL_PMON, 0x00 CALL INIT_RAM ; initialize the RAM MOVLW 0x00 ; init all 4 quadrants of MPH CALL INIT_MPH MOVLW 0x01 CALL INIT_MPH MOVLW 0x02 CALL INIT_MPH MOVLW 0x03 CALL INIT_MPH MOVLW 0x00 ; init all 4 quadrants of QDSX CALL INIT_QDSX MOVLW 0x01 CALL INIT_QDSX MOVLW 0x02 CALL INIT_QDSX MOVLW 0x03 CALL INIT_QDSX CALL GOTO ;************* ;* MAIN LOOP * ;************* MAIN_LOOP BTFSC TIMEFLAG, 0 GOTO CALL_PMON INTSOFF BCF CLKSTAT, 0 RD_MPH_L CLKAMON BTFSC STATUS, Z BSF CLKSTAT, 0 BTFSC CLKSTAT, 0 CALL NOCLK BTFSS CLKSTAT, 0 CALL CLKOK INTSON CLRWDT GOTO MAIN_LOOP CALL_PMON PAGE1 CALL PAGE0 GOTO NOCLK BTFSC RETURN CLKSTAT, 1 ; if host has already been informed ; no need to tell it again ENABLE_INTS MAIN_LOOP ; enable PIC interrupts ; go to main loop ; has 1s interrupt occured? ; if so, call PMON subroutine ; clear bit (assume clock is ok) ; Check if clock activity monitor is bad ; yes -> set bit PMON MAIN_LOOP ; make cross-page call 75 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface BSF BCF WR_RAM RETURN CLKOK BTFSC RETURN BSF BCF WR_RAM regained. RETURN CLKSTAT, 1 CLKSTAT, 2 MAILOUT, LOCA_A ; inform host of loss of clock activity CLKSTAT, 2 ; if host has already been informed ; no need to tell it again CLKSTAT, 2 CLKSTAT, 1 MAILOUT, LOCA_C ; inform host that clock activity has been ;***************************** ;* READ SUBROUTINE FOR MPH * ;***************************** READ_MPH ; setup BANK0 MOVF MOVWF MOVLW ANDWF MOVF ANDLW IORWF address bus ADDR_MPH_LO, 0 PORTC 0xF8 PORTA, 1 ADDR_MPH_HI, 0 0x07 PORTA, 1 ; transfer MPH address to latch ; clear A8-A10 ; load W with A8-A10 ; mask off unused bits ; insert A8-A10 into PORTA ; perform read by toggling RWB and CSB MOVLW 0xF7 ANDWF PORTA, 1 ; activate CSB MOVLW 0xFE ANDWF PORTE, 1 ; activate RDB MOVF PORTD, 0 ; latch data MOVWF DATA_REG ; save data MOVLW 0x01 IORWF PORTE, 1 ; deactivate RDB MOVLW 0x08 IORWF PORTA, 1 ; deactivate CSB and complete read BANK0 MOVF RETURN DATA_REG, 0 ; place result into W reg ; end of subroutine ;***************************** ;* READ SUBROUTINE FOR QDSX * ;***************************** READ_QDSX ; setup BANK0 MOVF MOVWF MOVLW ANDWF MOVF ANDLW IORWF address bus ADDR_QDSX_LO, 0 PORTC 0xF8 PORTA, 1 ADDR_QDSX_HI, 0 0x07 PORTA, 1 ; transfer QDSX address to latch ; ; load W ; ; clear A8-A10 with A8-A10 mask off unused bits insert A8-A10 into PORTA 76 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ; perform read by toggling RWB and CSB3 MOVLW 0xDF ANDWF PORTA, 1 ; activate CSB3 MOVLW 0xFE ANDWF PORTE, 1 ; activate RDB MOVF PORTD, 0 ; latch data MOVWF DATA_REG ; save data MOVLW 0x01 IORWF PORTE, 1 ; deactivate RDB MOVLW 0x20 IORWF PORTA, 1 ; deactivate CSB and complete read BANK0 MOVF RETURN DATA_REG, 0 ; place result into W reg ; end of subroutine ;*************************** ;* READ SUBROUTINE FOR RAM * ;*************************** READ_RAM ; setup BANK0 MOVF MOVWF MOVLW ANDWF MOVF ANDLW IORWF address bus ADDR_RAM_LO, 0 PORTC 0xF8 PORTA, 1 ADDR_RAM_HI, 0 0x07 PORTA, 1 ; transfer RAM address to latch ; ; ; ; clear A8-A10 load W with A8-A10 mask off unused bits insert A8-A10 into PORTA ; perform read by toggling RWB and CSB MOVLW 0xEF ANDWF PORTA, 1 ; activate CSB MOVLW 0xFE ANDWF PORTE, 1 ; activate OEB MOVF PORTD, 0 ; latch data MOVWF DATA_REG ; save data MOVLW 0x01 IORWF PORTE, 1 ; deactiveate OEB MOVLW 0x10 IORWF PORTA, 1 ; deactivate CSB and complete read BANK0 MOVF RETURN DATA_REG, 0 ; place result into W reg. ; end of subroutine ;****************************** ;* WRITE SUBROUTINE FOR MPH * ;****************************** WRITE_MPH BANK1 MOVLW MOVWF 0x00 TRISD ; config data bus as output ; setup address bus BANK0 MOVF ADDR_MPH_LO, 0 MOVWF PORTC ; transfer MPH address to latch 77 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVLW ANDWF MOVF ANDLW IORWF 0xF8 PORTA, 1 ADDR_MPH_HI, 0 0x07 PORTA, 1 ; clear A8-A10 ; load W with A8-A10 ; mask off unused bits ; insert A8-A10 into PORTA ; transfer DATA_REG to latch ; setup data bus MOVF DATA_REG, 0 MOVWF PORTD ; perform write by toggling WRB and CSB MOVLW 0xF7 ANDWF PORTA, 1 ; activate CSB MOVLW 0xFD ANDWF PORTE, 1 ; activate WRB MOVLW 0x02 IORWF PORTE, 1 ; deactivate WRB MOVLW 0x08 IORWF PORTA, 1 ; deactivate CSB and complete write ; tristate data bus BANK1 MOVLW 0xFF ; MOVWF TRISD ; BANK0 RETURN ; select as default ; end of subroutine ;****************************** ;* WRITE SUBROUTINE FOR QDSX * ;****************************** WRITE_QDSX BANK1 MOVLW MOVWF ; setup BANK0 MOVF MOVWF MOVLW ANDWF MOVF ANDLW IORWF 0x00 TRISD address bus ADDR_QDSX_LO, 0 PORTC 0xDF PORTA, 1 ADDR_QDSX_HI, 0 0x07 PORTA, 1 ; config data bus as output ; transfer QDSX address to latch ; ; load W ; ; clear A8-A10 with A8-A10 mask off unused bits insert A8-A10 into PORTA ; setup data bus MOVF DATA_REG, 0 MOVWF PORTD ; transfer DATA_REG to latch ; perform write by toggling WRB and CSB MOVLW 0xDF ANDWF PORTA, 1 ; activate CSB MOVLW 0xFD ANDWF PORTE, 1 ; activate WRB MOVLW 0x02 IORWF PORTE, 1 ; deactivate WRB MOVLW 0x20 IORWF PORTA, 1 ; deactivate CSB and complete write 78 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ; tristate data bus BANK1 MOVLW 0xFF ; MOVWF TRISD ; BANK0 RETURN ; select as default ; end of subroutine ;**************************** ;* WRITE SUBROUTINE FOR RAM * ;**************************** WRITE_RAM ; activate data bus as output BANK1 MOVLW 0x00 MOVWF TRISD ; setup BANK0 MOVF MOVWF MOVLW ANDWF MOVF ANDLW IORWF address bus ADDR_RAM_LO, 0 PORTC 0xF8 PORTA, 1 ADDR_RAM_HI, 0 0x07 PORTA, 1 ; transfer RAM address to latch ; ; ; ; clear A8-A10 load W with A8-A10 mask off unused bits insert A8-A10 into PORTA ; setup data bus MOVF DATA_REG, 0 MOVWF PORTD ; transfer DATA_REG to latch ; perform write by toggling WRB and CSB MOVLW 0xEF ANDWF PORTA, 1 ; activate CSB MOVLW 0xFD ANDWF PORTE, 1 ; activate WRB MOVLW 0x02 IORWF PORTE, 1 ; deactivate WRB MOVLW 0x10 IORWF PORTA, 1 ; deactivate CSB and complete write ; tristate data bus BANK1 MOVLW 0xFF MOVWF TRISD BANK0 RETURN ;***************************** ;* INIT SUBROUTINE FOR MICRO * ;***************************** INIT_MICRO MOVLW MOVWF MOVLW MOVWF BANK0 0x18 PORTA 0x04 PORTB ; initialize ports ; make RAM CSB and MPH CSB pins inactive ; turn off LEDs, force unused pin high ; ; select as default ; end of subroutine 79 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CLRF PORTC ; clear A0-A7 CLRF PORTD ; clear D0-D7 MOVLW 0x03 MOVWF PORTE ; make RDB (OEBR) and WRB (RWBR) inactive MOVLW 0x7F MOVWF FSR CLEAR_USER_REGS CLRF INDF DECF FSR, F MOVF FSR, W XORLW 0x1F BTFSS STATUS, Z GOTO CLEAR_USER_REGS BSF CLKSTAT, 2 MOVLW 0xFF MOVWF PRM_COUNTER ; set the performance report counter ; to FF so that it will roll over to 00 ; on very first generation of PRMs MOVLW MOVWF MOVLW MOVWF BANK1 ; I/O port configuration: see the PIC databook for detailed information ; regarding the configuration of the ports MOVLW 0x07 ; configure PORTA as digital MOVWF ADCON1 MOVLW 0x05 ; set OPT and TMR0 prescalar TO 1:64 MOVWF OPTION_REG MOVLW 0x20 ; tristate LOCKIN input MOVWF TRISA MOVLW 0x13 ; LED outputs, INT/BUSY inputs, ; unused pin output MOVWF TRISB MOVLW 0x00 ; configure address bus as output MOVWF TRISC MOVLW 0xFF ; configure data bus as input MOVWF TRISD MOVLW 0x00 ; configure control bus as output MOVWF TRISE BANK0 ; should switch back to bank 0 by default MOVF PORTB,0 ; read PORTB to initialize latch value for RBIF ; this is necessary because of the method that the PIC ; uses for interrupt detection on some of the PORTB ; pins: an interrupt is generated when a difference ; between the current value and the last read value ; is detected. RETURN ;*************************** ;* INIT SUBROUTINE FOR RAM * ;*************************** INIT_RAM RD_RAM WR_RAM MAILIN VER_ADDR, VER ; read mailbox to clear any interrupts ; write version number to RAM ; end of subroutine ONE_SEC_L TIME_COUNT_L ONE_SEC_H TIME_COUNT_H ; initialize timer counter bytes 80 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface WR_RAM RETURN REV_ADDR, REV ; write revision number to RAM ; end of subroutine ;***************************** ;* INIT SUBROUTINE FOR MPH * ;***************************** ; Input: Quadrant to be initialized in W reg (0-3) ; Results: The associated quadrant is initialized ; this routine is provided as a generic routine which initializes ; the specified MPH quadrant. A call to SETUP_MADDR is made to setup the ; upper address lines and from this call forward, special read/write ; macros are used which do not alter the upper address lines. INIT_MPH CALL SETUP_MADDR ; setup address regs. for MPH accesses ; MPH initialization registers WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L RECV_CONFIG, 0x00 ; XMIT_CONFIG, 0x10 ; RINT_CONFIG, 0x04 ; XINT_CONFIG, 0x08 ; XCLK_OPTION, 0x00 ; CDRC_CONFIG, 0x00 ; FRMR_CONFIG, 0x10 ; XFDL_CONFIG, 0x03 ; RFDL_CONFIG, 0x01 ; IBCD_CONFIG, 0x04 ; T1TRAN_CONFIG, 0x30 ; ALMI_CONFIG, 0x10 ; RXCP_CONTROL, 0x2C ; RXCP_FRAME_CONTROL, 0x40 TXCP_CONTROL, 0xA4 ; ; ; ; ; ; ; ; ; 1.544 Mbit/s T1 ATM UNI 1.544 Mbit/s T1 ATM UNI single rail single rail, NRZ 24xT1 rate, TCLK sources TCLKO B8ZS, RZ ESF, 4kbit/s FDL Enable XFDL block/CRC append Enable RFDL block x bit code length ESF, 4kbit/s FDl, B8ZS ESF, 4kbit/s FDL HCSADD, BLOCK ; LCDE HCINS, HCSADD ; MPH interrupt enable registers WR_MPH_L CDRC_IE, 0x00 WR_MPH_L FRMR_IE, 0x01 WR_MPH_L RBOC_IE, 0x05 WR_MPH_L ALMI_IE, 0x07 WR_MPH_L IBCD_IE, 0x30 WR_MPH_L RFDL_IE, 0x02 WR_MPH_L RXCP_IE, 0x20 WR_MPH_L TXCP_IE, 0X40 ; other MPH registers WR_MPH_L DL_OPT, 0x0F WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L WR_MPH_L No LOS interrupt yet Enable INFR Enable IDLE, BOCE Enable YEL, RED, AIS Enable LBAE, LBDE3D INTC039 FIFOE FIFOE ; RDLINTE, RDLEOME, ; TDLINTE, TDLUDRE IBCD_AC, 0x08 ; IBCD activate code IBCD_DC, 0x24 ; IBCD deactivate code RXCP_IDLEMASK_H1, 0xFF ; Header mask RXCP_IDLEMASK_H2, 0xFF ; Header mask RXCP_IDLEMASK_H3, 0xFF ; Header mask RXCP_IDLEMASK_H4, 0xFF ; Header mask RXCP_USERMASK_H1, 0xFF ; User mask RXCP_USERMASK_H2, 0xFF ; User mask RXCP_USERMASK_H3, 0xFF ; User mask RXCP_USERMASK_H4, 0xFF ; User mask 81 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface WR_MPH_L idle cells WR_MPH_L cells RETURN TXCP_IDLEPAT_H5, 0x55 TXCP_IDLEPAY, 0x6A ; Header Check sequence for ; Payload for unassigned ; end of subroutine ;***************************** ;* INIT SUBROUTINE FOR QDSX * ;***************************** ; Input: Quadrant to be initialized in W reg (0-3) ; Results: The associated quadrant is initialized ; this routine is provided as a generic routine which initializes ; the specified QDSX quadrant. A call to SETUP_QADDR is made to setup the ; upper address lines and from this call forward, special read/write ; macros are used which do not alter the upper address lines. INIT_QDSX CALL SETUP_QADDR ; setup address regs. for QDSX accesses ; QDSX initialization registers WR_QDSX_L WR_QDSX_L WR_QDSX_L WR_QDSX_L WR_QDSX_L RETURN CDRC_CONFIGQ, 0x64 IBCD_CONFIGQ, 0x04 XPLS_CONFIGQ, 0x40 IBCD_ACQ, 0x08 IBCD_DCQ, 0x24 ; end of subroutine ;************************************** ;* SUBROUTINE FOR ENABLING INTERRUPTS * ;************************************** ENABLE_INTS MOVLW MOVWF RETURN 0xB8 INTCON ; Enable TMR0, INT, RBI ; end of subroutine ;****************************** ;* INTERRUPT HANDLING ROUTINE * ;****************************** INTHDLR DET_SOURCE BTFSC CALL BTFSC CALL BTFSS INTCON, INTF ; check for external (MPH or QDSX) Interrupt EXT_INT INTCON, RBIF ; check for RAM Interrupt CALL_RAM_INT PORTB, 4 ; check for missed RAM Interrupt ; it's neccesary to poll the RAM interrupt ; pin because of a flaw in the PIC micro's ; interrupt handling. Basically, it ; occassionaly misses interrupts asserted ; by the interrupt-on-change pins (bits 4-7) ; of PORTA. CALL_RAM_INT INTCON, T0IE ; check that the TIMER int is not disabled SKIP ; INTCON, T0IF ; check for TIMER Interrupt CALL BTFSS GOTO BTFSC 82 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CALL SKIP ; ; ; ; ; CALL_TIMER_INT ; Check for pending external interrupt this check is here to minimize interrupt latency when there are multiple external interrupts pending, and to catch an external interrupt that may have occurred while another was being serviced PORTB, 0 ; skip if interrupt is not pending BTFSS TINT_LOOP CALL BTFSS GOTO CLEAN_UP BANK0 MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF SWAPF MOVWF SWAPF SWAPF RETFIE EXT_INT RD_MPH ANDLW BTFSC GOTO RD_QDSX ANDLW BTFSC GOTO RETURN EXT_INT ; if there is still a pending external ; int, then service it now PORTB, 0 ; loop until no MPH interrupts TINT_LOOP TEMP_PCLATH, W ; restore PCLATH PCLATH INT_STATUS_SP, W ; restore state of INT_STATUS INT_STATUS TEMP_DATA_REG, W ; restore DATA_REG DATA_REG TEMP_FSR, W ; restore FSR FSR TEMP_STATUS, W ; restore W and STATUS registers STATUS TEMP_W, F TEMP_W, W ; return from interrupt INT_ID 0xF0 STATUS, Z MPH_INT INT_IDQ 0xF0 STATUS, Z QDSX_INT ; check intid for MPH ; mask off unused bits ; test if MPH caused interupt ; check intid for QDSX ; test if QDSX caused interupt ; the following routines are required for cross-page calling ; they are associated with the code directly above CALL_RAM_INT PAGE1 CALL PAGE0 MOVF BCF RETURN RAM_INT PORTB, 1 ; Read PORTB onto itself to clear ; interrupt on change logic INTCON, RBIF ; Clear PORTB interrupt flag ; end of subroutine CALL_TIMER_INT PAGE1 CALL TIMER_INT PAGE0 RETURN ; end of subroutine 83 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ;*********************************** ;* SUBROUTINE FOR MPH INTERRUPTS * ;*********************************** MPH_INT BCF INTCON, INTF ; clear interrupt flag ; determine interrupting quadrant and set up MPH address regs. RD_MPH INT_ID ; which quadrant interrupted? MOVWF WORK ; save in reg for testing MOVLW 0x80 ; Initialize W to test for invalid quadrant ; after case statement BTFSC WORK, 4 ; quadrant 1? MOVLW 00 ; quadrant 1 BTFSC WORK, 5 ; quadrant 2? MOVLW 01 ; quadrant 2 BTFSC WORK, 6 ; quadrant 3? MOVLW 02 ; quadrant 3 BTFSC WORK, 7 ; quadrant 4? MOVLW 03 ; quadrant 4 MOVWF QUADRANT ; save quadrant BTFSC QUADRANT, 7 ; if MSB set, then no valid quadrant RETURN ; end of subroutine MOVWF DATA_REG ; prepare for write to RAM MOVF CALL QUADRANT, W SETUP_MADDR ; ; ; setup the upper address lines to address interrupting quadrant of the MPH ; read in MPH int source registers for interrupting quadrant RD_MPH_L INT1_1 ; read register MOVWF INT1 ; save value RD_MPH_L INT2_1 ; read register MOVWF INT2 ; save value ; test for interrupt source BTFSC INT1, 0 ; ALMI block? GOTO ALMI BTFSC INT2, 0 ; CDRC block? GOTO CDRC BTFSC INT1, 5 ; FRMR block? GOTO FRMR BTFSC INT1, 1 ; RBOC block? GOTO RBOC BTFSC INT1, 6 ; IBCD block? GOTO IBCD BTFSC INT1, 2 ; RFDL block? GOTO RFDL BTFSC INT2, 1 ; XFDL block? GOTO XFDL BTFSC INT2, 2 ; TXCP block? GOTO TXCP BTFSC INT2, 3 ; RXCP block? GOTO RXCP RETURN ; end of subroutine ; Alarm Integrator block 84 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ALMI RD_MPH_L ALMI_IS MOVWF INT_STATUS BTFSC INT_STATUS, 3 CALL AIS BTFSC INT_STATUS, 5 CALL YEL BTFSC INT_STATUS, 4 CALL RED RETURN ; test for AISI ; test for YELI ; test for REDI ; return from subroutine ; Clock and Data Recovery block CDRC RD_MPH_L CDRC_IS MOVWF INT_STATUS BTFSC INT_STATUS, 6 ; test for LOSI CALL LOS BTFSC INT_STATUS, 3 ; test for Z16DI CALL Z16DI RETURN ; return from subroutine ; Framer block FRMR RD_MPH_L FRMR_IS MOVWF INT_STATUS BTFSC INT_STATUS, 2 CALL INFR BTFSC INT_STATUS, 6 CALL FERI BTFSC INT_STATUS, 4 CALL SFEI RETURN ; test for INFRI ; test for FERI ; test for SFEI ; return from subroutine ; Bit Oriented Code Detector block RBOC RD_MPH_L RBOC_IS MOVWF INT_STATUS ANDLW 0x3F ; mask out 6-bit BOC MOVWF WORK ; save BOC in work BTFSC INT_STATUS, 6 ; test for BOCI CALL BOCI BTFSC INT_STATUS, 7 ; test for IDLEI CALL IDLEI RETURN ; return from subroutine BOCI MOVLW XORWF BTFSC BOC_YELI WORK, W STATUS, Z ; test for YELLOW alarm ; if it is, exit now (will be dealt with by alarm integrator block) ; return from subroutine ; indicate which quadrant ; RETURN MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD MOVF WORK, W ; re-load BOC MOVWF DATA_REG ; place in RAM for host WR_RAM_D RAM_RBOC WR_RAM MAILOUT, BOC_VALID ; indicate a valid BOC detected BC_QUAD_BIT QUADRANT, LL_REQ ; clear loopback request bit MOVF WORK, W ; re-load BOC 85 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO RETURN LLA BOC_LLA STATUS, LLA WORK, W BOC_LLD STATUS, LLD WORK, W BOC_PLA STATUS, PLA WORK, W BOC_PLD STATUS, PLD WORK, W BOC_ULD STATUS, ULD ; test for line loopback activate Z ; re-load BOC ; test for line loopback deactivate Z ; re-load BOC ; test for payload loopback act. Z ; re-load BOC ; test for payload looback deact. Z ; re-load BOC ; test for universal loopback dis. Z ; if none of these, then done QUADRANT, LL_REQ ; set loopback request ; return from subroutine BS_QUAD_BIT RETURN LLD RD_MPH_L MSTR_DIAG ; read in diagnostic register BCF DATA_REG, 4 ; clear line loopback bit WR_MPH_DL MSTR_DIAG ; update register RETURN ; return from subroutine PLA RD_MPH_L MSTR_DIAG BSF DATA_REG, 5 ; activate payload loopback WR_MPH_DL MSTR_DIAG ; update register RETURN ; return from subroutine PLD RD_MPH_L MSTR_DIAG BCF DATA_REG, 5 ; deactivate payload loopback WR_MPH_DL MSTR_DIAG ; update register RETURN ; return from subroutine ULD RD_MPH_L MSTR_DIAG ; universal loopback deactivate BCF DATA_REG, 4 ; clear all loopbacks BCF DATA_REG, 5 WR_MPH_DL MSTR_DIAG RETURN ; return from subroutine IDLEI MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, BOC_IDLE ; indicate idle BOC to host BTSS_QUAD_BIT QUADRANT, LL_REQ ; test for ll request RETURN RD_MPH_L MSTR_DIAG BSF DATA_REG, 4 ; activate line loopback WR_MPH_DL MSTR_DIAG RETURN ; return from subroutine ; Inband Loopback Code Detector block IBCD RD_MPH_L IBCD_IS 86 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVWF INT_STATUS BTFSC INT_STATUS, 1 ; test for in-band code act. GOTO IBCD_ACTIVATE BTFSC INT_STATUS, 0 ; test for in-band code deact. GOTO IBCD_DEACTIVATE RETURN ; return from subroutine IBCD_ACTIVATE RD_MPH_L MSTR_DIAG BSF DATA_REG, 4 ; activate line loopback WR_MPH_DL MSTR_DIAG MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, IBC_LLA ; indicate IBC ll activate to host RETURN ; return from subroutine IBCD_DEACTIVATE RD_MPH_L MSTR_DIAG BCF DATA_REG, 4 ; deactivate line loopback WR_MPH_DL MSTR_DIAG MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, IBC_LLD ; indicate IBC ll deactivate to host RETURN ; return from subroutine ; HDLC Transmitter block ; *** N.B. the timing with which the last byte of a packet and the ; end of message (EOM) bit is set is very important. The last byte is ; written, and then not until the XFDL block interrupts for another byte ; is the EOM bit set. This is because if the EOM bit is set right after ; writing the last byte of the packet, it is possible that the EOM bit ; will be erroneously cleared by the state machine in the XFDL block. ; Doing things in the sequence as in the code below prevents any ; possibility of this occuring. XFDL BTSC_QUAD_BIT QUADRANT, XFDL_USR_OR_PRM ; are we sending a user packet GOTO PRM_XMIT ; or a performance report message? RD_MPH_L XFDL_IS ; read MPH int. status register BTFSC DATA_REG, 0 ; re-send packet if under-run GOTO XFDL_RESTART BTFSS DATA_REG, 1 ; confirm an XFDL interrupt RETURN ; return from subroutine CALL SETUP_RADDR_XFDL ; setup RAM address to XFDL range MOVF QUADRANT, W ; access local packet length value ADDLW Q1_XFDL_PLEN MOVWF FSR MOVF INDF, W MOVWF WORK1 MOVF QUADRANT, W ; access data pointer value ADDLW Q1_XFDL_RPTR MOVWF FSR MOVF INDF, W XORWF WORK1, W ; have we reached the end of pkt.? BTFSC STATUS, Z ; if so go to end of message routine GOTO XFDL_EOM MOVLW 0x80 ; zero lower 7 RAM address bits ANDLW ADDR_RAM_LO MOVF INDF, W ; get RAM pointer for this quadrant IORWF ADDR_RAM_LO, 1 ; place it in RAM address reg. 87 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CALL READ_RAM ; read the RAM byte WR_MPH_DL XFDL_DATA ; write it to the MPH INCF INDF, 1 ; increment the RAM pointer MOVF INDF, W RETURN ; end of subroutine XFDL_EOM BTSC_QUAD_BIT QUADRANT, XFDL_PENDING GOTO SEND_PENDING_PRM RD_MPH_L XFDL_CONFIG ; we are finished, so BSF DATA_REG, 4 ; set EOM bit in XFDL BCF DATA_REG, 3 ; turn off XFDL interrupts WR_MPH_DL XFDL_CONFIG BC_QUAD_BIT QUADRANT, XFDL_BUSY ; clear XFDL busy bit MOVLW XFDL_DONE_Q1 ; signal done ADDWF QUADRANT, W MOVWF DATA_REG WR_RAM_D MAILOUT RETURN ; done this packet SEND_PENDING_PRM RD_MPH_L XFDL_CONFIG ; we are finished send user packet, so BSF DATA_REG, 4 ; set EOM bit in XFDL WR_MPH_DL XFDL_CONFIG BC_QUAD_BIT QUADRANT, XFDL_PENDING ; clear XFDL pending bit BS_QUAD_BIT QUADRANT, XFDL_USR_OR_PRM ; set user/PRM bit to PRM MOVLW XFDL_DONE_Q1 ; signal done ADDWF QUADRANT, W MOVWF DATA_REG WR_RAM_D MAILOUT RETURN ; done this packet XFDL_RESTART BCF DATA_REG, 0 WR_MPH_DL XFDL_IS MOVF QUADRANT, W ADDLW Q1_XFDL_TO MOVWF FSR MOVF INDF, W BTFSC STATUS, Z GOTO XFDL_GIVEUP DECF INDF, F GOTO XFDL_PKT_RESTART ; clear under-run bit ; setup for access to timeout counter ; add base offset ; place result in indirect mem. ptr. ; check we haven't timed out ; on packet restarts ; giveup if so ; decrement counter ; call routine to setup for ; the transmission of an XFDL packet XFDL_GIVEUP BTSC_QUAD_BIT QUADRANT, XFDL_PENDING GOTO SEND_PENDING_PRM2 RD_MPH_L XFDL_CONFIG BCF DATA_REG, 3 ; turn off XFDL interrupts WR_MPH_DL XFDL_CONFIG BC_QUAD_BIT QUADRANT, XFDL_BUSY ; clear FDL busy bit RETURN ; end of subroutine SEND_PENDING_PRM2 BC_QUAD_BIT QUADRANT, XFDL_PENDING ; clear XFDL pending bit BS_QUAD_BIT QUADRANT, XFDL_USR_OR_PRM ; set user/PRM bit to PRM RETURN ; done this packet XFDL_PKT_START RD_RAM XFDL_QUAD ; which quadrant's XFDL block? ANDLW 0x03 ; confine quadrant range MOVWF QUADRANT ; save in QUADRANT ; check if a user HDLC packet is already in progress, return if so 88 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface BTSS_QUAD_BIT QUADRANT, XFDL_BUSY GOTO XFDL_PKT_START_CONT BTSS_QUAD_BIT QUADRANT, XFDL_USR_OR_PRM RETURN XFDL_PKT_START_CONT MOVF QUADRANT, W ; reset timeout counter ADDLW Q1_XFDL_TO MOVWF FSR MOVLW XFDL_MAX_RESTARTS MOVWF INDF MOVF QUADRANT, W ; clear the RAM pkt. pointer to 0 ADDLW Q1_XFDL_RPTR MOVWF FSR CLRF INDF MOVF QUADRANT, W ; make local copy of packet length ADDLW Q1_XFDL_PLEN MOVWF FSR CALL SETUP_RADDR_XFDL RD_RAM_L RAM_PCT_LEN ; read in packet length MOVF DATA_REG, W ; store in local length register MOVWF INDF SUBLW MAX_FDL_PLEN ; make sure packet length < maxlength BTFSS STATUS, C RETURN ; abort if not so BTSC_QUAD_BIT QUADRANT, XFDL_BUSY GOTO XFDL_MAKE_PEND BC_QUAD_BIT QUADRANT, XFDL_USR_OR_PRM ; set user/PRM bit to user BS_QUAD_BIT QUADRANT, XFDL_BUSY ; set FDL busy bit MOVF QUADRANT, W CALL SETUP_MADDR RD_MPH_L XFDL_CONFIG BSF DATA_REG, 3 ; enable XFDL interrupts WR_MPH_DL XFDL_CONFIG RETURN ; return from subroutine XFDL_MAKE_PEND BS_QUAD_BIT QUADRANT, XFDL_PENDING ; set XFDL pending bit RETURN XFDL_PKT_RESTART MOVF QUADRANT, W ; clear the RAM pkt. pointer to 0 ADDLW Q1_XFDL_RPTR MOVWF FSR CLRF INDF MOVF QUADRANT, W ; make local copy of packet length ADDLW Q1_XFDL_PLEN MOVWF FSR CALL SETUP_RADDR_XFDL RD_RAM_L RAM_PCT_LEN ; read in packet length MOVF DATA_REG, W ; store in local length register MOVWF INDF RETURN PRM_XMIT RD_MPH_L XFDL_IS BTFSC DATA_REG, 0 GOTO PRM_ABORT BTFSS DATA_REG, 1 RETURN MOVLW Q1_PRM_PTR MOVWF FSR ; read MPH int. status register ; abort PRM if under-run ; confirm an XFDL interrupt ; return from subroutine ; check which byte we need to send next 89 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVF ADDWF MOVF BTFSC GOTO XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO QUADRANT, W FSR, F INDF, W STATUS, Z PRM_BYTE1 0x01 STATUS, Z PRM_BYTE2 INDF, W 0x02 STATUS, Z PRM_BYTE3 INDF, W 0x0B STATUS, Z END_PRM ; address byte #1 ; address byte #2 ; control byte ; have we finished? MOVLW 0x03 SUBWF INDF, W INCF INDF, F ADDLW 0x06 MOVWF WORK1 MOVF PRM_COUNTER, W SUBWF WORK1, F SUBWF WORK1, W ANDLW 0x07 ADDLW Q1_PRM_1B1 MOVWF FSR MOVF QUADRANT, W MOVWF WORK BCF STATUS, C RLF WORK, F RLF WORK, F RLF WORK, W ADDWF FSR, F MOVF INDF, W MOVWF DATA_REG COPY_PRM_BYTE WR_MPH_DL XFDL_DATA RETURN PRM_BYTE1 INCF MOVLW MOVWF GOTO PRM_BYTE2 INCF MOVLW MOVWF GOTO PRM_BYTE3 INCF MOVLW MOVWF GOTO INDF, F LAPD_ADDR_BYTE1 DATA_REG COPY_PRM_BYTE INDF, F LAPD_ADDR_BYTE2 DATA_REG COPY_PRM_BYTE INDF, F LAPD_CNTRL_BYTE DATA_REG COPY_PRM_BYTE ; point FSR to next PRM byte ; rolling over if neccesary ; increment PRM pointer here ; address byte #1 ; address byte #2 ; control byte PRM_ABORT BCF DATA_REG, 0 WR_MPH_DL XFDL_IS ; clear under-run bit 90 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface ; fall through to END_PRM, setting EOM bit doesn't matter END_PRM BTSC_QUAD_BIT QUADRANT, XFDL_PENDING GOTO SEND_PENDING_USR RD_MPH_L XFDL_CONFIG ; we are finished, so BSF DATA_REG, 4 ; set EOM bit in XFDL BCF DATA_REG, 3 ; turn off XFDL interrupts WR_MPH_DL XFDL_CONFIG BC_QUAD_BIT QUADRANT, XFDL_BUSY ; clear FDL busy bit RETURN SEND_PENDING_USR RD_MPH_L XFDL_CONFIG ; we are finished, so BSF DATA_REG, 4 ; set EOM bit in XFDL WR_MPH_DL XFDL_CONFIG BC_QUAD_BIT QUADRANT, XFDL_PENDING ; clear FDL pending bit BC_QUAD_BIT QUADRANT, XFDL_USR_OR_PRM ; set user/PRM bit to USR RETURN ; HDLC Receiver block RFDL MOVF QUADRANT, 0 ; update RAM indicating to which MOVWF DATA_REG ; quadrant current RFDL operation WR_RAM_D RFDL_QUAD ; pertains CALL SETUP_RADDR_RFDL; setup address MOVF QUADRANT, 0 ; setup FSR register to access ADDLW Q1_RFDL_STAT ; RFDL status reg. per quad. MOVWF FSR RFDL_REPEAT BCF FSR, 2 ; explicitly point to status regs RD_MPH_L RFDL_DATA ; read data byte MOVWF TEMP_RFDL_DATA ; save the read data RD_MPH_L RFDL_STATUS ; read status MOVWF TEMP_RFDL_STATUS BTFSC TEMP_RFDL_STATUS, 6 ; overrun? GOTO OVR BTFSS TEMP_RFDL_STATUS, 5 ; FLG set to 1? GOTO FLG_0 ; must be 0 FLG_1 MOVF FSR, W ; save FSR MOVWF WORK1 BTSC_QUAD_BIT QUADRANT, RFDL_ACTIVE GOTO NEW_BYTE BS_QUAD_BIT QUADRANT, RFDL_ACTIVE ; yes, then mark active MOVF WORK1, W ; restore FSR MOVWF FSR BSF FSR, 2 ; set to access counters CLRF INDF ; clear counter RETURN ; return from subroutine NEW_BYTE MOVF WORK1, W ; restore FSR MOVWF FSR MOVF TEMP_RFDL_DATA, 0 ; re-load data MOVWF DATA_REG ; get ready for write BSF FSR, 2 ; set to access counter MOVLW 0x80 ANDWF ADDR_RAM_LO, 1 ; mask off lower address lines MOVF INDF, 0 ; load pointer IORWF ADDR_RAM_LO, 1 ; setup address CALL WRITE_RAM INCF INDF, 1 ; increment pointer 91 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface BTFSC GOTO BTFSC RETURN GOTO FLG_0 TEMP_RFDL_STATUS, 4 ; end of message? RFDL_EOM TEMP_RFDL_STATUS, 7 ; is there another byte ; waiting? ; return from subroutine RFDL_REPEAT MOVF FSR, W ; save FSR MOVWF WORK1 BTSC_QUAD_BIT QUADRANT, RFDL_ACTIVE GOTO RFDL_ABORT RETURN ; return from subroutine RFDL_ABORT BC_QUAD_BIT QUADRANT, RFDL_ACTIVE ; yes, then set inactive MOVF WORK1, W ; restore FSR MOVWF FSR BCF FSR, 2 ; access status register CLRF INDF BSF FSR, 2 ; access counter register CLRF INDF RETURN ; return from subroutine OVR BCF FSR, 2 ; choose status registers BSF INDF, 6 ; set OVERRUN bit RETURN ; return from subroutine RFDL_EOM ; update channel status in local (PIC) registers BCF FSR, 2 ; choose status registers BTFSC TEMP_RFDL_STATUS, 3 BSF INDF, 3 ; set CRC bit BTFSC TEMP_RFDL_STATUS, 0 BSF INDF, 0 ; NVB0 BTFSC TEMP_RFDL_STATUS, 1 BSF INDF, 1 ; NVB1 BTFSC TEMP_RFDL_STATUS, 2 BSF INDF, 2 ; NVB2 ; transfer registers to ram MOVF INDF, 0 MOVWF DATA_REG WR_RAM_DL RAM_CHAN_STAT ; write channel status CLRF INDF BSF FSR, 2 ; choose counter register MOVF INDF, 0 MOVWF DATA_REG WR_RAM_DL RAM_PCT_LEN CLRF INDF MOVF DATA_REG, W ; check if packet length >= 3 SUBLW 0x02 BTFSC STATUS, C RETURN ; return from subroutine MOVLW RFDL_NEW_Q1 ; signal end of new packet ADDWF QUADRANT, W MOVWF DATA_REG WR_RAM_D MAILOUT RETURN ; return from subroutine ; TXCP Block TXCP RD_MPH_L TXCP_IS MOVWF INT_STATUS 92 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface BTFSC GOTO BTFSC GOTO RETURN COCA INT_STATUS, 2 COCA INT_STATUS, 1 FOVR ; Change of cell alignment? ; Transmit FIFO overrun? MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, COCA_A RETURN FOVR MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, XFFO_A RETURN ; indicate to host there has been a change of ; cell alignment ; indicate which quadrant ; send mailbox code ;indicate to host there has been a transmit ; FIFO overrun ; indicate which quadrant ; send mailbox code ; RXCP Block RXCP RD_MPH_L RXCP_IS MOVWF INT_STATUS BTFSS INT_STATUS, 1 ; recieve FIFO overrun? GOTO LCD ; if not may be loss of cell delineation MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD ; indicate quadrant WR_RAM MAILOUT, RFFO_A ; send mailbox code RETURN LCD RD_MPH_L RXCPFC_IS MOVWF INT_STATUS ; loss of cell delineation? BTFSS INT_STATUS, 5 RETURN BTFSS INT_STATUS, 4 ; send appropriate status GOTO LCD_CLEAR MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD ; indicate quadrant WR_RAM MAILOUT, LCD_A ; send mailbox code RETURN LCD_CLEAR MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD ; indicate quadrant WR_RAM MAILOUT, LCD_C ; send mailbox code RETURN AIS BTFSC INT_STATUS, 0 GOTO AIS_SET MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, AIS_C RETURN AIS_SET MOVF QUADRANT, W MOVWF DATA_REG ; is AIS set? ; indicate which quadrant ; send clear message ; return from subroutine ; indicate which quadrant 93 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface WR_RAM_D INT_QUAD WR_RAM MAILOUT, AIS_A RD_MPH_L MSTR_DIAG BCF DATA_REG, 4 BCF DATA_REG, 5 WR_MPH_DL MSTR_DIAG RETURN LOS ; ; ; ; ; ; send asserted message clear all loopbacks clear line loopback clear payload loopback update MPH return from subroutine BTFSC INT_STATUS, 0 ; is LOS set? GOTO LOS_SET MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, LOS_A ; send clear message GOTO LOS_END LOS_SET MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, LOS_C ; send asserted message LOS_END RETURN ; return from subroutine ; In-Frame indication is commented out INFR ; BTFSC INT_STATUS, 0 ; is INFR set? ; GOTO INFR_SET ; MOVF QUADRANT, W ; indicate which quadrant ; MOVWF DATA_REG ; WR_RAM_D INT_QUAD ; WR_RAM MAILOUT, INFR_C ; send clear message ; GOTO INFR_END INFR_SET ; MOVF QUADRANT, W ; indicate which quadrant ; MOVWF DATA_REG ; WR_RAM_D INT_QUAD ; WR_RAM MAILOUT, INFR_A ; send asserted message INFR_END RETURN ; return from subroutine YEL BTFSC INT_STATUS, 2 ; is YEL set? GOTO YEL_SET MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, YEL_C ; send clear message GOTO YEL_END YEL_SET MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, YEL_A ; send asserted message YEL_END RETURN ; return from subroutine RED BTFSC INT_STATUS, 1 ; is RED set? GOTO RED_SET MOVF QUADRANT, W ; indicate which quadrant 94 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, RED_C ; send clear message GOTO RED_END RED_SET MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD WR_RAM MAILOUT, RED_A ; send asserted message RED_END RETURN ; return from subroutine ; Pulse Density Violation indication is commented out Z16DI ; MOVF QUADRANT, W ; indicate which quadrant ; MOVWF DATA_REG ; WR_RAM_D INT_QUAD ; WR_RAM MAILOUT, PDV ; signal a pulse density voilation RETURN ; return from subroutine ; Framing Error indication is commented out FERI ; MOVF QUADRANT, W ; indicate which quadrant ; MOVWF DATA_REG ; WR_RAM_D INT_QUAD ; WR_RAM MAILOUT, FER ; signal a framing error RETURN ; return from subroutine ; Severe Framing Error indication is commented out SFEI BSF SEF, QUADRANT ; set bit for PMON SEF bit ; MOVF QUADRANT, W ; indicate which quadrant ; MOVWF DATA_REG ; WR_RAM_D INT_QUAD ; WR_RAM MAILOUT, SFER ; signal a severe framing error RETURN ; return from subroutine ;*********************************** ;* SUBROUTINE FOR QDSX INTERRUPTS * ;*********************************** QDSX_INT BCF INTCON, INTF ; clear interrupt flag ; determine interrupting quadrant and set up QDSX address regs. RD_QDSX INT_IDQ ; which quadrant interrupted? MOVWF WORK ; save in reg for testing MOVLW 0x80 ; Initialize W to test for invalid quadrant ; after case statement BTFSC WORK, 4 ; quadrant 1? MOVLW 00 ; quadrant 1 BTFSC WORK, 5 ; quadrant 2? MOVLW 01 ; quadrant 2 BTFSC WORK, 6 ; quadrant 3? MOVLW 02 ; quadrant 3 BTFSC WORK, 7 ; quadrant 4? MOVLW 03 ; quadrant 4 MOVWF QUADRANT ; save quadrant BTFSC QUADRANT, 7 ; if MSB set, then no valid quadrant RETURN ; end of subroutine 95 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVWF MOVF CALL DATA_REG QUADRANT, W SETUP_QADDR ; ; ; prepare for write to RAM ; setup the upper address lines to address interrupting quadrant of the QDSX ; read in QDSX int source register for interrupting quadrant RD_QDSX_L INTQ ; read register MOVWF INT1 ; save value ; test for interrupt source BTFSC INT1, 0 GOTO DJAT_Q ; DJAT ? BTFSC INT1, 1 GOTO CDRC_Q ; CDRC ? BTFSC INT1, 3 GOTO LCV_PMON_Q ; LCV_PMON ? BTFSC INT1, 4 GOTO PRSM_Q ; PRSM ? BTFSC INT1, 5 GOTO IBCD_Q ; IBCD ? BTFSC INT1, 6 GOTO XPLS_Q ; XPLS ? BTFSC INT1, 7 GOTO RLSC_Q ; RLSC ? RETURN ; end of subroutine DJAT_Q RD_QDSX_L DJAT_ISQ RETURN ;do nothing CDRC_Q RD_QDSX_L RETURN ;do LCV_PMON_Q RD_QDSX_L RETURN ;do PRSM_Q RD_QDSX_L RETURN ;do IBCD_Q RD_QDSX_L RETURN ;do XPLS_Q RD_QDSX_L RETURN ;do RLSC_Q RD_QDSX_L RETURN ;do ; ; ; ; CDRC_ISQ nothing LCV_PMON_ISQ nothing PRSM_ISQ nothing IBCD_ISQ nothing XPLS_ISQ nothing RLSC_ISQ nothing ; read the interupt to clear it ; read the interupt to clear it ; read the interupt to clear it ; read the interupt to clear it ; read the interupt to clear it ; read the interupt to clear it ; read the interupt to clear it This routine sets the upper 2 bits of the MPH address register according to the quadrant to be accessed Input: W register contains the quadrant Results: ADDR_MPH_HI and ADDR_MPH_LO are set up WORK5 ADDR_MPH_LO SETUP_MADDR MOVWF CLRF ; clear address registers 96 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CLRF IORWF RETURN ADDR_MPH_HI ADDR_MPH_HI, F ; return from subroutine ; This routine sets the upper 2 bits of the QDSX address register ; according to the quadrant to be accessed ; Input: W register contains the quadrant ; Results: ADDR_QDSX_HI and ADDR_QDSX_LO are set up ; **NB** WORK5 is affected by this routine !!! SETUP_QADDR MOVWF WORK5 CLRF ADDR_QDSX_LO ; clear address registers CLRF ADDR_QDSX_HI BSF ADDR_QDSX_LO, 6 ; copy bit 0 of quadrant (W=WORK5) to BSF ADDR_QDSX_LO, 7 ; bit 6 of LSB of QDSX address reg BTFSS WORK5, 0 ; and bit 1 of quadrant to BCF ADDR_QDSX_LO, 6 ; bit 7 of LSB of QDSX address reg BTFSS WORK5, 1 BCF ADDR_QDSX_LO, 7 RETURN ; return from subroutine ; This routines sets up bits 4 and 5 of the RAM address register ; according to quadrant specified in the W register to access ; PMON RAM locations ; **NB** WORK5 is affected by this routine !!! SETUP_RADDR_PMON MOVWF WORK5 BSF ADDR_RAM_LO, 4 ; copy bit 0 of quadrant (W) to BSF ADDR_RAM_LO, 5 ; bit 4 of LSB of RAM address reg BTFSS WORK5, 0 ; and bit 1 of quadrant (W) to BCF ADDR_RAM_LO, 4 ; bit 5 of LSB of RAM address reg BTFSS WORK5, 1 BCF ADDR_RAM_LO, 5 RETURN ; end of SETUP_RADDR_PMON ; This routine sets up the RAM address register to access the RFDL ; memory of a particular quadrant ; Input: QUADRANT register contains the quadrant ; Results: ADDR_RAM_HI and ADDR_RAM_LO are set up to point to the ; beginning of the RFDL data area for the correct quad. SETUP_RADDR_RFDL CLRF ADDR_RAM_LO ; clear address registers CLRF ADDR_RAM_HI BSF ADDR_RAM_LO, 7 ; copy bit 0 of QUADRANT to BSF ADDR_RAM_HI, 0 ; bit 7 of LSB of RAM address reg BTFSS QUADRANT, 0 ; and bit 1 of quadrant QUADRANT to BCF ADDR_RAM_LO, 7 ; bit 0 of MSB of RAM address reg BTFSS QUADRANT, 1 BCF ADDR_RAM_HI, 0 RETURN ; end of SETUP_RADDR_RFDL ; This routine sets up the RAM address register to access the XFDL ; memory of a particular quadrant ; Input: QUADRANT register contains the quadrant ; Results: ADDR_RAM_HI and ADDR_RAM_LO are set up to point to the ; beginning of the XFDL data area for the correct quad. SETUP_RADDR_XFDL CLRF ADDR_RAM_LO ; clear address registers CLRF ADDR_RAM_HI BSF ADDR_RAM_HI, 1 ; set bit 1 of MSB of RAM address reg 97 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface BSF BSF BTFSS BCF BTFSS BCF RETURN ADDR_RAM_LO, ADDR_RAM_HI, QUADRANT, 0 ADDR_RAM_LO, QUADRANT, 1 ADDR_RAM_HI, 7 0 7 0 ; ; ; ; copy bit 0 of QUADRANT to bit 7 of LSB of RAM address reg and bit 1 of quadrant QUADRANT to bit 0 of MSB of RAM address reg ; return from subroutine ; !!!!!!!!!!! Watch for this code bumping into the 0x800 boundary ; !!!!!!!!!!! Currently at ~0x794 ;********************************** PAGE 1 ************************************* ;****************************************************************************** * ORG 0x800 ; start of page 1 ;****************************** ;* HANDLER FOR RAM INTERRUPTS * ;****************************** ; Read mailbox and process RAM_INT RD_RAM MAILIN ; read mailbox PAGE1 ; The following is one big CASE statement MOVWF SCRATCH ; save for comparisons XORLW READ_REG ; check for MPH reg read BTFSC STATUS, Z GOTO REG_READ MOVF SCRATCH, 0 ; restore W for next compare XORLW WRITE_REG ; check for MPH reg write BTFSC STATUS, Z GOTO REG_WRITE MOVF SCRATCH, 0 ; restore W for next compare XORLW XFDL_START ; check for start of XFDL packet BTFSC STATUS, Z GOTO CALL_XFDL_PKT_START MOVF SCRATCH, 0 ; restore W for next compare XORLW XBOC_START ; check for transmit BOC command BTFSC STATUS, Z GOTO SETUP_BOC MOVF SCRATCH, 0 ; restore W for next compare XORLW XBOC_STOP ; check for idle BOC command BTFSC STATUS, Z GOTO FINISH_BOC MOVF SCRATCH, 0 ; restore W for next compare XORLW TIMER_ON ; check for enable timer ints command BTFSC STATUS, Z BSF INTCON, T0IE MOVF SCRATCH, 0 ; restore W for next compare XORLW TIMER_OFF ; check for disable timer ints command BTFSC STATUS, Z BCF INTCON, T0IE MOVF SCRATCH, 0 ; restore W for next compare XORLW LLBA ; check for line loopback act. command 98 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO MOVF XORLW BTFSC GOTO RETURN STATUS, Z LLBA_REQ SCRATCH, 0 ; restore W for next compare LLBD ; check for line loopback deact. command STATUS, Z LLBD_REQ SCRATCH, 0 ; restore W for next compare PLBA ; check for payload loopback act. command STATUS, Z PLBA_REQ SCRATCH, 0 ; restore W for next compare PLBD ; check for payload loopback deact. command STATUS, Z PLBD_REQ SCRATCH, 0 ; restore W for next compare DLBA ; check for diag. loopback act. command STATUS, Z DLBA_REQ SCRATCH, 0 ; restore W for next compare DLBD ; check for line loopback deact. command STATUS, Z DLBD_REQ SCRATCH, 0 ; restore W for next compare XAIS_START ; check for start xmit ais command STATUS, Z XAIS_START_REQ SCRATCH, 0 ; restore W for next compare XAIS_STOP ; check for stop xmit ais command STATUS, Z XAIS_STOP_REQ SCRATCH, 0 ; restore W for next compare READ_REG_QDSX ; check for read QDSX command STATUS, Z READ_QDSX_REQ SCRATCH, 0 ; restore W for next compare WRITE_REG_QDSX ; check for write QDSX command STATUS, Z WRITE_QDSX_REQ ; return from subroutine CALL_XFDL_PKT_START PAGE0 ; XFDL_PKT_START is in page 0 CALL XFDL_PKT_START PAGE1 RETURN ; return from subroutine REG_READ RD_RAM REG_ADR_LO ; transfer address MOVWF ADDR_MPH_LO RD_RAM REG_ADR_HI MOVWF ADDR_MPH_HI PAGE0 CALL READ_MPH PAGE1 WR_RAM_D REG_DATA WR_RAM MAILOUT, RW_DONE ; signal end of access MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD RETURN ; return from subroutine REG_WRITE 99 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface RD_RAM REG_ADR_LO ; transfer address MOVWF ADDR_MPH_LO RD_RAM REG_ADR_HI MOVWF ADDR_MPH_HI RD_RAM REG_DATA MOVWF DATA_REG PAGE0 CALL WRITE_MPH PAGE1 WR_RAM MAILOUT, RW_DONE ; signal end of access MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD PAGE1 RETURN ; return from subroutine SETUP_BOC RD_RAM SERVICE_QUAD PAGE0 ; located in PAGE 0 MOVF DATA_REG, W CALL SETUP_MADDR PAGE1 RD_RAM RAM_XBOC ; read in BOC to transmit WR_MPH_DL XBOC_CODE ; start BOC transmission PAGE1 RETURN ; return from subroutine FINISH_BOC RD_RAM SERVICE_QUAD PAGE0 ; located in PAGE 0 MOVF DATA_REG, W CALL SETUP_MADDR PAGE1 WR_MPH_L XBOC_CODE, BOC_TERMINATE ; end BOC transmission PAGE1 RETURN ; return from subroutine LLBA_REQ RD_RAM PAGE0 MOVF CALL PAGE1 RD_RAM PAGE0 MOVF MOVWF CALL PAGE1 RETURN LLBD_REQ RD_RAM PAGE0 MOVF CALL PAGE1 RD_RAM PAGE0 ; handle line loopback activate request SERVICE_QUAD ; located in PAGE 0 DATA_REG, W SETUP_MADDR SERVICE_QUAD ; located in PAGE 0 DATA_REG, W QUADRANT LLA ; return from subroutine ; handle line loopback deactivate request SERVICE_QUAD ; located in PAGE 0 DATA_REG, W SETUP_MADDR SERVICE_QUAD ; located in PAGE 0 100 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVF MOVWF CALL PAGE1 RETURN PLBA_REQ RD_RAM PAGE0 MOVF CALL PAGE1 RD_RAM PAGE0 MOVF MOVWF CALL PAGE1 RETURN PLBD_REQ RD_RAM PAGE0 MOVF CALL PAGE1 RD_RAM PAGE0 MOVF MOVWF CALL PAGE1 RETURN DATA_REG, W QUADRANT LLD ; return from subroutine ; handle payload loopback activate request SERVICE_QUAD ; located in PAGE 0 DATA_REG, W SETUP_MADDR SERVICE_QUAD ; located in PAGE 0 DATA_REG, W QUADRANT PLA ; return from subroutine ; handle payload loopback deactivate request SERVICE_QUAD ; located in PAGE 0 DATA_REG, W SETUP_MADDR SERVICE_QUAD ; located in PAGE 0 DATA_REG, W QUADRANT PLD ; return from subroutine ; deactivate diagnostic loopback ; setup for quadrant DLBA_REQ RD_RAM SERVICE_QUAD PAGE0 MOVF DATA_REG, W CALL SETUP_MADDR PAGE0 RD_MPH_L MSTR_DIAG BSF DATA_REG, 2 WR_MPH_DL MSTR_DIAG PAGE1 RETURN DLBD_REQ RD_RAM SERVICE_QUAD PAGE0 MOVF DATA_REG, W CALL SETUP_MADDR PAGE0 RD_MPH_L MSTR_DIAG BCF DATA_REG, 2 WR_MPH_DL MSTR_DIAG PAGE1 RETURN XAIS_START_REQ RD_RAM SERVICE_QUAD ; read register ; change register ; save register ; deactivate diagnostic loopback ; setup for quadrant ; read register ; change register ; save register ; Start transmit AIS ; setup for quadrant 101 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PAGE0 MOVF DATA_REG, W CALL SETUP_MADDR PAGE0 RD_MPH_L T1TRAN_ALM ; read register BSF DATA_REG, 0 ; change register WR_MPH_DL T1TRAN_ALM ; save register PAGE1 RETURN XAIS_STOP_REQ ; Stop transmit AIS RD_RAM SERVICE_QUAD ; setup for quadrant PAGE0 MOVF DATA_REG, W CALL SETUP_MADDR PAGE0 RD_MPH_L T1TRAN_ALM ; read register BCF DATA_REG, 0 ; change register WR_MPH_DL T1TRAN_ALM ; save register PAGE1 RETURN READ_QDSX_REQ RD_RAM REG_ADR_LO ; transfer address MOVWF ADDR_QDSX_LO RD_RAM REG_ADR_HI MOVWF ADDR_QDSX_HI PAGE0 CALL READ_QDSX PAGE1 WR_RAM_D REG_DATA WR_RAM MAILOUT, RW_DONE ; signal end of access MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD RETURN ; return from subroutine WRITE_QDSX_REQ RD_RAM REG_ADR_LO ; transfer address MOVWF ADDR_QDSX_LO RD_RAM REG_ADR_HI MOVWF ADDR_QDSX_HI RD_RAM REG_DATA MOVWF DATA_REG PAGE0 CALL WRITE_QDSX PAGE1 WR_RAM MAILOUT, RW_DONE ; signal end of access MOVF QUADRANT, W ; indicate which quadrant MOVWF DATA_REG WR_RAM_D INT_QUAD PAGE1 RETURN ; return from subroutine ;******************************** ;* HANDLER FOR TIMER INTERRUPTS * ;******************************** TIMER_INT BANK0 BCF INTCON, T0IF ; clear interrupt flag 102 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface BSF DECFSZ RETURN MOVF BTFSS GOTO MOVLW MOVWF MOVLW MOVWF BSF MOVLW XORWF RETURN TIMEFLAG, 1 ; set 3.2768mS flag TIME_COUNT_L, 1 ; decrement low byte of counter ; return from subroutine TIME_COUNT_H, 0 ; affect Z flag STATUS, Z DECREMENT_COUNTER ONE_SEC_L ; reset counter (1SEC=200NS*64*256*305) TIME_COUNT_L ONE_SEC_H TIME_COUNT_H TIMEFLAG, 0 ; set flag bit 0x80 PORTB, 1 ; toggle LED4 ; return from subroutine DECREMENT_COUNTER DECF TIME_COUNT_H, 1 ; decrement counter RETURN ; return from subroutine ;******************************************** ;* PERFORMANCE REPORT GENERATION SUBROUTINE * ;******************************************** GENERATE_PRM MOVWF MOVWF BCF RLF RLF RLF ADDLW MOVWF MOVLW ADDWF MOVF SUBWF SUBWF WORK2 WORK3 STATUS, C WORK3, F WORK3, F WORK3, W 0x06 FSR Q1_PRM_1B1 FSR, F PRM_COUNTER, W FSR, F FSR, F ; save quadrant to WORK2 CLRF INCF MOVF MOVWF DECF RTXCP INDF FSR, F PRM_COUNTER, W INDF FSR, F ; setup to access performance ; report register according ; to quadrant and PRM counter ; in order for the history ; to work properly, we must write ; in the opposite direction that ; we read, hence we start with ; Q1_PRM_4B1 and subtract PRM_COUNTER ; clear performance report byte 1 ; copy performance report counter ; bits into performance report byte 2 ; this is ok because bits 2-7 = 0 RXCP and TXCP counters to RAM ;Shadow INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_UHCSL1 ; MOVLW 0xFF ; ANDWF DATA_REG, F ; WR_RAM_DP RXCP_UHCSL1_RAM ; INTSON read uncorrectable HCS error count LSB Mask off unused bits copy to ram 103 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_UHCSM1 MOVLW 0x0F ANDWF DATA_REG, F WR_RAM_DP RXCP_UHCSM1_RAM INTSON INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_CHCSL1 MOVLW 0xFF ANDWF DATA_REG, F WR_RAM_DP RXCP_CHCSL1_RAM INTSON INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_CHCSM1 MOVLW 0x0F ANDWF DATA_REG, F WR_RAM_DP RXCP_CHCSM1_RAM INTSON INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_IDLEL1 MOVLW 0xFF ANDWF DATA_REG, F WR_RAM_DP RXCP_IDLEL1_RAM INTSON INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_IDLEM1 MOVLW 0xFF ANDWF DATA_REG, F WR_RAM_DP RXCP_IDLEM1_RAM INTSON INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_RECVL1 MOVLW 0xFF ANDWF DATA_REG, F WR_RAM_DP RXCP_RECVL1_RAM INTSON ; ; ; ; read uncorrectable HCS error count MSB Mask off unused bits copy to ram ; ; ; ; read correctable HCS error count LSB Mask off unused bits copy to ram ; ; ; ; read uncorrectable HCS error count LSB Mask off unused bits copy to ram ; ; ; ; read Idle/unassigned cell count LSB Mask off unused bits copy to ram ; ; ; ; read Idle/unassigned cell count MSB Mask off unused bits copy to ram ; ; ; ; read RXCP recieive cell count LSB Mask off unused bits copy to ram 104 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L RXCP_RECVM1 MOVLW 0xFF ANDWF DATA_REG, F WR_RAM_DP RXCP_RECVM1_RAM INTSON INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L TXCP_XMITL1 MOVLW 0xFF ANDWF DATA_REG, F WR_RAM_DP TXCP_XMITL1_RAM INTSON INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L TXCP_XMITM1 MOVLW 0xFF ANDWF DATA_REG, F WR_RAM_DP TXCP_XMITM1_RAM INTSON ; ; ; ; read RXCP recieive cell count MSB Mask off unused bits copy to ram ; ; ; ; read TXCP transmit cell count LSB Mask off unused bits copy to ram ; ; ; ; read TXCP transmit cell count MSB Mask off unused bits copy to ram G_BITS INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L CRCM1 MOVLW 0x02 ANDWF DATA_REG, F WR_RAM_DP CRCM1_RAM MOVF DATA_REG, W INTSON PAGE1 BTFSS STATUS, Z GOTO BE_256PLUS INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L CRCL1 WR_RAM_DP CRCL1_RAM MOVF DATA_REG, W INTSON PAGE1 BTFSC STATUS, Z GOTO SEF_BIT XORLW 0x01 BTFSS STATUS, Z ; read MSB of CRC count ; mask off unused bits ; copy it to RAM ; is MSB of CRC count > 0 ? ; read LSB of CRC count ; copy it to RAM ; is LSB of CRC count = 0 ? ; yes then no need to set any G bits ; is LSB of CRC count = 1 ? 105 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface GOTO INCF BSF DECF GOTO BE_2PLUS MOVF SUBLW BTFSS GOTO INCF BSF DECF GOTO BE_6PLUS MOVF SUBLW BTFSS GOTO BSF GOTO BE_11PLUS MOVF SUBLW BTFSS GOTO BSF GOTO BE_101PLUS BSF BE_2PLUS FSR, F INDF, PRM_G1 FSR, F SEF_BIT DATA_REG, W 0x05 STATUS, C BE_6PLUS FSR, F INDF, PRM_G2 FSR, F SEF_BIT DATA_REG, W 0x0A STATUS, C BE_11PLUS INDF, PRM_G3 SEF_BIT DATA_REG, W 0x64 STATUS, C BE_101PLUS INDF, PRM_G4 SEF_BIT INDF, PRM_G5 ; yes then ; set G1 ; is LSB of CRC count < 6 ? ; yes then ; set G2 ; is LSB of CRC count < 11 ? ; yes then set G3 ; is LSB of CRC count < 101 ? ; yes then set G4 ; CRC count must be 100 106 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface PAGE0 MOVF CALL INTSON PAGE1 BTFSC GOTO INCF BSF DECF PAGE1 GOTO FE_BIT MOVF INTSON PAGE1 BTFSC GOTO INCF BSF DECF LV_BIT WORK2, W SETUP_MADDR SEF, WORK2 FE_BIT FSR, F INDF, PRM_SE FSR, F LV_BIT DATA_REG, W STATUS, Z LV_BIT FSR, F INDF, PRM_FE FSR, F ; is framing error count >= 1 ? ; yes then ; set FE ; is severely errored frame count >= 1 ? ; yes then ; set SE INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L LCVL1 ; read LSB of line code violation WR_RAM_DP LCVL1_RAM ; copy it to RAM MOVF DATA_REG, W INTSON PAGE1 BTFSC STATUS, Z ; is line code violation LSB >= 1 GOTO LCVL_ZERO BSF INDF, PRM_LV ; yes then set LV ; but have to read/copy MSB of line ; code violation anyway LCVL_ZERO INTSOFF PAGE0 MOVF WORK2, W CALL SETUP_MADDR RD_MPH_L LCVM1 ; read MSB of line code violation MOVLW 0x0F ; mask off unused bits ANDWF DATA_REG, F WR_RAM_DP LCVM1_RAM ; copy it to RAM MOVF DATA_REG, W INTSON PAGE1 BTFSC STATUS, Z ; is line code violation MSB >= 1 GOTO SL_BIT BSF INDF, PRM_LV ; yes then set LV SL_BIT BCF INDF, PRM_SL ; slip bit is always zero LB_BIT INCF FSR, F ; set LB if this quadrant is in ; payload loopback INTSOFF PAGE0 MOVF WORK2, W count ? count ? 107 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CALL SETUP_MADDR RD_MPH_L MSTR_DIAG ; read master diagnostic register ; to check for payload loopback INTSON PAGE1 BSF INDF, PRM_LB BTFSS DATA_REG, 5 BCF INDF, PRM_LB MOVLW MOVWF MOVF ADDWF CLRF Q1_PRM_PTR FSR WORK2, W FSR, F INDF ; clear the PRM pointer BTSS_QUAD_BIT WORK2, XFDL_BUSY GOTO PRM_ENBL_XFDL BS_QUAD_BIT WORK2, XFDL_PENDING RETURN PRM_ENBL_XFDL BS_QUAD_BIT WORK2, XFDL_BUSY ; set XFDL busy bit BS_QUAD_BIT WORK2, XFDL_USR_OR_PRM ; set user/PRM bit to PRM MOVF WORK2, W INTSOFF PAGE0 CALL SETUP_MADDR RD_MPH_L XFDL_CONFIG BSF DATA_REG, 3 ; enable XFDL interrupts WR_MPH_DL XFDL_CONFIG PAGE1 INTSON RETURN ; end of GENERATE_PRM ;************************************* ;* PERFORMANCE MONITORING SUBROUTINE * ;************************************* PMON BCF TIMEFLAG, 0 ; clear the 1 sec. flag ; Write to MPH to update all PMON counters INTSOFF WR_MPH GLOBAL_PMON, 00 INTSON PAGE1 PMON_LOOP RD_MPH PAGE1 BTFSC GOTO INCF ANDLW MOVWF MOVLW CALL MOVLW CALL GLOBAL_PMON DATA_REG, 3 PMON_LOOP PRM_COUNTER, W 0x03 PRM_COUNTER 0x00 GENERATE_PRM 0x01 GENERATE_PRM ; tight loop until PMON registers are updated ; increment performance report counter ; and take modulus 4 ; ; ; ; create performance report messages and make RAM copies of performance monitoring statistics for each quadrant 108 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface MOVLW CALL MOVLW CALL 0x02 GENERATE_PRM 0x03 GENERATE_PRM ; signal update to host ; indicate which quadrant INTSOFF WR_RAM MAILOUT, PMON_UPDATE MOVF QUADRANT, W MOVWF DATA_REG WR_RAM_D INT_QUAD INTSON RETURN END ; return from subroutine ;** END OF SOURCE FILE ** 109 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface CONTACTING PMC-SIERRA PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, B.C. Canada V5A 4V7 Telephone: 604-415-6000 Facsimile: 604-415-6200 Product Information: Applications information: World Wide Web Site: info@pmc-sierra.bc.ca apps@pmc-sierra.bc.ca http://www.pmc-sierra.com 110 PMC-Sierra, Inc. REFERENCE DESIGN PMC-960951 ISSUE 2 PM7344 S/UNI-MPH SATURN QUAD T1/E1 Multi-PHY User Network Interface NOTES ______________________________________________________________________________________________ Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of third-party rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1997 PMC-Sierra, Inc. PMC-960951 Printed in Canada Issue date: June, 1997 PMC-Sierra, Inc.105 - 8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415 6000 |
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