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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
PM7545 S/UNI-PDH-EVBD
REFERENCE DESIGN FOR S/UNI-PDH
Preliminary Information Issue 2, January, 1995
_______________________________________________________________________________________ PMC-Sierra, Inc. 8501 Commerce Court Burnaby, BC Canada V5A 4N3 604 668 7300
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
CONTENTS OVERVIEW........................................................................................................................1 FUNCTIONAL DESCRIPTION.......................................................................................2 SCI-PHY Interface ..................................................................................................3 Microprocessor interface.......................................................................................3 Indicators..................................................................................................................3 PM7345 S/UNI-PDH ..............................................................................................3 On Board Oscillators ..............................................................................................4 PLCP Stuff Control .................................................................................................4 T1XC .........................................................................................................................4 E1XC.........................................................................................................................5 DS3 LIU....................................................................................................................5 E3 LIU .......................................................................................................................5 DS1 Line Interface..................................................................................................6 E1 Line Interface.....................................................................................................6 DS3 Line Interface..................................................................................................6 E3 Line Interface.....................................................................................................6 S/UNI-PDH EVBD CONNECTOR SIGNAL DESCRIPTIONS..................................7 Daughterboard Microprocessor Connector.......................................................7 Daughterboard SCI-PHY Connector Interface..................................................10 Line Interface Signals............................................................................................13 Header Descriptions ..............................................................................................13 Power Connector....................................................................................................23 OPERATION......................................................................................................................24 Operation with SCI-PHY Motherboard ...............................................................24 Operation in Loopback Mode...............................................................................24 ELECTRICAL SPECIFICATIONS .................................................................................25 SCI-PHY ATM and Microprocessor Interface....................................................25 Line Interface Signals............................................................................................25 S/UNI-PDH EVBD Power......................................................................................25 STOCK LIST.....................................................................................................................26
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
REFERENCES .................................................................................................................30 APPENDIX 1: COMPONENT PLACEMENT DIAGRAM............................................31 APPENDIX 2: SUGGESTED REVISIONS ..................................................................32 APPENDIX 3: SCHEMATICS........................................................................................33 APPENDIX 4: EXAMPLE FORTH WORDS .................................................................34 APPENDIX 5: EXAMPLE BOARD LAYOUT................................................................35
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
OVERVIEW The PM7545 S/UNI-PDH EVBD is a versatile board used to perform functional testing of the S/UNI-PDH PM7345 chip (PDH). The board allows for complete functional testing of the S/UNI-PDH device at DS3 and E3 rates of 44.736 Mbit/s and 34.368 Mbit/s, as well as at DS1 and E1 rates of 1.544 Mbit/s and 2.048 Mbit/s. The board can be used with the SATURN COMPLIANT INTERFACE FOR ATM PHYSICAL LAYER INTERCONNECT EVALUATION MOTHER BOARD (SCI-PHY EVMB), or it can be used stand alone with reduced functionality. The S/UNI-PDH EVBD is normally configured, monitored, and powered through two 96 pin DIN connectors that mate directly to the SCI-PHY EVMB. There is a power connector and fuse for the application of +5V and ground directly to the S/UNI-PDH EVBD. There are four PM7345 S/UNI-PDH devices on the S/UNI-PDH EVBD. One PM7345 is configured for operation at DS1, another one at E1, one at DS3, and the last one at E3. The rate that each S/UNI-PDH works at is fixed by the board design. The DS1 format S/UNI-PDH utilizes the PMC PM4341 T1XC T1 framer and transceiver. The DS3/E3 format S/UNI-PDHs utilize the internal PDH T3/E3 framer and the external Silicon Systems SSI78P7200 DS3/E3 LIU. The E1 format S/UNIPDH utilizes the PMC PM6341 E1XC E1 framer and transceiver. The E3 format S/UNI-PDH can also be put into a special Loopback mode whereby parallel ATM bus receive signals are looped back into the transmit side. The rest of the S/UNIPDH devices will not function in this mode. Line side connections use BNC and Bantam connectors. One of the 96 pin DIN connectors is a generic microcontroller port. The second 96 pin DIN connector contains signals necessary to implement ATM cell transfer. All four S/UNI-PDH PM7345 devices have microprocessor interfaces that are accessible through the DIN connector. Control of the T1XC, E1XC, and 78P7200 devices is accomplished via the same connector. Twenty four general purpose parallel input/output (PIO) lines are also accessible through the same connector. PIO lines are used to control and monitor various signals on the S/UNI-PDH EVBD. Headers are provided for PLCP and DS3/E3 overhead insertion and extraction. Headers are also provided for HDLC signals and other pertinent control/status signals. Each S/UNI-PDH PM7345 is independently configurable and has its own LIU. All four PM7345 share data signals on the ATM bus side and are individually selectable under microprocessor control.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
FUNCTIONAL DESCRIPTION Fig 1. Block Diagram
Indicators PLCP Stuff Control 1.544 MHz Osc 37.056 MHz Osc
96 Pin DIN Plug Connector
SCI-PHY ATM BUS
RX TX
8 8
S/UNI-PDH PM7345 #1
T1XC
TX/RX ENB
PLCP Stuff Control
2.048 MHz Osc
49.152 MHz Osc
S/UNI-PDH PM7345 #2
TX/RX ENB
E1XC
S/UNI-PDH PM7345 #3
TX/RX ENB
DS3 LIU 78P7200
Microprocessor Interface
96 Pin DIN Plug Connector
S/UNI-PDH PM7345 #4
TX/RX ENB DATA 8 ADDRESS 8 CONTROL
E3 LIU 78P7200
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E3 Line Interface
PLCP Stuff Control
34.368 MHz Osc
DS3 Line Interface
PLCP Stuff Control
44.736 MHz Osc
E1 Line Interface
DS1 Line Interface
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
SCI-PHY Interface The SCI-PHY interface provides a standard connection to the S/UNI-PDH ATM drop side according the SCI-PHY specification. The 96 pin DIN SCI-PHY connector contains parallel ATM receive and transmit signals along with the required FIFO control signals and clocks. The PDH devices on the S/UNI-PDH EVBD utilize 8 bit parallel transmit and receive ATM transfers. The SCI-PHY interface contains signals that support multiple physical layer devices. Since there are four S/UNI-PDH PM7345 on the EVBD, the SCI-PHY interface will be supporting its maximum number of physical layer devices. Also included in the SCI-PHY connector is a +5V supply. The SCI-PHY interface was designed to be electrically compatible with the SCI-PHY EVMB. Microprocessor interface The Microprocessor interface is a generic microprocessor interface. The interface contains data, address, and control lines compatible with the SCI-PHY EVMB microprocessor interface and is available on a 96 pin DIN connector. These signals are directly connected to the microprocessor ports on the four S/UNI-PDH PM7345 devices, the T1XC, and the E1XC. Six chip select lines are use to control the programmable devices on the board. In addition, this interface contains 24 parallel input/output (PIO) lines, 16 of which are used by the S/UNI-PDH EVBD. The mother board's PIO lines come from an undedicated 8255 PIO on that board. PIO lines are used to provide control over each PM7345's 8 kHz reference for PLCP stuff control (C13/CADD). PIO lines are used to control the two 78P7200 devices. PIO input lines are used to monitor low received line signal level on the 78P7200 LIUs. PIO inputs also monitor Loss of Frame signals from the PM7345s. Indicators There are five LEDs provided for visual status. One LED lights when a source of five volts is provided to the S/UNI-PDH EVBD. The other four LEDs light up when Loss of Cell Delineation (LCD) occurs for the individual S/UNI-PDH PM7345 chips. PM7345 S/UNI-PDH
The PM7345 devices are the heart of the S/UNI-PDH EVBD. They are ATM physical layer processors with integrated DS3 and E3 framing. PLCP sublayer DS1, DS3, E1, and E3 processing is supported as is ATM cell delineation. All traffic goes through the PM7345s. Each PM7345 is setup through the microprocessor interface. All the internal registers are accessed through this interface. When a PM7345 is configured for DS3 transmission, the overhead bits are inserted and extracted on an external serial interface. The DS3 overhead interface signals are brought out to a header. When PLCP framing is enabled, the PLCP overhead octets are inserted and extracted on an external serial interface that is also brought out to headers. All ATM data is passed through the parallel SCI-PHY data bus.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Because there are four physical layer devices sharing the ATM parallel data buses, device select signals on the SCI-PHY DIN connector are utilized to select a particular PM7345 in the transmit and receive directions. S/UNI-PDH device 4 can be put into a special Loopback mode using jumpers on the board. This will allow Loopback testing on the ATM parallel bus side. All other S/UNI-PDH devices do not function in this mode. When a PM7345 is configured for DS1 or E1 transmission sublayer processing, a unipolar signal with the appropriate clock and framing is provided and expected. For a complete description of the PM7345, refer to the PM7345 data sheet. On Board Oscillators Each S/UNI-PDH PM7345 device requires an oscillator feeding its TICLK pin . This clock source is used to generate the transmit clock for line side transmissions. S/UNI-PDH device 1 uses a 1.544 MHz oscillator for DS1 transmissions. S/UNIPDH device 2 uses a 2.048 MHz oscillator for E1 transmissions. S/UNI-PDH device 3 uses a 44.736 MHz oscillator for DS3 transmissions. S/UNI-PDH device 4 uses a 34.368 MHz oscillator for E3 transmissions. The T1XC device uses a 37.056 MHz oscillator on pin XCLK for internal timing generation. The E1XC device uses a 49.152 MHz oscillator on pin XCLK for internal timing generation. PLCP Stuff Control The PM7345 S/UNI-PDH devices provide stuffing control for T3 PLCP (nibble stuffing) and E3 PLCP (byte stuffing) frame formats via the C13/CADD pin. The PLCP Stuff Control block allows this pin to be controlled by one of two reference sources to produce a nominal 125 microsecond PLCP frame rate. The source is either the result of a phase comparison between the transmit PLCP frame rate and receive PLCP frame rate (loop time operation) or the result of a phase comparison between the transmit PLCP frame rate and a generated 8 KHz clock. The 8 KHz clock is generated using the onboard 1.544 MHz crystal oscillator and 22V10 PALs. T1XC The PM4341 T1XC is a full featured T1 transceiver with an integrated framer and line analog circuitry. A 37.056 MHz oscillator is used by its internal digital PLL for clock and data recovery. All internal registers for configuration, control, and status monitoring are accessible through its microprocessor interface. The analog line interface is brought out to Bantam connectors. Headers are provided for the digital transmit and receive interface as well as the facility data link (FDL) interface. Also note that the T1XC is connected on the digital signal side to PM7345 S/UNI-PDH device 1. For a complete description of the T1XC, refer to the PM4341 datasheet.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
E1XC The PM6341 E1XC is a full featured E1 transceiver with an integrated framer and line analog circuitry. A 49.152 MHz oscillator is used by its internal digital PLL for clock and data recovery. All internal registers for configuration, control, and status monitoring are accessible through its microprocessor interface. The analog line interface is brought out to Bantam connectors. Headers are provided for the digital transmit and receive interface as well as the facility data link (FDL) interface. Also note that the E1XC is connected on the digital signal side to PM7345 S/UNI-PDH device 2. For a complete description of the E1XC, refer to the PM6341 datasheet DS3 LIU A Silicon Systems 78P7200 DS3 line interface unit (LIU) is used to convert the digital B3ZS-encoded AMI encoded data to its analog equivalent and to convert analog B3ZS-encoded AMI to its digital equivalent. The LIU has 3 main control inputs for controlling the transmitter. If the received signal falls below the required threshold, a status signal, LOWSIGB, is asserted. The transmitter control and LOWSIGB signals are accessible via PIO lines. These lines would be under microprocessor control if the SCI-PHY EVMB was connected to the S/UNI-PDH EVBD. Also note that the 78P7200 DS3 LIU is connected on the digital signal side to PM7345 S/UNI-PDH device 3. For a complete description of the 78P7200, refer to the datasheets in Silicon Systems Communication Products databook. E3 LIU A Silicon Systems 78P7200 E3 line interface unit (LIU) is used to convert the digital HDB3-encoded AMI encoded data to its analog equivalent and to convert analog HDB3-encoded AMI to its digital equivalent. The LIU has 3 main control inputs for controlling the transmitter. If the received signal falls below the required threshold, a status signal, LOWSIGB, is asserted. The transmitter control and LOWSIGB signals are accessible via PIO lines. These lines would be under microprocessor control if the SCI-PHY EVMB were connected to the S/UNI-PDH EVBD. Also note that the 78P7200 E3 LIU is connected on the digital signal side to PM7345 S/UNI-PDH device 4. For a complete description of the 78P7200, refer to the datasheets in Silicon Systems Communication Products databook.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
DS1 Line Interface The S/UNI-PDH EVBD provides for the standard DS1 100 ohm analog interface. Two Bantam connectors are provided. E1 Line Interface The S/UNI-PDH EVBD provides for the standard E1 120 ohm analog interface. Two Bantam connectors are provided. DS3 Line Interface The S/UNI-PDH EVBD provides for the standard DS3 75 ohm analog interface. Two BNC connectors are provided. E3 Line Interface The S/UNI-PDH EVBD provides for the standard E3 75 ohm analog interface. Two BNC connectors are provided.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
S/UNI-PDH EVBD CONNECTOR SIGNAL DESCRIPTIONS Daughterboard Microprocessor Connector The Daughterboard Microprocessor Connector Interface is made up of a 96 pin DIN plug connector designed to mate with a corresponding connector on the SCI-PHY mother board. The connector consists of signals appropriate to read and write the registers of the S/UNI-PDH EVBD. It also provides the necessary power and ground. CMOS signal levels are used on this interface. Si g n a l Name PIO1A[0] Type I Pin A1 Function Connected to C13REF1. This signal selects between the 1.544 MHz crystal (divided by 193) or RPOHFP1 as the onboard source of the C13/CADD pin on S/UNI-PDH device 1. Connected to C13REF2. This signal selects between the 1.544 MHz crystal (divided by 193) or RPOHFP2 as the onboard source of the C13/CADD pin on S/UNI-PDH device 2. Connected to C13REF3. This signal selects between the 1.544 MHz crystal (divided by 193) or RPOHFP3 as the onboard source of the C13/CADD pin on S/UNI-PDH device 3. Connected to C13REF4. This signal selects between the 1.544 MHz crystal (divided by 193) or RPOHFP4 as the onboard source of the C13/CADD pin on S/UNI-PDH device 4. Connected to C13SEL1. This signals controls which 8 kHz reference signal goes to the C13/CADD pin on S/UNI-PDH device 1 Connected to C13SEL2. This signals controls which 8 kHz reference signal goes to the C13/CADD pin on S/UNI-PDH device 2. Connected to C13SEL3. This signals controls which 8 kHz reference signal goes to the C13/CADD pin on S/UNI-PDH device 3. Connected to C13SEL4. This signals controls which 8 kHz reference signal goes to the C13/CADD pin on S/UNI-PDH device 4. Connected to LOF1. Loss of frame for S/UNI-PDH device 1. Connected to LOF2. Loss of frame for S/UNI-PDH device 2.
PIO1A[1]
I
A2
PIO1A[2]
I
A3
PIO1A[3]
I
A4
PIO1A[4] PIO1A[5] PIO1A[6] PIO1A[7] PIO1B[0] PIO1B[1]
I I I I O O
A5 A6 A7 A8 A9 A10
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
PIO1B[2] PIO1B[3] PIO1B[4] PIO1B[5] PIO1B[6] PIO1B[7] PIO1C[0] PIO1C[1] PIO1C[2] PIO1C[3] PIO1C[4] PIO1C[5] PIO1C[6] PIO1C[7] CSB0 CSB1 CSB2 CSB3 CSB4 CSB5 CSB6 CSB7 GND PWR+5V
O O O O O O I I I I I I I I I I I I I I NC NC P P
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 B1 to B26 B27 to B32
Connected to LOF3. Loss of frame for S/UNI-PDH device 3 Connected to LOF4. Loss of frame for S/UNI-PDH device 4. Not used Not used Connected to DS3LOWSIG. Low receive line level for DS3 78P7200 LIU. Connected to E3LOWSIG. Low receive line level for E3 78P7200 LIU. Connected to DS3LBO. Controls line buildout function on DS3 78P7200 LIU. Connected to DS3OPT1. Controls transmitter output power on DS3 78P7200 LIU. Connected to DS3OPT2. Controls transmitter enable on DS3 78P7200 LIU. Not used Connected to E3LBO. Controls line build out function on E3 78P7200 LIU. Connected to E3OPT1. Controls transmitter output power on E3 78P7200 LIU. Connected to E3OPT2. Controls transmitter enable on E3 78P7200 LIU. Not used Active low chip select for S/UNI-PDH device 1. Active address range C000H - C0FFH. Active low chip select for S/UNI-PDH device 2. Active address range C100H - C1FFH. Active low chip select for S/UNI-PDH device 3. Active address range C200H - C2FFH. Active low chip select for S/UNI-PDH device 4. Active address range C300H - C3FFH. Active low chip select for T1XC. Active address range C400H - C4FFH. Active low chip select for E1XC. Active address range C500H - C5FFH. Not used Not used. Ground. +5V power.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
RST RSTB WRB RDB ALE
NC I I I I
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32
HC11_IRQB O HC11_ XIRQB PIO_RSTB D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] NC NC I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I NC NC NC NC NC NC NC NC
Not Connected Active low hardware reset connected to RSTB line of S/UNI-PDH devices, T1XC, and E1XC. Active low write strobe to S/UNI-PDH devices, T1XC, and E1XC. Active low read strobe to S/UNI-PDH devices, T1XC, and E1XC. Address latch enable. When high, identifies that address is valid on D[7:0]. Connected to the four S/UNI-PDH devices, T1XC, and E1XC. Maskable 68HC11 interrupt. Connected to the four S/UNI-PDH devices, the T1XC, and the E1XC interrupt pins (INTB). Not used Not used Eight bit microprocessor data bus. Connected to the four S/UNI-PDH devices, T1XC, and the E1XC data lines.
Sixteen bit microprocessor address bus. Lower eight bits are connected to the S/UNI-PDH devices, T1XC, and E1XC address lines. Higher address lines are unconnected.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Daughterboard SCI-PHY Connector Interface The Daughterboard SCI-PHY connector is the parallel ATM drop side interface made up of a 96 pin DIN plug connector and is designed to mate with a corresponding connector on the SCI-PHY mother board. It consists of signals required by the SCIPHY interface. Please refer to the PMC-940212, SATURN COMPLIANT INTERFACE FOR ATM DEVICES document for interface timing details. CMOS signal levels are used on this interface. Signal Name TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] Type I I I I I I I I NC NC NC NC NC NC NC NC O O O O O O O O NC NC NC NC NC NC NC NC Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 Function Transmit Data. TDAT[7:0] is used to transfer ATM cells to an ATM PHY daughterboard. TDAT[15:8] are not connected.
Receive Data. RDAT[8:0] is used to transfer ATM cells from an ATM PHY daughterboard. RDAT[15:8] are not connected.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
GND PWR-2V PWR-4.5V PWR+5V TFCLK GND TSOC TXPRTY[0] TXPRTY[1] TCA1 TCA2 TCA3 TCA4 TWREN1B TWREN2B TWREN3B TWREN4B PD2_MISO PD3_MOSI GND RFCLK
P NC NC P I P I I NC O O O O I I I I NC NC P I
B1 to B23 B24 B25 to B28 B29 to B32 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
Ground. Not Connected. Not Connected. +5V power. Supplies S/UNI-PDH devices with a TFCLK signal up to 25 MHz. Ground. Transmit Start Of Cell. TSOC marks the start of cell on the TDAT bus. TSOC drives all S/UNI-PDH devices' TSOC input. Transmit Parity. TXPRTY[0] drives all S/UNI-PDH devices' TXPRTY input. Not connected Transmit cell available. Connected to S/UNI-PDH device 1 TCA output. Transmit cell available. Connected to S/UNI-PDH device 2 TCA output. Transmit cell available. Connected to S/UNI-PDH device 3 TCA output. Transmit cell available. Connected S/UNI-PDH device 4 TCA output. The Transmit Write Enable. TWREN1B drives the TWRENB signal of S/UNI-PDH device 1. The Transmit Write Enable. TWREN2B drives the TWRENB signal of S/UNI-PDH device 2. The Transmit Write Enable. TWREN3B drives the TWRENB signal of S/UNI-PDH device 3. The Transmit Write Enable. TWREN4B drives the TWRENB signal of S/UNI-PDH device 4. Not connected Not connected Ground. Receive FIFO clock. RFCLK is used to synchronize data transfer transactions from the ATM PHY daughterboard. RFCLK supplies a 25 MHz clock and is connected to all S/UNI-PDH devices' RFCLK input. Ground.
GND
P
C18
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
RSOC
O
C19
RXPRTY[0] RXPRTY[1] RCA1
O NC O
C20 C21 C22
RCA2
O
C23
RCA3
O
C24
RCA4
O
C25
RRDEN1B RRDEN2B RRDEN3B RRDEN4B
I I I I
C26 C27 C28 C29 C30 C31 C32
PD4_SCLK NC PD5_SS NC BUS8 NC
Receive Start Of Cell. RSOC marks the start of cell on the RDAT bus. When RSOC is high, the first word of the cell structure should be present on the RDAT bus. RSOC is sampled on the rising edge of RFCLK and is considered valid only when RRDENB is simultaneously asserted. RSOC is connected to each S/UNI-PDH devices' RSOC output. Receive parity. RXPRTY[0] should indicate the parity of the RDAT[7:0] bus. RXPRTY[0] is connected to all S/UNI-PDH devices' RXPRTY output. Not Connected Receive Cell Available. RCA1 is used by an ATM physical layer device to indicate when it can provide a full cell. RCA1 is connected to the S/UNI-PDH device 1 RCA output. Receive Cell Available. RCA2 is used by an ATM physical layer device to indicate when it can provide a full cell. RCA2 is connected to the S/UNI-PDH device 2 RCA output. Receive Cell Available. RCA3 is used by an ATM physical layer device to indicate when it can provide a full cell. RCA3 is connected to the S/UNI-PDH device 3 RCA output. Receive Cell Available. RCA4 is used by an ATM physical layer device to indicate when it can provide a full cell. RCA4 is connected to the S/UNI-PDH device 4 RCA output. The Receive Read Enable. RRDEN1B is connected to S/UNI-PDH device 1 RRDENB input. The Receive Read Enable. RRDEN2B is connected to S/UNI-PDH device 2 RRDENB input. The Receive Read Enable. RRDEN3B is connected to S/UNI-PDH device 3 RRDENB input. The Receive Read Enable. RRDEN4B is connected to S/UNI-PDH device 4 RRDENB input. Not connected Not connected Not connected
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Line Interface Signals The S/UNI-PDH EVBD contains four S/UNI-PDH devices that operate with four different line interface formats. These input and output signals are transformer isolated. Signal+ TXDS1P RXDS1P TXE1P RXE1P TXDS3P RXDS3N TXE3P RXE3P SignalTXDS1N RXDS1N TXE1N RXE1N TXDS3N RXDS3N TXE3N RXE3N Description DS1 balanced TX outputs. DS1 balanced RX inputs. E1 balanced TX outputs. E1 balanced RX inputs. DS3 unbalanced TX outputs. DS3 unbalanced RX inputs. E3 unbalanced TX outputs. E3 unbalanced RX inputs.
Header Descriptions Several jumper terminals are used as test headers to test and monitor certain S/UNI-PDH EVBD signal lines. CMOS signal levels are used for all inputs and outputs. Header J4 (page 2 of schematics) Header J4 is a 5 row by 2 column header whose function is to monitor signals common to the four S/UNI-PDH devices. The selection of operating modes is given in the OPERATION section. The signals on the header are described in the next table. Si g n a l TFCLK +5V RFCLK +5V TSOC GND RSOC GND IRQB GND PIN # 1 2 3 4 5 6 7 8 9 10 Description ATM Transmit FIFO clock. Clock for transferring ATM parallel data into the S/UNI-PDH devices. Power ATM Receive FIFO clock. Clock for transferring ATM parallel data out of the S/UNI-PDH devices. Power Transmit start of Cell. TSOC marks the start of cell on the TDAT data bus. Ground Receive start of cell. RSOC marks the start of cell on the RDAT data bus. Ground Maskable interrupt to the controlling microprocessor via the microprocessor interface. Ground
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Headers J13, J12, J9, J20 (pages 3, 4, 5, 6 of schematics) Headers J13, J12, J9, J20 are 8 row by 2 column headers. These headers are described together because they serve identical functions for each S/UNI-PDH device. They are used to monitor HDLC signals as well as TICLK and LCD for the four S/UNI-PDH devices. They are also used to bring an external source of 8 kHz signal via EXTC13 for C13/CADD generation, and to control the TSEN input for each S/UNI-PDH device. J13 services S/UNI-PDH device 1, J12 is for device 2, J9 is for device 3, and J20 is for device 4. The signals on the headers are described in the next table. Note that each signal has an * at the end of its name. When referring to a specific signal on the header for a S/UNI-PDH device, just replace the * with the S/UNI-PDH device number (1 to 4). Si g n a l GND TDLSIG* GND TDLCLK* GND TSEN* PIN # 1 2 3 4 5 6 Description Ground HDLC transmit data input to S/UNI-PDH. Ground HDLC transmit data clock. Ground Tristate enable for RDAT bus, RXPRTY, and RSOC pins. When TSEN is a logic 0 RDAT bus , RXPRTY, and RSOC are always active and are forced to digital logic values. Ground HDLC receive data clock. Ground HDLC receive data output from S/UNI-PDH. Ground External source for 8 kHz signal for C13/CADD generation. Ground TICLK is the S/UNI-PDH transmission system baud clock. Ground Loss of Cell Delineation indication. LCD transitions to a logic 1 when an out of cell delineation is found.
GND RDLCLK* GND RDLSIG* GND EXTC13* GND TICLK* GND LCD*
7 8 9 10 11 12 13 14 15 16
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PMC-Sierra, Inc.
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PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Headers J11, J10, J7, J14 (pages 3, 4, 5, 6 of schematics) Headers J11, J10, J7, J14 are 20 pin headers. These headers are described together because they serve identical functions for each S/UNI-PDH device. They are used to monitor PLCP as well as overhead stuff signals for the four S/UNI-PDH devices. They are also used to bring external PLCP and overhead stuff signals to each S/UNI-PDH device. These headers are also used to monitor LOF, OOF, TCELL, RCELL, TCA, and RCA for each S/UNI-PDH device. J11 services S/UNIPDH device 1, J10 is for device 2, J7 is for device 3, and J14 is for device 4.The signals on the header are described in the next table. Note that each signal has an * at the end of its name. When refering to a specific signal on the header for a S/UNI-PDH device, just replace the * with the S/UNI-PDH device number (1 to 4). Si g n a l PIN # XTOHCLK* 1 XTOHFP* XTOHINS* XTOH* 2 3 4 Description Buffered transmit overhead clock. XTOH*, XTOHINS*, are sampled on the rising edge of XTOHCLK* Buffered transmit overhead frame position. XTOHFP* is updated on the falling edge of XTOHCLK*. Buffered transmit overhead insertion. Controls insertion of overhead bit into XTOH* stream. Buffered transmit overhead data. Contains overhead bits that are inserted into DS3, E3 transmit streams. Buffered transmit PLCP overhead clock. XTPOH*, and XTPOHINS* are sampled on the rising edge of XTPOHCLK*. Buffered transmit PLCP overhead frame position. XTPOHFP* is updated on the falling edge of XTPOHCLK*. Buffered transmit PLCP overhead insertion. Controls insertion of PLCP overhead bits into XTPOH* stream. Buffered transmit PLCP overhead data. Contains PLCP overhead bits that are inserted into the transmit PLCP frame. Transmit cell indication. TCELL* Pulses once for every ATM cell transmitted. Transmit cell available. TCA* is a logic 1 when the cell based transmit FIFO is empty. It is a logic 0 when the FIFO contains cells. Receive cell indication. RCELL* pulses once for every ATM cell received. Receive cell available. RCA* is a logic 1 when the cell based received FIFO contains at least one cell. It is logic 0 when the FIFO is empty (or nearly empty).
XTPOHCLK* 5 XTPOHFP* 6 XTPOHINS* 7 XTPOH* TCELL* TCA* RCELL* RCA* 8 9 10 11 12
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
LOF* OOF*
13 14
XRPOHFP* 15 XRPOHCLK*16 XRPOH* XROHFP* 17 18
XROHCLK* 19 XROH* 20
PLCP Loss of frame. LOF* is asserted to a logic 1 while the PLCP receiver is in a loss of frame state. PLCP Out of frame. OOF* is asserted to a logic 1 while the PLCP receiver is in a loss of frame state. Buffered receive PLCP overhead frame position. XRPOHFP* is updated on the falling edge of XRPOHCLK*. Buffered receive PLCP overhead clock. XRPOHFP* and XRPOH* are updated on the falling edge of XRPOHCLK*. Buffered receive PLCP overhead data. Contains PLCP overhead bits that are extracted from the receive PLCP frame. Buffered receive overhead frame position. XROHFP* is updated on the falling edge of XROHCLK*. Buffered receive overhead clock. XROH*, and XROHFP*, are updated on the falling edge of XROHCLK* Buffered receive overhead data. Contains overhead bits that are extracted from DS3, E3 receive streams.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Headers J16, J17, J19 (page 6 of schematics) Headers J16, J17, J19 are 14 pin headers. These headers are used to put S/UNIPDH device 4 into either normal ATM bus mode or ATM Loopback mode. A 14 row by 2 column jumper block is used to short across headers J16 and J19 for normal ATM bus mode. A jumper block is used to short headers J17 and J16 for ATM Loopback mode. The following table describes signals on J16. J16 signals connect directly to inputs on S/UNI-PDH device 4 TDAT bus side. Si g n a l TFCLK4 RFCLK4 TDAT4(0) TDAT4(1) TDAT4(2) TDAT4(3) TDAT4(4) TDAT4(5) TDAT4(6) TDAT4(7) TSOC4 PIN # 1 2 3 4 5 6 7 8 9 10 11 Description ATM Transmit FIFO clock. Clock for transferring ATM parallel data into S/UNI-PDH devices 4. ATM Receive FIFO clock. Clock for transferring ATM parallel data out of S/UNI-PDH device 4. Parallel ATM transmit data bus bit 0. Parallel ATM transmit data bus bit 1. Parallel ATM transmit data bus bit 2. Parallel ATM transmit data bus bit 3. Parallel ATM transmit data bus bit 4. Parallel ATM transmit data bus bit 5. Parallel ATM transmit data bus bit 6. Parallel ATM transmit data bus bit 7. Transmit start of cell. Marks start of cell on TDAT4 bus. Transmit parity. Indicates parity on TDAT4 bus. Transmit write enable. Used to enable write TDAT bus data to S/UNI-PDH device 4 only. Receive Read output enable. Enables read data onto RDAT bus for S/UNI-PDH device 4 only.
TXPRTY4 12 TWREN4B4 13 RRDEN4B4 14
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
The following table describes signals on J17. J17 signals are connected to J16 inputs on S/UNI-PDH device 4 TDAT bus side in Loopback mode with shorting jumpers. Si g n a l NC NC RDAT(0) RDAT(1) RDAT(2) RDAT(3) RDAT(4) RDAT(5) RDAT(6) RDAT(7) RSOC RXPRTY BRCA4 BTCA4 PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description Not connected. This pin is left open for external TFCLK source to be connected in Loopback mode. Not connected. This pin is left open for external source of RFCLK to be connected in Loopback mode. Parallel ATM receive data bus bit 0. Connected to TDAT4(0) in Loopback mode. Parallel ATM receive data bus bit 1. Connected to TDAT4(1) in Loopback mode. Parallel ATM receive data bus bit 2. Connected to TDAT4(2) in Loopback mode. Parallel ATM receive data bus bit 3. Connected to TDAT4(3) in Loopback mode. Parallel ATM receive data bus bit 4. Connected to TDAT4(4) in Loopback mode. Parallel ATM receive data bus bit 5. Connected to TDAT4(5) in Loopback mode. Parallel ATM receive data bus bit 6. Connected to TDAT4(6) in Loopback mode. Parallel ATM receive data bus bit 7. Connected to TDAT4(7) in Loopback mode. Receive start of cell. Marks start of cell on RDAT bus. This signal is connected to TSOC4 in Loopback mode. Receive parity. Indicates parity on RDAT bus. This signal is connected to TXPRTY4 in Loopback mode. Inverted Receive Cell Available. Indicates when a cell is available for output on the RDAT bus. Connected to TWREN4B4 in Loopback mode. Inverted Transmit Cell Available. Indicates when transmit cell FIFO is empty. Connected to RRDEN4B4 in Loopback mode.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
The following table describes signals on J19. J19 signals are normally connected to J16 inputs on S/UNI-PDH device 4 TDAT bus side with shorting jumpers. Si g n a l TFCLK RFCLK TDAT(0) TDAT(1) TDAT(2) TDAT(3) TDAT(4) TDAT(5) TDAT(6) TDAT(7) TSOC TXPRTY TWREN4B RRDEN4B PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description ATM Transmit FIFO clock. Clock for transferring ATM parallel data into S/UNI-PDH device 4 from SCI-PHY connector. ATM Receive FIFO clock. Clock for transferring ATM parallel data out of S/UNI-PDH device 4 to SCI-PHY connector. Parallel ATM transmit data bus bit 0 from SCI-PHY connector. Parallel ATM transmit data bus bit 1 from SCI-PHY connector. Parallel ATM transmit data bus bit 2 from SCI-PHY connector. Parallel ATM transmit data bus bit 3 from SCI-PHY connector. Parallel ATM transmit data bus bit 4 from SCI-PHY connector. Parallel ATM transmit data bus bit 5 from SCI-PHY connector. Parallel ATM transmit data bus bit 6 from SCI-PHY connector. Parallel ATM transmit data bus bit 7 from SCI-PHY connector. Transmit start of cell. Marks start of cell on TDAT bus. Transmit parity. Indicates parity on TDAT bus from SCI-PHY connector. Transmit write enable. Used to enable a write of TDAT bus data to S/UNI-PDH device 4 from SCIPHY connector. Receive Read output enable. Enables a read of data onto RDAT bus on the SCI-PHY connector from S/UNI-PDH device 4.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Headers J21 (page 7 of schematics) Headers J21 is a 17 pin header. This header is a used to test and monitor signals connected to the PM4341 T1XC T1 framer transceiver. The following table describes signals on J21. Si g n a l GND T1BRFPI T1BRCLK PIN # 1 2 3 Description Ground Backplane frame pulse input. This signal is used to frame align the received data to the system backplane. It is pulled up with 10 kohms. Backplane Receive clock. This input can be fed with a 1.544 MHz clock. It is pulled up with 10 kohms. Receive data link clock. This output is the clock for the HDLC receiver T1RDLSIG signal. Receive data link signal. This output is the HDLC receiver data signal. Receive Digital Negative Line Pulse. This input can receive the negative phase NRZ or RZ line receive data stream. It is pulled up with 10 kohms. Receive Digital Positive Line Pulse. This input can receive the positive phase NRZ or RZ line receive data stream. It is pulled up with 10 kohms. Backplane Receive Signalling. The T1BRSIG output contains extracted signalling bits for each channel in the receive frame. Backplane Receive PCM. This output contains the recovered receive line data stream. Backplane Frame Pulse Output. This output indicates the frame alignment of the T1BRPCM data stream. Receive Line Clock Input. This input can be an externally recovered 1.544 MHz clock used to sample the T1RDP and T1RDN inputs. It is pulled up with 10 kohms. Transmit Data Link Signal. HDLC transmit data is input to this pin to be inserted in the line transmit stream. It is pulled up with 10 kohms. Transmit Data Link Clock. This input provides clocking for the T1TDLSIG signal. Transmit Digital Negative Line Pulse. This output represents the negative phase line transmit data stream with RZ or NRZ CMOS levels. Transmit Digital Positive Line Pulse. This output represents the positive phase line transmit data stream with RZ or NRZ CMOS levels.
T1RDLCLK 4 T1RDLSIG T1RDN T1RDP T1BRSIG T1BRPCM T1BRFPO T1RCLKI 5 6 7 8 9 10 11
T1TDLSIG
12
T1TDLCLK 13 T1TDN T1TDP 14 15
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
T1TCLKO T1TCLKI
16 17
Transmit Clock Output. The T1TDP, and T1TDN outputs can be clocked on the rising or falling edge of T1TCLKO. Transmit Clock Input.This input can be used to generate the TCLKO signal. It is pulled up with 10 kohms.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
Headers J15 (page 8 of schematics) Headers J15 is a 17 pin header. This header is a used to test and monitor signals connected to the PM6341 E1XC E1 framer transceiver. The following table describes signals on J15. Si g n a l GND E1BRFPI E1BRCLK RFP E1RDLCLK E1RDLSIG PIN # 1 2 3 4 5 6 Description Ground Backplane Frame Pulse Input. This signal is used to frame align the received data to the system backplane. It is pulled up with 10 kohms. Backplane Receive Clock. This input can be fed with a 2.048 MHz clock. It is pulled up with 10 kohms. Receive Frame Pulse. This output indicates frame alignment of the RDPCM data stream. Receive Data Link Clock. This is the output clock for the HDLC receiver E1RDLSIG signal. Receive Data Link Signal. This is the HDLC receiver data signal output. Recovered Decoded PCM. This output is the recovered receive PCM data stream. Receive Digital Negative Line Pulse. This input can receive the negative phase NRZ or RZ line receive data stream. It is pulled up with 10 kohms. Receive Digital Positive Line Pulse. This input can receive the positive phase NRZ or RZ line receive data stream. It is pulled up with 10 kohms. Backplane Receive Signalling. The E1BRSIG output contains extracted signalling bits for each channel in the receive frame. Receive Line Clock Input. This input could be an externally recovered 2.048 MHz clock used to sample the E1RDP and E1RDN inputs. It is pulled up with 10 kohms. Transmit Data Link Signal. HDLC transmit data is input to this pin to be inserted in the line transmit stream. It is pulled up with 10 kohms. Transmit Data Link Clock. This input provides clocking for the E1TDLSIG signal. Transmit Digital Negative Line Pulse. This output represents the negative phase line transmit data stream with RZ or NRZ CMOS levels.
RDPCM_RPCM 7 E1RDN E1RDP E1BRSIG E1RCLKI 8 9 10 11
E1TDLSIG E1TDLCLK E1TDN
12 13 14
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PMC-Sierra, Inc.
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PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
E1TDP E1TCLKO E1TCLKI
15 16 17
Transmit Digital Positive Line Pulse. This output represents the positive phase line transmit data stream with RZ or NRZ CMOS levels. Transmit Clock Output. The E1TDP, and E1TDN outputs can be clocked on the rising or falling edge of E1TCLKO. Transmit Clock Input.This input can be used to generate the TCLKO signal. It is pulled up with 10 kohms.
Power Connector A supply of +5V and ground is normally provided by the SCI-PHY EVBD via the 96 pin DIN connectors when the SCI-PHY EVBD is attached to the S/UNI-PDH EVBD. When the S/UNI-PDH EVBD is used in Loopback mode, a 2 position barrier strip power connector, J25 (on schematic page 10), is provided to supply +5V and ground to the board. The +5V connection is fused with a 3 Amp quick blow fuse (F1). J25 connections are listed in the next table. Si g n a l GND +5V PIN # 1 2 Description Ground Power
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
OPERATION The S/UNI-PDH EVBD has been designed to work with the SCI-PHY evaluation mother board, or in a Loopback mode with reduced functionality. Operation with SCI-PHY Motherboard During operation with the SCI-PHY mother board, TDAT[7:0], RDAT[7:0], the control lines, and clocks come from the SCI-PHY 96 pin DIN connector. Microprocessor control and data bus signals are provided from the SCI-PHY motherboard via the Microprocessor Interface 96 pin DIN connector. Each S/UNI-PDH device on the S/UNI-PDH EVBD has an independent line interface but all S/UNI-PDH devices are common to the ATM parallel data buses. Since all four S/UNI-PDH devices are common to the ATM parallel data buses, access to a particular S/UNI-PDH device is controlled by read and write enable signals emanating from the SCI-PHY motherboard. This is done under control by the microprocessor on the SCI-PHY motherboard. In order that the S/UNI-PDH EVBD operates properly in its normal operating mode, headers J16 and J19 must have their adjacent pins jumpered together with a 2 row by 14 column shorting jumper block. Operation in Loopback Mode The S/UNI-PDH EVBD can be operated in a Loopback mode with reduced functionality. Only S/UNI-PDH device 4, which is configured for operation at the E3 line rate, can be operated in Loopback mode. The rest of the S/UNI-PDH devices will not be able to function during Loopback mode. In Loopback mode the receive parallel RDAT ATM data bus is looped back to the transmit parallel TDAT4 bus input on S/UNI-PDH device 4. RSOC is looped back to TSOC4. RXPRTY is looped back to TXPRTY4. RCA4 is inverted and looped back to TWREN4B4. TCA4 is inverted and looped back to RRDEN4B4. To put the S/UNI-PDH board into Loopback mode one must jumper together adjacent pins on headers J16 and J17 (page 6 on schematics) with a 2 row by 14 column shorting jumper block. Off board clock sources for TFCLK4 and RFCLK4 must be provided on pins 1 and 2 of header J17 for Loopback mode to work on S/UNI-PDH device 4. If the SCI-PHY motherboard is not mated with the S/UNI-PDH EVBD, Pins 1 and 2, 3 and 4, 5 and 6 on header J4 (page 2 on schematics) must be shorted with 2 position shorting jumpers to prevent floating CMOS inputs on the rest of the S/UNI-PDH devices on the board.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
ELECTRICAL SPECIFICATIONS SCI-PHY ATM and Microprocessor Interface Both the SCI-PHY ATM and Microprocessor interfaces use 96 pin DIN plug connectors. These interfaces provide support for the ATM drop side as well as the microprocessor interface. See SATURN COMPLIANT INTERFACE FOR ATM PHYSICAL LAYER INTERCONNECT EVALUATION MOTHERBOARD ENGINEERING DOCUMENT for further details on this interface. CMOS level voltages are used by all signals on these connectors. Line Interface Signals The transmit and receive line interface signals are transformer isolated. The termination impedance and connector type for each signal is given in the following table. Signal+ TXDS1P RXDS1P TXE1P RXE1P TXDS3P RXDS3N TXE3P RXE3P SignalTXDS1N RXDS1N TXE1N RXE1N TXDS3N RXDS3N TXE3N RXE3N Impedance Connector 100 ohm Bantam 100 ohm Bantam 120 ohm Bantam 120 ohm Bantam 75 ohm BNC Coax 75 ohm BNC Coax 75 ohm BNC Coax 75 ohm BNC Coax Description DS1 balanced TX outputs. DS1 balanced RX inputs. E1 balanced TX outputs. E1 balanced RX inputs. DS3 unbalanced TX outputs. DS3 unbalanced RX inputs. E3 unbalanced TX outputs. E3 unbalanced RX inputs.
S/UNI-PDH EVBD Power The S/UNI-PDH EVBD requires a single supply of +5 Volts D.C. at x.xx Amps. This can be provided through several pins on the Microprocessor interface 96 pin DIN connector, or, by J25, a two position barrier strip connector. The +5V supply via pin 1 on J25 is fused for 3 Amps, quick blow. The S/UNI-PDH EVBD draws its power from the SCI-PHY EVMB when attached to it. Fusing in this case is provided on the SCI-PHY board.
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PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
STOCK LIST
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 Part PDH PM4341 PM6341 78P7200 PE64952 PE65663 OC S OC S OC S OC S OC S OC S 74HCT541 Description PM7345 S/UNI-PDH PM4341 T1XC PM6341 E1XC 78P7200 PLCC 28 pin Transformers PE64952 Transformer PE65663 Oscillator 49.152 MHz Osc TTL Oscillator 44.736 MHz Osc TTL Oscillator 37.056 MHz Osc TTL Oscillator 34.368 MHz Osc TTL Oscillator 2.048 MHz Osc TTL Oscillator 1.544 MHz TTL 74HCT541 Reference U1,U7,U9,U12 U20 U21 U18,U19 T1,T2 T3 Y2 Y5 Y1 Y6 Y4 Y3 U2,U3,U4,U5,U6, U8,U10,U11 14 HDR5X2 Header - Dual row breakable header strip, tin plate, male, 0.1" spacing, 50 contacts total, INDUS 923866 - CUT INTO LENGTHS OF 5 CONTACT PAIRS EACH. 15 HDR8X2 Header - Dual row breakable header strip, tin plate, male, 0.1" spacing, 50 contacts total, INDUS 923866 - CUT INTO LENGTHS OF 8 CONTACT PAIRS EACH 16 HDR14 Header - Single row breakable header strip, tin plate, male, 0.1" spacing, 36 contacts total INDUS 929647-01-36 - CUT INTO LENGTHS OF 14 contacts each J16,J17,J19 3 J9,J12,J13,J20 4 J4 1 Qty 4 1 1 2 2 1 1 1 1 1 1 1 8
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PMC-Sierra, Inc.
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PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
17
HDR17
Header - Single row breakable header strip, tin plate, male, 0.1" spacing, 36 contacts total, INDUS 929647-01-36 - CUT INTO LENGTHS OF 17 CONTACTS EACH
J15,J21
2
18
HDR20
Header - Single row breakable header strip, tin plate, male, 0.1" spacing, 36 contacts total, INDUS 929647-01-36 - CUT INTO LENGTHS OF 20 CONTACTS EACH.
J7,J10,J11,J14
4
19
RSIP9
resistor 10 pin 9 resistor 4.7K ohms 5% (4.7kx9+1)
RN1,RN2,RN3
3
20 21 22 23 24 25 26 27 28 29 30
RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR
resistor 75 ohm 1% resistor 422 ohm 1% resistor 5.23Kohm resistor 6.81Kohm 1% 1%
R28,R53,R54 R51 R40 R37 R50 R52 R35,R45 R41,R48 R21,R27 R2,R5 R6,R22,R23,R31, R38,R42,R44, R46,R55,R56
3 1 1 1 1 1 2 2 2 2 10
resistor 301 ohm 1% resistor 604 ohm 1% resistor 6.04 Kohm 1% resistor 100 Kohm 1% resistor 316 Kohm 1% resistor 1.1 Kohm 1% resistor 1 ohm 1%
31 32 33 34 35 36 37 38 39
RESISTOR RESISTOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR
resistor 9.09 K ohm 1% resistor 412 ohm 1% cap 22 pF ceramic Cog cap 10 pF ceramic "100" NPO cap 2.7 pF ceramic 50V cap 0.22 microFarad elec. tant. cap 0.022 microFarad ceramic "223" X7R cap 10 microFarad elec. 10V cap 0.047 microFarad ceramic "473" X7R
R16 R20 C32 C23,C97 C20,C98 C18,C22 C19,C30 C46,C99 C15,C17
1 1 1 2 2 2 2 2 2
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PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
40
CAPACITOR
cap 0.1 microFarad ceramic "104" X7R
C1,C3-C8,C12, C13,C16,C25C29,C31,C33C45,C47-C96
79
41 42
CAPACITOR
cap 0.01 microFarad ceramic PCB 4 layer, one +5V plane, one GND plane,two signal planes,
C24
1 1
43 44 45 46
DIN96 BANTAM BNC INDUCTOR
R/A PCB connector 3x32 pins Bantam PCB Jack + cover (PC834) BNC PCB R/A mount 75 ohm Inductor 4.7 microHenry
J1,J2 J18,J22,J23,J24 J3,J5,J6,J8 L1,L2,L3,L4,L6, L7,L8,L9
2 4 4 8
47 48 49 50
INDUCTOR LED LED RESISTOR
Inductor 0.47 microHenry LED Green LED Red resistor 330 ohm 1/4W 5%
L5 D5 D1,D2,D3,D4 R9,R15,R24,R32, R57
1 1 4 5
51
22V10PLCC
PAL 22V10 -25
U13,U15,U16, U17
4
52 53 54
74F04BLK PE65664 RESISTOR
74F04 SOIC Transformers PE65664 resistor 120 ohm 5%
U14 T4,T5,T6 R26,R30,R34, R49
1 3 4
55 56 57 58
RESISTOR RESISTOR RESISTOR RESISTOR
resistor 22.1 ohm 1% resistor 47 ohm 5% resistor 4.53 kohm 1% resistor 4.7 kohm 5%
R47 R39 R7 R3,R4,R8,R10, R11,R12,R13, R14,R17,R18, R19,R25,R29, R33,R36,R43
1 1 1 16
59
RESISTOR
resistor 523 ohm 1%
R1
1
______________________________________________________________________________________________ 28
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
60 61 62
CAPACITOR CAPACITOR CAPACITOR
cap 0.001 F ceramic
"101" NPO
C2,C11 C9,C10 C14,C21
2 2 2
cap 0.47 F elec. tant. surface mount cap 0.68 F ceramic monolithic X7R thru hole
63
RSIP9
resistor 10 pin 9 resistor10K ohms 5% (4.7kx9+1)
RN4,RN5
2
64
POWER2
PW 2 Power Connector - Barrier Strip 2 pos. PC mount
J25
1
65
FUSE
Fuse - 3A - PICO II Very Fast Acting Pico Fuse
F1
1
66 67 68 69 70 CAPACITOR
Socket-PLCC-28 pin surface mount Adhesive Mount Rubber Feet Spacer 4-40 nylon hex 1/4' Screw 4-40 1/4 nylon Cap 3.3pF ceramic chip H1 H2 possible substitute for C20, C98
6 4
______________________________________________________________________________________________ 29
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
REFERENCES * PMC-940212, ATM_SCI_PHY, "SATURN COMPLIANT INTERFACE FOR ATM DEVICES", February 1994, Issue 1 * PMC-940324, SATURN COMPLIANT INTERFACE FOR ATM PHYSICAL LAYER INTERCONNECT EVALUATION MOTHERBOARD (SCI-PHY EVMB) ENGINEERING DOCUMENT. * PMC-931011, "SATURN USER-NETWORK INTERFACE FOR ATM PLESIOCHRONOUS DIGITAL HIERARCHY", April 1994 * PM4341A T1XC DATABOOK, "T1 FRAMER TRANSCEIVER". * PM6341A E1XC DATABOOK, "E1 FRAMER TRANSCEIVER". * 78P7200 LIU DATASHEET, "COMMUNICATION PRODUCTS DATABOOK", SILICON SYSTEMS, 1994.
______________________________________________________________________________________________ 30
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
APPENDIX 1: COMPONENT PLACEMENT DIAGRAM
______________________________________________________________________________________________ 31
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
APPENDIX 2: SUGGESTED REVISIONS 1) The placement of J16 and J17 should be swapped.
______________________________________________________________________________________________ 32
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
APPENDIX 3: SCHEMATICS
______________________________________________________________________________________________ 33
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
APPENDIX 4: EXAMPLE FORTH WORDS TBD;
______________________________________________________________________________________________ 34
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
APPENDIX 5: EXAMPLE BOARD LAYOUT
______________________________________________________________________________________________ 35
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
NOTES
______________________________________________________________________________________________ 36
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
NOTES
______________________________________________________________________________________________ 37
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
NOTES
______________________________________________________________________________________________ 38
PMC-Sierra, Inc.
STANDARD PRODUCT
PM7545 S/UNI-PDH-EVBD
PRELIMINARY INFORMATION, Issue 2, January 11, 1995 S/UNI-PDH REFERENCE DESIGN _______________________________________________________________________________________
NOTES
______________________________________________________________________________________________ Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of third-party rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1995 PMC-Sierra, Inc. 941141P2 ref 940602P3 Printed in Canada Issue date: January 1995.
______________________________________________________________________________________________ PMC-Sierra, Inc. 8501 Commerce Court Burnaby, BC Canada V5A 4N3 604 668 7300

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