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Final Electrical Specifications
LTC1661 Micropower Dual 10-Bit DAC in MSOP
January 1999
FEATURES
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DESCRIPTION
The LTC(R)1661 integrates two accurate, addressable, 10-bit digital-to-analog converters (DACs) in a single tiny MS8 package. Each buffered DAC consumes just 60A total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads up to 1000pF. Sleep mode further reduces total supply current to a negligible 1A. Linear Technology's proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. The double-buffered input logic provides simultaneous update capability and can be used to write to either DAC without interrupting Sleep mode. Ultralow supply current, power-saving Sleep mode and extremely compact size make the LTC1661 ideal for battery-powered applications, while its straightforward usability, high performance and wide supply range make it an excellent choice as a general purpose converter. For additional outputs and even greater board density, please refer to the LTC1660 micropower octal 10-bit DAC.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Tiny: Two 10-Bit DACs in an 8-Lead MSOP-- Half the Board Space of an SO-8 Ultralow Power: 60A per DAC Plus 1A Sleep Mode for Extended Battery Life Wide 2.7V to 5.5V Supply Range Double Buffered for Independent or Simultaneous DAC Updates Rail-to-Rail Voltage Outputs Drive 1000pF Reference Range Includes Supply for Ratiometric 0V-to-VCC Output 3-Wire Serial Interface with Schmitt Trigger Inputs Differential Nonlinearity: 0.75LSB Max
APPLICATIONS
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Mobile Communications Digitally Controlled Amplifiers and Attenuators Portable Battery-Powered Instruments Automatic Calibration for Manufacturing Remote Industrial Devices
BLOCK DIAGRA
VOUT A 8
GND 7
VCC 6
VOUT B 5
Differential Nonlinearity (DNL)
1.0
10-BIT DAC A 10-BIT DAC B
DNL ERROR (LSB)
0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6
CONTROL LOGIC
ADDRESS DECODER
SHIFT REGISTER
- 0.8 -1.0 0 256 512 CODE 768 1023
1661 TA02
1 CS/LD
2 CLK
3 DIN
4 REF
1661 BD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1661 ABSOLUTE
(Note 1)
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RATI GS
Operating Temperature Range LTC1661C.............................................. 0C to 70C LTC1661I........................................... - 40C to 85C Lead Temperature (Soldering, 10 sec)................ 300C
VCC to GND .............................................. - 0.5V to 7.5V Logic Inputs to GND ................................ - 0.5V to 7.5V VOUT A, VOUT B, REF to GND ............ - 0.2V to VCC + 0.2V Maximum Junction Temperature ......................... 125C Storage Temperature Range ................ - 65C to 150C
PACKAGE/ORDER I FOR ATIO
TOP VIEW CS/LD CLK DIN REF 1 2 3 4 8 7 6 5 VOUT A GND VCC VOUT B
ORDER PART NUMBER
CS/LD 1
LTC1661CMS8 LTC1661IMS8 MS8 PART MARKING LTDV LTDW
MS8 PACKAGE 8-LEAD PLASTIC MSOP
TJMAX = 125C, JA = 150C/W
Consult factory for Military grade parts.
VCC = 2.7V to 5.5V, VREF VCC, VOUT Unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL Accuracy Resolution Monotonicity DNL INL VOS FSE Differential Nonlinearity Integral Nonlinearity Offset Error VOS Temperature Coefficient Full-Scale Error Full-Scale Error Temperature Coefficient Reference Input Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current Positive Supply Voltage Supply Current Power Supply For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) Sleep Mode (Note 3)
q q q q q q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
VREF VCC - 0.1V (Note 2) VREF VCC - 0.1V (Note 2) VREF VCC - 0.1V (Note 2) Measured at Code 20 VCC = 5V, VREF = 4.096V
Not in Sleep Mode (Note 6) Sleep Mode
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TOP VIEW 8 7 6 5 VOUT A GND VCC VOUT B
ORDER PART NUMBER LTC1661CN8 LTC1661IN8
CLK 2 DIN 3 REF 4
N8 PACKAGE 8-LEAD PLASTIC DIP
TJMAX = 125C, JA = 100C/W
MIN 10 10
TYP
MAX
UNITS Bits Bits
q q q q
0.1 0.4 5 15 1 30 0 140 260 15 0.001 2.7 120 95 1
0.75 2 30 12
LSB LSB mV V/C LSB V/C
q
VCC
V k pF
q q q
1 5.5 195 154 3
A V A A A
LTC1661
VCC = 2.7V to 5.5V, VREF VCC, VOUT Unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER Short-Circuit Current Low Short-Circuit Current High AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital I/O VIH VIL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VIN = GND to VCC (Note 6)
q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS VOUT = 0V, VCC = VREF = 5V, Code = 1023 VOUT = VCC = VREF = 5V, Code = 0 Rising (Notes 4, 5) Falling (Notes 4, 5) To 0.5LSB (Notes 4, 5)
q q
MIN 10 7
TYP 25 19 0.60 0.25 30
MAX 100 120
UNITS mA mA V/s V/s s V V
DC Performance
2.4 2.0 0.8 0.6 10 10
V V A pF
TI I G CHARACTERISTICS
SYMBOL t1 t2 t3 t4 t5 t6 t7 t9 t11 t1 t2 t3 t4 t5 t6 t7 t9 t11 PARAMETER DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK High to CS/LD High CS/LD Low to CLK High CLK Low to CS/LD Low CS/LD High to CLK Positive Edge DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK High to CS/LD High CS/LD Low to CLK High CLK Low to CS/LD Low CS/LD High to CLK Positive Edge (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CONDITIONS
q q q q q q q q q q q q q q q q q q
VCC = 4.5V to 5.5V 40 0 30 30 80 30 65 0 20 60 0 50 50 100 50 80 0 30 15 - 10 14 14 27 2 22 -5 0 20 - 10 15 15 30 3 23 -5 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VCC = 2.7V to 5.5V
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined from the first code that is greater than or equal to the maximum offset specification to code 1023 (full scale). See Applications Information.
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MIN
TYP
MAX
UNITS
Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10k in parallel with 100pF. Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e., codes k = 102 and k = 922. Note 6: Guaranteed by design and not subject to test.
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LTC1661 TI I G DIAGRA
CLK t9 DIN t5 CS/LD
1661 TD
PIN FUNCTIONS
CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, CLK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, CLK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible. CLK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 3): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of CLK. CMOS and TTL compatible. REF (Pin 4): Reference Voltage Input. 0V VREF VCC. VOUT A, VOUT B (Pins 8,5): DAC Analog Voltage Outputs. The output range is 0 to VREF
DEFINITIONS
Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB Where VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/1023)]/LSB Where VOUT is the output voltage of the DAC measured at the given input code.
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t1 t2 t3 t4 t6 t11 A3 t7 A2 A1 X1 X0
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1023 1024
VCC (Pin 6): Supply Voltage Input. 2.7V VCC 5.5V. GND (Pin 7): System Ground.
LTC1661
DEFINITIONS
Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/1024 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero.
OPERATIO
Transfer Function The transfer function for the LTC1661 is:
VOUT(IDEAL) = k VREF 1024
where k is the decimal equivalent of the binary DAC input code D9-D0 and VREF is the voltage at REF (Pin 6). Power-On Reset The LTC1661 positively clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Power Supply Sequencing The voltage at REF (Pin 4) must not ever exceed the voltage at VCC (Pin 6) by more than 0.2V. Particular care should be taken in the power supply turn-on and turn-off sequences to assure that this limit is observed. See Absolute Maximum Ratings. Serial Interface See Table 1. The 16-bit input word consists of the 4-bit DAC control code, the 10-bit input code and two don't care bits. Table 1. LTC1661 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 Control Input Code Don't Care
The data path for the 10-bit input code is buffered by two latch registers. The first of these, the Input Register, is used for loading new input codes. The second buffer, the DAC
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Register, is used for updating the DAC outputs. Each DAC has its own 10-bit Input Register and 10-bit DAC Register. By selecting the appropriate 4-bit DAC control code (see Table 2) it is possible to perform single operations, such as loading one DAC or changing Power-Down status (Sleep/Wake). In addition, some control codes perform two or more operations at the same time. For example, one such code loads DAC A, updates both outputs and Wakes the part. The DACs can be loaded separately or together, but the outputs are always updated together. Register Loading Sequence See Figure 1. With CS/LD held low, data on the DIN input is shifted into the 16-bit Shift Register on the positive edge of CLK. The 4-bit DAC control code, A3-A0, is loaded first, then the 10-bit input code, D9-D0, ordered MSB-to-LSB in each case. Two don't-care bits, X1 and X0, are loaded last. When the full 16-bit word has been shifted in, CS/LD is pulled high, causing the system to respond according to Table 2. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low. Sleep Mode DAC control code 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, most internal bias currents are disabled while all digital circuitry stays fully active; static power consumption is thus virtually eliminated. The analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state.
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LTC1661
OPERATIO
CONTROL A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 No Change Load DAC A
Table 2. DAC Control Functions
INPUT REGISTER STATUS No Change Load DAC A Load DAC B DAC REGISTER STATUS No Update No Update No Update Reserved Reserved Reserved Reserved Reserved Update Outputs Update Outputs Wake Wake Load Both DAC Regs with Existing Contents of Input Regs. Outputs Update. Part Wakes Up Load Input Reg A. Load DAC Regs with New Contents of Input Reg A and Existing Contents of Reg B. Outputs Update. Part Wakes Up Load Input Reg B. Load DAC Regs with Existing Contents of Input Reg A and New Contents of Reg B. Outputs Update. Part Wakes Up POWER-DOWN STATUS (SLEEP/WAKE) No Change No Change No Change COMMENTS No Operation. Power-Down Status Unchanged (Part Stays In Wake or Sleep Mode) Load Input Register A with Data. DAC Outputs Unchanged. Power-Down Status Unchanged Load Input Register B with Data. DAC Outputs Unchanged. Power-Down Status Unchanged
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0
1
0
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1 No Change No Change Load DACs A, B with Same 10-Bit Code
CLK
DIN
CS/LD
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Load DAC B Update Outputs Wake Reserved Reserved No Update No Update Update Outputs Wake Sleep Wake Part Wakes Up. Input and DAC Regs Unchanged. DAC Outputs Reflect Existing Contents of DAC Regs Part Goes to Sleep. Input and DAC Regs Unchanged. DAC Outputs Set to High Impedance State Load Both Input Regs. Load Both DAC Regs with New Contents of Input Regs. Outputs Update. Part Wakes Up
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 CONTROL INPUT CODE INPUT WORD W0 (CLK ENABLED) (LTC1661 RESPONDS)
1661 F01
DON'T CARE
Figure 1. Register Loading Sequence
LTC1661
OPERATIO
Sleep mode is initiated by performing a load sequence using control code 1110b (the DAC input code D9-D0 is ignored). The input codes stored in the input register for each channel may be changed during Sleep by using control codes 0001b and 0010b. Voltage Outputs Each of the rail-to-rail output amplifiers contained in the LTC1661 can typically source or sink up to 5mA (VCC = 5V). The outputs swing to within a few millivolts of either supply when unloaded and have an equivalent
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 2b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 2c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
VREF = VCC POSITIVE FSE
OUTPUT VOLTAGE
0
OUTPUT VOLTAGE
0V NEGATIVE OFFSET INPUT CODE (b)
1661 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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output resistance of 85 (typical) when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. For example, a 0.1F load can be successfully driven by inserting a 110 resistor. The phase margin of the resulting circuit is 45, and increases monotonically from this point if larger values of resistance, capacitance or both are substituted for the values given.
OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC 512 INPUT CODE (a) 1023
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LTC1661
PACKAGE DESCRIPTION
0.007 (0.18) 0.021 0.006 (0.53 0.015)
0 - 6 TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP 0.192 0.004 (4.88 0.10) 0.118 0.004** (3.00 0.102)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076)
(
+0.035 0.325 -0.015 +0.889 8.255 -0.381
)
0.100 0.010 (2.540 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
RELATED PARTS
PART NUMBER LTC1446/LTC1446L LTC1448 LTC1454/LTC1454L LTC1458/LTC1458L LTC1659 LTC1660 DESCRIPTION Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference Dual 12-Bit VOUT DAC in SO-8 Package Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V Octal 10-Bit VOUT DAC in 16-Pin Narrow SSOP COMMENTS LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
1661I LT/TP 0199 4K * PRINTED IN THE USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 0.004* (3.00 0.102) 0.040 0.006 (1.02 0.15) 0.034 0.004 (0.86 0.102) 8 76 5
0.006 0.004 (0.15 0.102)
MSOP (MS8) 1197
1
23
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N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400* (10.160) MAX 8 7 6 5
0.045 - 0.065 (1.143 - 1.651)
0.130 0.005 (3.302 0.127)
0.255 0.015* (6.477 0.381)
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N8 1197
(c) LINEAR TECHNOLOGY CORPORATION 1999

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