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EZ80L925048MOD
eZ80L92 Module
Product Specification
PS017005-0903 PRELIMINARY
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
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Document Disclaimer
(c) 2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v The eZ80L92 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 eZ80L92 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . . . . 13 EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 EMAC Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Mounting the Module onto the eZ80(R) Development Platform . . . . . . . . . . . . . . 19 ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 The eZ80L92 Module Product Specification . . . . . . . . . . . . . . . . . . . . . . . . 32
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Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Return Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Problem Description or Suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32 32 32 32
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. eZ80L92 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . 3 eZ80L92 Module Peripheral Bus Connector Pin Configuration . . . . . 4 eZ80L92 Module I/O Connector Pin Configuration . . . . . . . . . . . . . . 8 Dimension Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mounting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 eZ80L92 Module Schematic Diagram, #1 of 9--Top Level . . . . . . . 23 eZ80L92 Module Schematic Diagram, #2 of 9--100-Pin QFP eZ80L92 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 eZ80L92 Module Schematic Diagram, #3 of 9-- 36-Pin SRAM Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 eZ80L92 Module Schematic Diagram, #4 of 9--NOR Flash Device 26 eZ80L92 Module Schematic Diagram, #5 of 9--E-NET Module . . . 27 eZ80L92 Module Schematic Diagram, #6 of 9--IrDA Reset . . . . . . 28 eZ80L92 Module Schematic Diagram, #7 of 9--Headers . . . . . . . . 29 eZ80L92 Module Schematic Diagram, #8 of 9--Power Supply . . . 30 eZ80L92 Module Schematic Diagram, #9 of 9--Control Logic . . . . 31
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List of Tables
Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification. . . . . . . . 5 Table 2. eZ80L92 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . 8 Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Chip Frequency to Wait State Cycle Time Calculation. . . . . . . . . . . . . 14 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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EZ80L925048MOD eZ80L92 Module Product Specification
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The eZ80L92 Module
The eZ80L92 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity. This low-cost, expandable module is powered by ZiLOG's latest power-efficient, high-speed, optimized pipeline architecture eZ80L92 device (EZ80L925048MOD), a member of ZILOG's new eZ80(R) microprocessor family. The eZ80L92 microprocessor is a high-speed single-cycle instruction-fetch microprocessor, which can operate with a clock speed of 48 MHz. It can operate in Z80compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80L92 Module makes it suitable for a variety of applications, including industrial control, IrDA connectivity, communication, security, automation, point-of-sale terminals, and embedded networking applications.
Module Features * * * * * * * * * * * * * * *
eZ80L92 MPU default factory operating clock frequency at 48 MHz 10 Base-T Ethernet Media Access Controller+ PHI with Onboard RJ45 connector 512KB zero-wait-state onboard SRAM 1 MB onboard NOR Flash ROM (90-100 ns) GoldCap backup for Real-Time Clock I/O connector provides 24 general-purpose 5 V-tolerant I/O pinouts ZiLOG's industry-leading IrDA transceiver--ZiLOG ZHX1810 In-circuit Flash programming circuitry Onboard connector provides I2C 2-wire SDA/SCL interface Onboard connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data) Low-cost adaptation to carrier board via two 2x25pin (2.54mm) headers Horizontal or vertical mounting onto the eZ80(R) Development Platform Small footprint 64 x 64mm; height is 24 mm 3.3 V power supply Standard operating temperature range: 0C to +70C
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The eZ80L92 Module
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eZ80L92 Processor Features * * * * * * * * * * * * * * * * *
Single-cycle instruction fetch, high-performance, pipelined eZ80(R) CPU core Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control Two UARTs with independent baud rate generators SPI with independent clock rate generator I2C with independent clock rate generator Infrared Data Association (IrDA)-compliant infrared encoder/decoder New DMA-like eZ80(R) instructions for efficient block data transfer Glueless external memory interface with 4 chip selects, individual wait state generators, and an external WAIT input pin--supports Intel- and Motorola-style buses Fixed-priority vectored interrupts (both internal and external) and interrupt controller Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and separate VDD pin for battery backup Six 16-bit Counter/Timers with prescalers and direct input/output drive Watch-Dog Timer 24 bits of general-purpose I/O JTAG and ZDI debug interfaces 100-pin LQFP package 3.0-3.6 V supply voltage with 5V tolerant inputs Standard operating temperature range: 0C to +70C
Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low.
Block Diagram
Figure 1 illustrates a block diagram of the eZ80L92 Module.
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The eZ80L92 Module
EZ80L925048MOD eZ80L92 Module Product Specification
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Gold Cap
32 KHz XTAL
XTAL/Osc.
IrDA Transceiver
Real-Time Clock
eZ80 CPU
Power-On Reset
50-Pin Connector
PD
UART 24-Bit GPIO
Watch-Dog Timer
PC
UART
ZDI/JTAG
PB
SPI 6 Timer
I2C/SPI RJ45 Bus Controller 10 BaseT Controller w/ Magnetics
50-Pin Connector
1 MB Flash/ROM
128/512 KB SRAM
Figure 1. eZ80L92 Module Functional Block Diagram
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The eZ80L92 Module
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Pin Description
Peripheral Bus Connector
Figure 2 illustrates the pin layout of the 50-pin I/O Connector, located at position JP1 on the eZ80L92 Module. Table 1 describes the pins and their functions.
JP1 A6 A10 GND_EXT A8 A13 A15 A18 A19 A2 A11 A4 A5 DIS_ETH A21 A22 CS0 CS2 D1 D3 D5 D7 MREQ GND_EXT WR BUSACK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 A0 A3 V3.3_EXT A7 A9 A14 A1 6 GND_EXT A1 A12 A20 A17 DIS_FLASH V3.3_EXT A23 CS1 D0 D2 D4 GND_EXT D6 IOREQ RD INSTRD BUSREQ
HEADER 25X2 IDC50
Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration
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Pin Description
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Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* Pull Up/Down*
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Symbol A6 A0 A10 A3 GND VDD A8 A7 A13 A9 A15 A14 A18 A16 A19 GND A2 A1 A11 A12 A4 A20 A5 A17
Signal Direction Comments Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). 3.3 V Supply Input Pin. Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the eZ80(R) CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Pin Description
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Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued) Pull Up/Down* PU 10 K
Pin # 25
Symbol DIS_Eth
Signal Direction Comments Input A Low disables on-module EMAC from responding to CS3 on a per-cycle basis. CS3 can be used on the eZ80(R) Development Platform; CMOS Input 3.3 V (5 V tolerant) A Low disables on-module Flash memory from responding to CS0 on a per-cycle basis. CS0 can be used on the eZ80(R) Development Platform for external memory purposes; CMOS Input 3.3 V (5 V tolerant).
26
DIS_Flash
PU 10 K
Input
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A21 VDD A22 A23 CS0 CS1 CS2 D0 D1 D2 D3 D4 D5 GND D7 D6 MREQ PU 4k7 PU 4k7 PU 4k7 PU 4k7 PU 4k7 PU 4k7 PU 4k7
Bidirectional 3.3 V supply input pin. Bidirectional Bidirectional Output Output Output Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the eZ80(R) CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Pin Description
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Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued) Pull Up/Down*
Pin # 44 45 46 47 48 49 50
Symbol IORQ GND RD WR INSTRD BUSACK BUSREQ
Signal Direction Comments Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Output
PU 10K PU 10K
Output Input
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the eZ80(R) CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Pin Description
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I/O Connector
Figure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position JP2 of the eZ80L92 Module. Table 2 describes the pins and their functions.
JP2 PB7 PB5 PB3 PB1 GND_EXT PC6 PC4 PC2 PC0 PD6 PD5 PD3 PD1 TDO GND_EXT TCK RTC_VDD IICSCL IICSDA FLASHWE CS3 RESET V3.3_EXT HALT_SLP V3.3_EXT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 GND_EXT PD4 PD2 PD0 TDI TRIGOUT TMS EZ80CLK GND_EXT DIS_IRDA WAIT GND_EXT NMI
HEADER 25X2 IDC50
Figure 3. eZ80L92 Module I/O Connector Pin Configuration Table 2. eZ80L92 Module I/O Connector Pin Identification* Pull Up/Down Signal Direction Bidirectional Bidirectional
Pin # 1 2
Symbol PB7 PB6
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Pin Description
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Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional PD 4k7 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Pin # 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Symbol PB5 PB4 PB3 PB2 PB1 PB0 GND PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 GND PD5 PD4 PD3 PD2 PD1 PD0
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Pin Description
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Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Output PU 10 K Input
Pin # 27 28 29 30 31 32 33 34 35 36 37 38 39
Symbol TDO TDI/ZDA GND TRIGOUT TCK/ZCL TMS RTC_VDD EZ80CLK SCL GND SDA GND FlashWE
Comments JTAG data output pin. JTAG data input pin. VSS/Ground (0 V).
Output PU 10 K PU 10 K Input Input
Active High trigger event indicator. JTAG clock. High on reset enables ZDI mode; Low on reset enables OCI debug. JTAG Test Mode Select. RTC supply from GoldCap (or external battery).
Output PU 4k7 Bidirectional
48 MHz synchronous CPU clock. I2C Bus Clock. VSS/Ground (0 V). I2C Bus Data. VSS/Ground (0 V).
PU 4k7
Bidirectional
PU 10 K
Input
Low enables Write to onboard Flash memory. If this pin is unconnected, the Flash memory is writeprotected. VSS/Ground (0 V).
40 41 42 43 44
GND CS3 DIS_IRDA RESET WAIT PU 10 K PU 2k2 PU 2k2 Output Input Bidirectional Input
Used on module for CS8900 EMAC. Low disables onboard IRDA transceiver to use PD0/ PD1 UART pins externally. Reset output from Module or push-button reset. Driving the WAIT pin Low forces the eZ80(R) CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write operation. 3.3 V supply input pin.
45
VDD
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Pin Description
EZ80L925048MOD eZ80L92 Module Product Specification
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Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction
Pin # 46 47
Symbol GND HALT_SLP
Comments VSS/Ground (0 V).
Output, Active A Low on this pin indicates that the eZ80(R) CPU Low enters either HALT or SLEEP mode because of execution of either a HALT or SLP instruction. PU 10 K Schmitt Trigger Input, Active Low The NMI input is a higher priority input than the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being connected to the NMI input of the eZ80(R) CPU. 3.3 V supply input pin. NC Reserved--No Connection.
48
NMI
49 50
VDD Reserved
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Pin Description
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Onboard Component Description
Logic-Level I/Os
The I/O connector features 24 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/ O, UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80L92 dual modes, please refer to the eZ80L92 Product Specification (PS0130).
Onboard Battery Backup
An onboard 0.1 F capacitor (GoldCap) is used to bridge power outages of 2-4 hours if the power supply to the module is disconnected. The capacitor is charged to 3.1 V during normal operation and is discharged through the on-chip Real Time Clock. The VRTC pin is available on the I/O connector of the module to connect external components to a power supply or to a larger GoldCap. Caution: Do not connect a Lithium Battery to the GoldCap capacitor, because onboard charging circuitry for the capacitor can destroy the lithium battery.
Ethernet Media Access Controller
The eZ80L92 Module contains a CS8900A EMAC (MAC, PHI, and RAM) which is attached to the data/address bus of the processor. This chip is connected to the processor's CS3 Chip Select, A0-A3, D0-D7, RD, WR, and PD4 pins for interrupt purposes. Connection of pins PD6 and PD7 for LANACT (wake-up from sleep) and SLEEP is optional and resistor-selectable onboard (see below).
Ethernet LEDs
There are two green LEDs, a Link LED and a LAN LED, that are located adjacent to each other on the eZ80L92 Module. A flashing LAN LED (top) indicates received link pulses from the 10 Base-T Ethernet. This LAN LED should be ON if RX+ is connected to TX+ and RX- is connected to TX-. A steady Link LED (bottom) indicates Traffic (RX or TX) on the LAN.
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Onboard Component Description
EZ80L925048MOD eZ80L92 Module Product Specification
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An RJ45 loopback connector can be used to verify the correct operation of the Receiver and the Transmitter. The green LED should be on if RX+ is connected with TX+ and RX- is connected with TX-.
Ethernet Connectors
The eZ80L92 Module is equipped with an RJ45 connector that features integrated magnetics (transformer, common mode chokes). The remaining pins on the onboard RJ45 connector are not connected. Node assignments for the RJ45 Ethernet connector are shown in Table 3.
Table 3. Ethernet Connector Pin Assignments Pin 1 2 3 6 Function TX+ TX- RX+ RX-
Node assignment, in contrast to hub assignment, means that a straight-through cable (equivalent pin numbers on both sides of the cable are connected to each other) is used to attach the board to an Ethernet hub or switch. To connect the eZ80L92 Module directly to another node (e.g., a personal computer), a crossover cable must be used. The EMAC can be additionally protected by placing a U9 ESD protection array on the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1 (ST Microelectronics) devices.
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt
GPIO input bit PD4 serves as an active High interrupt input for the EMAC's INTRQ0 output. GPIO output bit PD7 can be used to enter the EMAC into SLEEP mode. When pulling SLEEP (PD7) Low after enabling HWStandbyE and HWSleepE modes, the chip draws lower current, because only the receiver is operating. A zero-Ohm resistor at position R14 on the eZ80L92 Module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector. If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is connected to GPIO input PD6 and can be used in interrupt edge-detection mode to wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R15 on
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14
the module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector.
EMAC Ports
Chip Select CS3 is used for selecting the EMAC via I/O decoding. The I/O base address is user-selectable. The EMAC is connected as an 8- or 16-bit device with 8-word-wide I/O registers:
EMAC Wait States
The CS8900A EMAC should be operated in Intel bus mode so that the setup and hold times for the I/O access are met. For 48 MHz operation, first set CS3_BMC (I/ O address 0xF3h) to 84h (Intel bus mode with four system clock cycles per bus cycle) and then CS3_CTL (I/O Address 0xB3) to 18h (0 wait states for I/O). For a 20.8 ns CPU Clock cycle time, the Read and Write access time is:
2 x 4 x 20.8 ns-16 ns (for capacitive and chip delays) = 150 ns
Memory
The eZ80L92 Module offers SRAM and Flash memories and the wait states that support memory operations, as described in this section.
Wait States
To ensure that valid data is read from or written to slower memories, a number of wait states must be inserted into the memory or I/O access operations by the processor. The number of wait states that are required should be added by programming the chip select control registers. To calculate the minimum number of wait states required, refer to Table 4.
Table 4. Chip Frequency to Wait State Cycle Time Calculation MHz 12 20 24 36 40 48 Cycle Time 83.3 ns 50.0 ns 41.7 ns 27.8 ns 25.0 ns 20.8 ns
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Static RAM
The eZ80L92 Module features 512 KB of fast SRAM. Access speed is typically 12 ns or faster, allowing zero-wait-state operation at 48 MHz. With the CPU at 48 MHz, onboard SRAM can be accessed with zero wait states in eZ80 mode. CS1_CTL (chip select CS1) can be set to 08h (no wait states).
Flash Memory
The Flash Boot Loader, application code, and user configuration data are held permanently in NOR Flash memory. A typical application requires eight times more ROM for code than RAM. As an example, for 128 KB onboard SRAM, 1 MB of ROM is required. The eZ80L92 Module allows NOR Flash memories between 4 megabits (512 KB) and 32 megabits (4 MB) to be used. The chips are housed in wide TSOP40 cases. Flash ROM access times are 55-150 ns; typically 90 ns. NOR Flash should be operated in Intel bus mode to satisfy setup and hold times and to prevent bus contention with a Write cycle that could possibly follow. For proper CPU operation at 48 MHz, first set the bus mode control register CS0_BMC (I/O address 0xF0h) to 82h, then set the Chip Select Control register CS0_CTL (I/O address 0xAAh) to 08h. These settings select Intel Bus Mode with two system clocks per bus cycle and zero wait states.
IrDA Transceiver
An onboard IrDA transceiver (ZiLOG ZHX1810) is connected to PD0 (TX), PD1 (RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type 870 nm Class 1. The receiver supply current is 90-150 A and the transmitter supply current is 260 mA when the LED is active.The IrDA transceiver is accessible via the IrDA controller attached to UART0 on the eZ80L92 device. The UART0 console and the IrDA transceiver cannot be used simultaneously. To use the UART0 for console or to save power, the transceiver can be disabled by the software or by an off-board signal when using the proper jumper selection. The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings. To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.
Reset Generator
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below
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16
2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80L92 Module with a low-impedance output (e.g. a 100-Ohm pushbutton).
Serial Interface Ports
The processor contains two 16550-style UARTs with programmable baud rate generators. UART0 is typically used for console I/O and initial boot code upload or to connect remote peripherals that can be controlled and monitored via Ethernet. UART0 is connected to GPIO PD[0:3] on the I/O connector. There are no RS232level shifters on the eZ80L92 Module. Note: Do not connect an RS-232 interface without level shifters. UART1 can be used for modem attachment or as a communications port to a host computer, where the embedded Ethernet module emulates an AT-style modem for internet access. UART1 does not offer onboard RS232-level shifters.
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Physical Dimensions
The size of the eZ80L92 Module PCB is 64 x 64mm. With an RJ45 Ethernet connector, the overall height is 25 mm, as shown in Figure 4.
63.5 mm 16 mm 8.3 mm max. 1 2.54 mm 16.3 mm 13.7 mm Link LAN 8.5 mm LEDs 1
RJ45
9 mm 3.5 mm
Bus Connector
Top View
I/O Connector
64 mm
9 mm 2.7 mm 6.2 mm
IrDA
7 mm
55.88 mm
Figure 4. Dimension Drawing
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EZ80L925048MOD eZ80L92 Module Product Specification
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Figure 5 illustrates a top view of the eZ80L92 Module.
Figure 5. Top Layer
Figure 6 illustrates a bottom view of the eZ80L92 Module.
Figure 6. Bottom Layer
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EZ80L925048MOD eZ80L92 Module Product Specification
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Mounting the Module onto the eZ80(R) Development Platform
The eZ80L92 Module can be mounted in several positions. Depending on volume and area restrictions, it can be mounted horizontally or vertically with or without components between the connectors on the eZ80(R) Development Platform. See Figure 8 for examples.
Low Profile Mounting
63.5 mm 64 mm
Bus
1
RJ45 (rear)
E-NET Module
Ds LE
1
15.3 mm
H = 4.5 mm
1.7 mm
I/O
8.3 mm
Carrier Board
Stacked Mounting
64 mm
Bus
1
4.2 mm RJ45 (rear) E-NET Module H = 4.5 mm
I/O
1
8.5 mm
Modem or Power Supply 50.5 mm max
Carrier Board Figure 7. Mounting Examples
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EZ80L925048MOD eZ80L92 Module Product Specification
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ESD/EMI Protection
Caution: The eZ80L92 Module is a component that is intended to be part of a system design for end-user devices. Therefore, the user must exercise caution to use ESD protection on the I/O pins. The EMAC can be additionally protected by placing an ESD protection array on the eZ80L92 Module at position U9. Either use ESDA25B1 from ST Microelectronics or LCDA15C-6 from Semtech. A mounting hole on the board can be used for grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD currents from flowing through the digital circuitry. The RJ45 Ethernet Connector on the eZ80L92 Module contains a transformer and common mode chokes for EMI suppression. Caution: CMOS I/Os are ESD-sensitive and must be handled with care. Handling of the module should be performed in ESD-safe environments (for example with a wrist-wrap attached). When developing applications, the user must provide for proper ESD protection on external, useraccessible I/Os (e.g. suppressor arrays for the I/Os). The components are mounted on a multilayer PCB to provide a stable ground plane for onboard components. The module features several GND pins next to pins with higher switching frequency for short ground returns. If unused, the clock output can be separated from the module header by removing a series resistor on the module. Removing the series resistor further reduces electromagnetic emissions.
Absolute Maximum Ratings
Stresses greater than those listed in Table 5 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS).
Table 5. Absolute Maximum Ratings Parameter Standard operating temperature Storage temperature Operating Humidity (RH @ 50C) Operating Voltage (5%) Min 0 -45 25% -- Max +70 +85 90% 3.3 V Units C C
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Power Supply
The eZ80L92 Module requires a regulated external 3.3 VDC/0.5A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3 V from 5 V or use the following switcher circuit to generate 3.3 V from unregulated 10-28V power supply. Power connections follow these conventional descriptions:
Connection Power Ground Circuit VCC GND Device VDD VSS
Figure 8 offers two typical power supply examples.
Switcher 10-28V 3.3V
U1 LM2575S-ADJ 10-28V V IN C1 1000uF C2 100n 1 VIN G N D 3 FB OVOUT N / O F F 5 4 2 L1
To Module
VDD 3.3V
R1 5k6 1% C3 470uF/6.3V Low ESR 330uH/1A
D1 1A/30V R2 3k3 1%
GND
GND
LDO 5V 3.3V
4-6V VCC U1 LM3940 VI G N D VO
VDD 3.3V
C3 Low ESR 470uF/6.3V GND
C1 100n GND
Figure 8. Power Supply Examples
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EZ80L925048MOD eZ80L92 Module Product Specification
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Document Number Description
The Document Control Number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table:
PS 0170 05 0903 Product Specification Unique Document Number Revision Number Month and Year Published
Change Log
Rev Date 01 02 03 04 05 June 2002 July 2002 October 2002 January 2003 September 2003 Purpose Original issue Minor modifications Minor modifications Minor modifications Minor modifications By M. Staubermann, R. Pujar M. Staubermann, R. Beebe R. Beebe R. Beebe R. Beebe
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Document Number Description
EZ80L925048MOD eZ80L92 Module Product Specification
Schematic Diagrams
Figures 9 through 17 diagram the layout of the eZ80L92 Module.
03
RAM SRAM D[0..7] A[0..23] -RD -WR -CS1 D[0..7] A[0..23] -RD -WR -CS1
23
02
CPU eZ80 D[0..7] A[0..23] -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI -RESET -RESET
07
Peripherals Reset -RESET IRDA_TXD IRDA_RXD IRDA_SD IRDA_TXD IRDA_RXD IRDA_SD
08
-RESET -FLASHWE -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI A[0..23] CLK_OUT -WR -RD RTC_VDD IICSDA IICSCL A[0..23] D[0..7] -WR -RD D[0..7] A[0..23] IRDA_TXD IRDA_RXD IRDA_SD -DIS_FL -DIS_IRDA PB[0..7] PC[0..7] PD[0..7] -CS[0..3] JTAG[1..4] TDO -WR -RD
Connector Headers -RESET -FLASHWE -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI CLK_OUT RTC_VDD IICSDA IICSCL D[0..7] A[0..23] -WR -RD -DIS_FL -DIS_IRDA PB[0..7] PC[0..7] PD[0..7] -CS[0..3] JTAG[1..4] TDO -DIS_ETH
04
ROM NOR-Flash D[0..7] A[0..23] -RD -WR -CSFLASH -RESFLASH -FLASHWE D[0..7] A[0..23] -RD -WR -CSFLASH -RESFLASH -FLASHWE
-NMI CLK_OUT RTC_VDD IICSDA IICSCL
CLK_OUT RTC_VDD IICSDA IICSCL D[0..7]
06
Logic CTRL-Logic
-RESET -WAIT PB[0..7] PC[0..7] PD[0..7] -CS[0..3] JTAG[1..4] TDO PB[0..7] PC[0..7] PD[0..7] -CS[0..3] JTAG[1..4] TDO
-RESET -WAIT
IRDA_TXD IRDA_RXD IRDA_SD -DIS_FL PD[0..7] -DIS_IRDA -CS[0..3] -CSFLASH -RESFLASH IOCHRDY -ETHRD -ETHWR ETHIRQ -SLEE P -ACTIVE SD[0..7] SA[0..3]
-CSFLASH -RESFLASH
09
Power PowerSupply V3.3 GND V3.3 GND
ETHIRQ -SLEE P -ACTIVE
05
Ethernet CS8900A SD[0..7] SA[0..3] IOCHRDY -ETHRD -ETHWR ETHIRQ -SLEEP -ACTIVE -DIS_ETH SD[0..7] SA[0..3] IOCHRDY -ETHRD -ETHWR ETHIRQ -SLEEP -ACTIVE
V3.3 GND
V3.3_EXT GND_EXT
Figure 9. eZ80L92 Module Schematic Diagram, #1 of 9--Top Level
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EZ80L925048MOD eZ80L92 Module Product Specification
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XIN
eZ80=IIC-bus-master
IICSDA IICSCL CLK_OUT IICSDA IICSCL CLK_OUT IICSDA IICSCL CLK_OUT
PB[0..7]
PC[0..7] XOUT XOU T XIN PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Y2
48 MHz HC49SM
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
R27 L1 3.3 H PD[0..7] 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 TDO TDI TRIGOUT TCK TMS RTC_VDD RTC_XOUT RTC_XIN -HALT_SLP -BUSACK -BUSREQ -NMI -RESET (= JTAG0) = JTAG1 = JTAG2 = JTAG3 = JTAG4 C16 15pF
1M
C17 4.7pF
PB[0..7] PC[0..7] PD[0..7]
PC[0..7] PD[0..7] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A0 A1 A2 A3 A4 A5 VDD VSS A6 A7 A8 A9 A10 A11 A12 A13 A14 VDD VSS A15 A16 A17 A18 A19 A20
PHI SCL SDA VSS VDD PB7/MOSI PB6/MISO PB5/T5_OUT PB4/T4_OUT PB3/SCK PB2/SS PB1/T1_IN PB0/T0_IN VDD XOUT XIN VSS PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 PC2/RTS1 PC1/RxD1 PC0/TxD1
PB[0..7]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0/IR_SD PD1/RxD0/IR_RXD PD0/TxD0/IR_TXD VDD TDO TDI (ZDA) TRIGOUT TCK (ZCL) TMS VSS RTC_VDD RTC_XOUT RTC_XIN VSS VDD HALT_SLP BUSACK BUSREQ NMI RESET
C25 220pF V3.3 JTAG[1..4] R28 100
-RESET JTAG[1..4] TDO -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP
-RESET JTAG[1..4] TDO -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP
U8
eZ80L92
TQFP100
D1 TMM BAT 41 MINIMELF_AK RTC_VDD C18 100nF
GoldCap
C19 0,1F GOLDCAP_SD
R29 10k
-BUSREQ -BUSACK -NMI
-BUSREQ -BUSACK -NMI
A21 A22 A23 CS0 CS1 CS2 CS3 VDD VSS D0 D1 D2 D3 D4 D5 D6 D7 VDD VSS IOREQ MREQ RD WR INSTRD WAIT
R32 RTC_XOUT 220 Y3 32.768kHz XTAL3 C24 18pF C20 18pF VDD VSS GND V3.3
-IOREQ -MREQ -RD -WR -INSTRD -WAIT
A21 A22 A23 -CS0 -CS1 -CS2 -CS3
D0 D1 D2 D3 D4 D5 D6 D7
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RTC_XIN
A[0..23]
A[0..23]
A[0..23]
-CS[0..3]
-CS[0..3] V3.3 V3.3
-CS[0..3] V3.3 D[0..7] C21 1nF C22 1nF C23 1nF
D[0..7]
D[0..7]
RTC_VDD
RTC_VDD
PLACE CAPS CLOSE TO PINS 97,7,33,43
Figure 10. eZ80L92 Module Schematic Diagram, #2 of 9--100-Pin QFP eZ80L92 Device
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EZ80L925048MOD eZ80L92 Module Product Specification
25
D[0..7] A[0..23] -CS1 -RD -WR
D[0..7] A[0..23] -CS1 -RD -WR
A21/A22/A23 not used here
RN1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 1
A18 A0 A1 A2 A3 -CS1 D0 D1 D2 D3 -WR A12 A9 A6 A4 A17
U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 N.C. A18 A17 A16 A15 OE I/O7 I/O6 VSS VDD I/O5 I/O4 A14 A13 A12 A11 A10 N.C. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
A20 A16 A15 A14 A13 -RD D7 D6 D5 D4 A11 A8 A10 A7 A5 A19
4.7k
512kx8 SRAM SOJ36.400
C7 100nF 14 U2D 8
VDD VSS V3.3
9
14
11
10
13
14
U2E
74LVC04/SO U2F 12
GND
74LVC04/SO
74LVC04/SO
Figure 11. eZ80L92 Module Schematic Diagram, #3 of 9--36-Pin SRAM Device
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EZ80L925048MOD eZ80L92 Module Product Specification
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D[0..7]
U3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
VDD VDD
30 31
A[0..23]
Intel-Type
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE OE WE RP WP VPP 25 26 27 28 32 33 34 35 22 24 9 10 12 11 29 38 DFLASH0 DFLASH1 DFLASH2 DFLASH3 DFLASH4 DFLASH5 DFLASH6 DFLASH7 -CSFLASH -RD -WR -RESFLASH -WP VPP A21 A20 0R R2 74LVC04/SO
= = = = = = = =
D0 D1 D2 D3 D4 D5 D6 D7
VDD R1 10K -FLASHWE
2
14
U2A 1
Pin37=N.C. for 4MbitFlashes
VSS VSS
N.C. N.C.
A20/A21 used for 16/32Mbit-Flash
MT28F008B3VG TSOP40.20MM C8 100nF
D[0..7] A[0..23] -CSFLASH -RD -WR -RESFLASH
D[0..7]
V3.3
A[0..23] -CSFLASH -RD -WR -RESFLASH
A22/A23 not used here
23 39
VDD VSS GND
-FLASHWE
-FLASHWE
Note: Must be pulled 'low' externally for programming.
Figure 12. eZ80L92 Module Schematic Diagram, #4 of 9--NOR Flash Device
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EZ80L925048MOD eZ80L92 Module Product Specification
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V3.3
VDD VSS 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
R19 10k
90 degree, stacked dual-LED
SD10 SD11 DVSS DVDD SD12 SD13 SD14 SD15 CSOUT DMACK0 DMARQ0 DMACK1 DMARQ1 DMACK2 DMARQ2 DVSS DVDD DVSS CHIPSEL EEDATAIN EEDATAOUT (TDO) EESK EECS ELCS AVSS
green
-LANLED 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 -LANLED -LINKLED Y1 20.000 MHz HC49SM R23 RXDRXD+ TXDTXD+ 4k99/1% -LINKLED 3
LD1B 4 LD1A 1 2
R20 220 0603
R21 220 0603
R22 4k7 ETHIRQ
SA0 SA1 SA2 SA3 SA[0..3]
SA13 SA14 SA15 SA16 DVSS DVDD DVSS SA17 SA18 SA19 IOR IOW AEN (TCK) IOCHRDY SD0 SD1 SD2 SD3 DVDD DVSS SD4 SD5 SD6 SD7 RESET
-DIS_ETH
SD9 SD8 MEMW MEMR INTRQ2 INTRQ1 INTRQ0 IOCS16 MEMCS16 INTRQ3 SHBE SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 REFRESH SA12
U7 CS8900A-CQ3
TQFP100
LANLED LINKLED/HC0 XTAL2 XTAL1 AVSS AVDD AVSS RES RXDRXD+ AVDD AVSS TXDTXD+ AVSS AVDD DODO+ CICI+ DIDI+ BSTATUS/HC1 SLEEP TEST
yellow
ESD protection array
U9 RD+ 1 RD2 3 4 8 TD+ 7 TD6 5 LCDA15C-6 SO8.150 GND
-SLEEP
int. Pull-Up
TXDR24 TXD+ R25 RXD8R2 C12 560pF 8R2 RDTD-
GND
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
J1 TD+ CTD 1 2 3 4 CRD 5 6 8 C14 100nF C15 100nF 1 2 3 4 5 6 8 HFJ11-1041 HALOFASTJACK
device addresses: 00300h bis 0030Fh
-ETHRD -ETHWR IOCHRDY -ETHRD -ETHWR
-ETHRD -ETHWR SD[0..7] R34 10k 0603
SD0 SD1 SD2 SD3
SD4 SD5 SD6 SD7
C13 100nF
R26 100 RXD+ RD+
SD[0..7] SA[0..3] ETHIRQ -SLEEP -ACTIVE
SD[0..7] SA[0..3] ETHIRQ -SLEEP -ACTIVE
V3.3
through hole solder pad place near J1
1
JP4 HEADER 1 SIP1
VDD VSS GND
don't stuff
CASE
TX+ TXRX+ RX-
<-> <-> <-> <->
1 2 3 6
L2
ferrite tbd
don't stuff
= -LANLED
Figure 13. eZ80L92 Module Schematic Diagram, #5 of 9--E-NET Module
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EZ80L925048MOD eZ80L92 Module Product Specification
28
V3.3 C9 100nF 0603
U4
GND VDD
R3 2k2 0603 -RESET -RESET
3
RESET
2
open-drain
C10 10nF 0603
MAX6328UR29 SOT-23-L3
alternative: Maxim MAX6802UR29D3
1
IR-transceiver
V3.3 R5 68R C11
330nF IRDA_TXD IRDA_RXD IRDA_SD IRDA_TXD IRDA_RXD IRDA_SD IRDA_SD IRDA_RXD 4 3 6 R6 2R7, 0.25W 1206 (MMA 020 4) IRDA_TXD U5 5 1 2 VCC LEDA TXD
V3.3
SD RXD GND T
VDD VSS
ZHX1810 0
GND
Figure 14. eZ80L92 Module Schematic Diagram, #6 of 9--IrDA Reset
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29
A[0..23] D[0..7] -CS[0..3]
A[0..23] D[0..7] -CS[0..3] R7 4k7 R8 4k7 IICSDA IICSCL R9 33 EZ80CLK
connector 1
A6 A10 GND_EXT A8 A13 A15 A18 A19 A2 A11 A4 A5 DIS_ETH A21 A22 -CS0 -CS2 D1 D3 D5 D7 -MREQ GND_EXT -WR -BUSACK R36 10K JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 A0 A3 V3.3_EXT A7 A9 A14 A16 GND_EXT A1 A12 A20 A17 -DIS_FL V3.3_EXT A23 -CS1 D0 D2 D4 GND_EXT D6 -IOREQ -RD -INSTRD -BUSREQ
connector 2
JP2 PB7 PB5 PB3 PB1 GND_EXT PC6 PC4 PC2 PC0 PD6 PD5 PD3 PD1 TDO GND_EXT TCK RTC_VDD IICSCL IICSDA -FLASHWE -CS3 -RESET V3.3_EXT -HALT_SLP V3.3_EXT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 GND_EXT PD4 PD2 PD0 TDI TRIGOUT TMS EZ80CLK GND_EXT -DIS_IRDA -WAIT GND_EXT -NMI
IICSDA IICSCL CLK_OUT -DIS_FL -DIS_IRDA -FLASHWE RTC_VDD -DIS_ETH PB[0..7] PC[0..7] PD[0..7] -RESET -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI JTAG[1..4] TDO
IICSDA IICSCL CLK_OUT -DIS_FL -DIS_IRDA -FLASHWE RTC_VDD
place near eZ80 output (PHI)
PB[0..7] PC[0..7] PD[0..7] -RESET -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI JTAG[1..4] TDO V3.3 -WAIT -BUSREQ R10 2k2 0603 R33 2k2 0603
HEADER 25X2 IDC50
HEADER 25X2 IDC50
R11 10k JTAG1 (JTAG0 JTAG2 JTAG3 JTAG4 = =) = = = TDI TDO TRIGOUT TCK TMS
R12 10k
V3.3_EXT GND_EXT
V3.3_EXT GND_EXT
R13 4k7
GND
Figure 15. eZ80L92 Module Schematic Diagram, #7 of 9--Headers
PS017005-0903 PRELIMINARY Schematic Diagrams
EZ80L925048MOD eZ80L92 Module Product Specification
30
V3.3
common power plane
V3.3 V3.3 V3.3 C1 47uF TAJC GND GND C2 47uF TAJC C3 1nF C4 100nF C5 1nF C6 100nF
GND
GND
common ground plane
no power supply on board!
Input: VDD(=V3.3) = 3.3V 5% Power: Pmax = 1.6W Ptyp = 0.4W Current: Imax = 200mA (IrDA not in use) Imax = 460mA (IrDA in use) Ityp = 100mA
PCB1
E-NET Module Rev.B 98Cxxxx-xxx
Figure 16. eZ80L92 Module Schematic Diagram, #8 of 9--Power Supply
PS017005-0903
PRELIMINARY
Schematic Diagrams
EZ80L925048MOD eZ80L92 Module Product Specification
31
D[0..7] A[0..23]
D[0..7] A[0..23]
D[0..7]
=
SD[0..7] SA[0..3]
SD[0..7] SA[0..3] -ETHRD -ETHWR
SD[0..7] SA[0..3] -ETHRD -ETHWR
only A0,A1,A2,A3 are used here PD3 and PD5 not used here
A[0..23] A0 A1 A2 A3 = = = = SA0 SA1 SA2 SA3
PD[0..7]
PD[0..7]
VDD PD4 14 -RESET -WAIT -DIS_FL -DIS_IRDA -RD -WR -RESET -WAIT -DIS_FL -DIS_IRDA -RD -WR 1 -WR -CS[0..3] -CS[0..3] 3 2 74LCX32 TSSOP14 -CS3 = -CSETH -RD U6D 12 11 13 74LCX32 TSSOP14 14 -WAIT -ETHWR U6A PD7 -ETHRD PD6 R14 R15 0R 0R -SLEEP -ACTIVE = ETHIRQ ETHIRQ -SLEEP -ACTIVE
don't stuff
R35 0 IOCHRDY
-CS1 and-CS2 not used here
VDD
PD0 PD1
= =
IRDA_TXD IRDA_RXD IRDA_SD
IRDA_TXD IRDA_RXD IRDA_SD
R30 10k 0603 -DIS_FL 3
14
U2B 4 DIS_FL -CS0 74LVC04/SO U6B 4 6 5 74LCX32 TSSOP14 14 14
-CSFLASH -RESET = -RESFLASH -RESFLASH
R17 10k 0603 -DIS_IRDA 5
14
U2C 6 DIS_IRDA PD2 = IR_SD 74LVC04/SO U6C 9 8 10 74LCX32 TSSOP14 VDD VSS GND V3.3 -CSFLASH IRDA_SD -CSFLASH
Figure 17. eZ80L92 Module Schematic Diagram, #9 of 9--Control Logic
PS017005-0903
PRELIMINARY
Schematic Diagrams
EZ80L925048MOD eZ80L92 Module Product Specification
32
Customer Feedback Form
The eZ80L92 Module Product Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Customer Information
Name Company Address City/State/Zip Country Phone Fax Email
Product Information
Serial # or Board Fab #/Rev. # Software Version Document Number Host Computer Description/Type
Return Information ZiLOG System Test/Customer Support 532 Race Street San Jose, CA 95126 Phone: (408) 558-8500 Fax: (408) 558-8536 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.
_____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________
PS017005-0903
PRELIMINARY
Customer Feedback Form

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