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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308A
3.3V Zero-Delay Buffer
Product Features
* 10 MHz to 140 MHz operating range * Zero input-output propagation delay, adjustable by capacitive load on FBK input * Multiple configurations, see Available PI6C2308A Configurations table * Input to output delay, less than 150ps * Multiple low skew outputs - Output-output skew less than 200ps - Device-device skew less than 500ps - Two banks of four outputs, Hi-Z by two select inputs * Low Jitter, less than 200ps * 3.3V operation * Available in industrial &commercial temperatures * Packages: - Space-saving 16-pin, 150-mil SOIC (W) - 16-pin TSSOP (L)
Functional Description
Providing two banks of four outputs, the PI6C2308A is a 3.3V zerodelay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. Each bank of four outputs can be controlled by the select inputs as shown in the Select Input Decoding Table. The PI6C2308A provides 8 copies of a clock signal that has 150ps phase error compared to a reference clock. The skew between the output clock signals for PI6C2308A is less than 200ps. When there are no rising edges on the REF input, the PI6C2308A enters a power down state. In this mode, the PLL is off and all outputs are Hi-Z. This results in less than 12A of current draw. The Select Input Decoding table shows additional examples when the PLL shuts down. The PI6C2308A configuration table shows all available devices. The base part, PI6C2308A-1, provides output clocks in sync with a reference clock. With faster rise and fall times, the PI6C2308A-1H is the high-drive version of the PI6C2308A-1. Depending on which output drives the feedback pin, PI6C2308A-2 provides 2X and 1X clock signals on each output bank. The PI6C2308A-3 allows the user to obtain 4X and 2X frequencies on the outputs. The PI6C2308A-4 provides 2X clock signals on all outputs. PI6C2308A (-1, -2, -3, -4) allows bank B to be Hi-Z when all output clocks are not required.The PI6C2308A-6 allows bank B to switch from Reference clock to half of the frequency of Reference clock using the control inputs S1 and S2 if Bank A is connected to feedback FBK. In addition, using the control inputs S1 and S2, the PI6C2308A-6 allows bank A to switch from Reference clock to 2X the frequency of Reference clock if Bank B is connected to feedback FBK. For testing purposes, the select inputs connect the input clock directly to outputs.
Block Diagrams
/2
REF
PLL
MUX
FBK CLKA1 CLKA2 CLKA3 CLKA4
/2
Extra Divider (-3, -4)
S2 S1
Select Input Decoding
CLKB1
Extra Divider (-2,-3)
CLKB2 CLKB3 CLKB4
PI6C2308A (-1, -1H, -2, -3, -4)
Pin Configuration PI6C2308A (-1, -1H, -2, -3, -4, -6)
REF
PLL
MUX
FBK CLKA1 CLKA2 CLKA3
REF CLKA1 CLKA2 VDD 1 2 3 4 5 6 7 8 16 15 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
S2 S1
Select Input Decoding /2 MUX
CLKA4
16-Pin 13 W, L
12 11 10 9
14
GND CLKB1
CLKB1
CLKB2 S2
PI6C2308A-6
CLKB2 CLKB3 CLKB4
1
PS8385B
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PI6C2308A 3.3V Zero Delay Buffer
Select Input Decoding for PI6C2308A (-1, -1H, -2, -3, -4)
S2 0 0 1 1 S1 0 1 0 1 CLKA [1-4] Hi- Z Driven Driven Driven CLKB [1-4] Hi- Z Hi- Z Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N
Select Input Decoding for PI6C2308A-6
S2 0 0 1 1 S1 0 1 0 1 CLKA [1-4] Hi- Z Driven = Reference Driven = PLL Driven = PLL CLKB [1-4] Hi- Z Driven = Reference/2 Driven = PLL Driven = PLL/2 Output Source PLL Reference PLL PLL PLL Shutdown Y Y N N
Available PI6C2308A Configurations
De vice PI6C2308A- 1 PI6C2308A- 1H PI6C2308A- 2 PI6C2308A- 2 PI6C2308A- 3 PI6C2308A- 3 PI6C2308A- 4 PI6C2308A- 6 PI6C2308A- 6 Fe e dback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A Bank B Bank A Fre que ncy Reference Reference Reference 2X Reference 2X Reference 4X Reference 2X Reference Reference Reference or 2X Reference Bank B Fre que ncy Reference Reference Reference/2 Reference Reference 2X Reference 2X Reference Reference or Reference/2 Reference
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REF - Input to CLKA/CLKB Delay (ps)
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PI6C2308A 3.3V Zero Delay Buffer
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay vs. Difference in Loading between FBK pin and CLKA/CLKB pins
800
600
400
200
0 -25 -200 -20 -15 -10 -5 0 5 10 15 20 25
-400
PI6C2308A-1H
-600
-800
PI6C2308A-1,2,3,4,6
-900
-1000
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the PI6C2308A, the FBK pin can be driven from any of the 8 available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs.
Maximum Ratings
Supply Voltage to Ground Potential ...................................................0.5V to +7.0V DC Input Voltage (Except REF) .................................................. 0.5V to VDD +0.5V DC Input Voltage REF ................................................................................ 0.5 to 7V Storage Temperature ........................................................................ 65C to +150C Maximum Soldering Temperature (10 seconds) ................................................ 260C Junction Temperature ....................................................................................... 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................. >2000V
Operating Conditions (over the operating range, TA = 0C to +70C, VCC = 3.3V 0.3V)
Parame te r VDD TA Cl Cin De s cription Supply Voltage Operating Temperature (Ambient) Load Capacitance Input Capacitance M in. 3.0 0 M ax. 3.6 70 30 7 Units V C pF
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PI6C2308A 3.3V Zero Delay Buffer
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF(1) C LK A1(2) C LK A2(2) VDD GN D C LK B1(2) C LK B2(2) S2(3) S1(3) C LK B3(2) C LK B4(2) GN D VDD C LK A3(2) C LK A4(2) FBK Signal D e s cription Input reference frequency, 5VTolerant input, allows spread spectrum clock input C lock output, Bank A C lock output, Bank A 3.3V supply Ground C lock output, Bank B C lock output, Bank B Select input, bit 2 Select input, bit 1 C lock output, Bank B C lock output, Bank B Ground 3.3V, supply C lock output, Bank A C lock output, Bank A PLL feedback input
Electrical Characteristics for Commercial Temperature Device
Parame te r VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD IDD De s cription Input LOW Voltage(4) Input HIGH Voltage(4) VIN = 0V VIN = VDD IOL = 8mA IOL = 12mA (- 1H) IOH = 8mA IOH = 12mA (- 1H) REF = 0 MHz Unloaded outputs, 66.66 MHz, Select inputs at VDD or GND Unloaded outputs, 100 MHz, Select inputs at VDD or GND Input LOW Current Input HIGH Current Output LOW Voltage(5) Output HIGH Voltage(5) Te s t Conditions M in. 2.0 2.4 M ax. 0.8 50.0 200.0 0.4 V 12.0 39 mA 54 A Units V A
Power Down Supply Current Supply Current Supply Current
4
PS8385B
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PI6C2308A 3.3V Zero Delay Buffer
Switching Characteristics(5,6) for Commercial Temperature Device
Parame te rs FCLK N ame O utput Frequency Duty C ycle(5) = t2 / t1 t2 Duty C ycle(5) = t2 / t1 (- 1H) Duty C ycle = t2 / t1 (- 1,- 2,- 3,- 4,- 6) t3 t3 t3 t4 t4 t4 t5 t5 t6 t7 Rise Time(5) @30pF Rise Time(5) @15pF Rise Time(5) @30pF (- 1H) Fall Time(5) @30pF Fall Time(5) @15pF Fall Time(5) @30pF (- 1H) O utput to O utput Skew(5) same bank O utput to O utput Skew(5) different bank (2,3,6) Delay, REF Rising Edge to FBK Rising Edge(5) Device to Device Skew(5) O utput Slew Rate(5) C ycle to C ycle Jitter(5) PLL Lock Time(5) All outputs equally loaded, VDD/2 All outputs equally loaded, VDD/2 Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on - 1H device using Test C ircuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clocks presented on REF and FBK pins 1 0 0 Measured between 0.8V and 2.0V Te s t Conditions 15pF to 30pF load Measured at VDD/2 Measured at 1.4V, FO UT 45 MHz Measured at 1.4V M in. 10 45 45 40 50 50 50 Typ. M ax. 140 55 55 60 2. 2 1. 5 1. 5 2. 2 1. 5 1. 2 5 200 400 ps 15 0 500 ns % Units MHz
t8
V/ns
tJ tLO CK
200 1. 0
ps ms
Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. REF and FBK inputs have a threshhold voltage of VDD/2. 5. Parameter is guaranteed by design and characterization. Not 100% tested in production. 6. For definition of t1-8, see Switching Waveforms on page 6
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PS8385B
08/03/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308A 3.3V Zero Delay Buffer
Operating Conditions for Industrial Temperature Devices
Parame te r VDD TA CL CIN Supply Voltage O perating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance D e s cription M in. 3.0 40 M ax. 3.6 85 30 15 7 pF Units V C
Electrical Characteristics for Industrial Temperature Devices
Parame te r VIL VIH IIL IIH VOL VOH IDD (PD mode) De s cription Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage(4) Output HIGH Voltage(4) Power Down Supply Current VIN = 0V VIN = VDD IOL = 8 mA (1,2,3,4) IOL = 12 mA (1H,5) IOH = 8 mA (1,2,3,4) IOH = 12 mA (1H,5) REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs at VDD or GND IDD Supply Current Unloaded outputs, 66 MHz, REF, except 1H Unloaded outputs, 33 MHz, REF, except 1H 2.4 25.0 45.0 70.0 (1H) 35.0 20.0 mA A 2.0 50.0 100.0 0.4 V Te s t Conditions M in. M ax. 0.8 Units V
A
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PS8385B
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PI6C2308A 3.3V Zero Delay Buffer
Switching Characteristics for Industrial Temperature Devices(5)
Parame te r Name 30pF load, All devices t1 O utput Frequency 20pF load, 1H, 5, devices 15pF load, 1,2,3,4 devices t2 Duty Cycle(4) = t2 / t1 (1,2,3,4) Measured at 1.4V, FOUT <66.66MHz 30- pF load Measured at 1.4V, FOUT <100 MHz 15- pF load Measured at 1.4V, FOUT <133 MHz 15- pF load Duty Cycle(4) = t2 / t1 (1H,5) Measured at 1.4V, FOUT < 45MHz Measured at 1.4V, FOUT <66.66 MHz 15- pF load Measured at 1.4V, FOUT <45MHz Measured between 0.8V and 2.0V, 30- pF load Measured between 0.8V and 2.0V, 15- pF load Measured between 0.8V and 2.0V, 30- pF load Measured between 0.8V and 2.0V, 30- pF load Measured between 0.8V and 2.0V, 15- pF load Measured between 0.8V and 2.0V, 30- pF load 40.0 35.0 40.0 45.0 2.2 1.50 1.50 2.50 1.50 1.25 ns 10 Te s t Conditions M in. Typ. M ax. Units 100 140 140 60.0 MHz
50.0 55.0
%
Duty Cycle(4) = t2 / t1 (1H,5) Rise Time t3
(4) (4)
(1,2,3,4) (1,2,3,4)
Rise Time
Rise Time(4) (1H,5) Fall Time(4) t4 (1,2,3,4) Fall Time(4) (1,2,3,4) Fall Time(4) (1H,5) O utput to O utput Skew on same Bank (1,2,3,4)(4) O utput to O utput Skew (1H,5) t5 O utput Bank A to O utput Bank B Skew (1, 4, 5) O utput Bank A to O utput Bank B Skew (2, 3) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge(4) Device to Device Skew(4) O utput Slew Rate(4) Cycle to Cycle Jitter(4), (1, 1H,5, 4) Cycle to Cycle Jitter(4), (2,3) Cycle to Cycle Jitter(4), (2,3) tLOCK PLL Lock Time(4)
200 All outputs equally loaded ps 400 Measured at VDD/2 Measured at VDD/2 MHz, on the FBK pins of devices Measured twx 0.8V & 2.0V on 1H,5 device using Test Circuit #2. Measured at 66.67 MHz, loaded outputs, 30pF Load Measured at 66.67 MHz, loaded outputs, 15pF Load Measured at 66.67 MHz, loaded outputs Stable power supply, valid clocks presented on REF and FBK pins 1 200 100 400 1.0 ms ps 0 150 500 V/ns
tJ
Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. REF and FBK inputs have a threshhold voltage of VDD/2. 5. Parameter is guaranteed by design and characterization. Not 100% tested in production. 6. For definition of t1-8, see Switching Waveforms on page 6
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PS8385B 08/03/00
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PI6C2308A 3.3V Zero Delay Buffer
Switching Waveforms
Duty Cycle Timing
t1 t2
1.4V 1.4V 1.4V
All Outputs Rise/Fall Time
OUTPUT 2.0V 0.8V 2.0V 0.8V 3.3V 0V
t3
t4
Output-Output Skew
OUTPUT 1.4V
OUTPUT
1.4V
t5
Input-Output Propagation Delay
INPUT VDD/2
FBK
VDD/2
t6
Device-Device Skew
FBK Device 1 VDD/2
FBK Device 2
VDD/2
t7
Test Circuit #1
0.1mF
VDD OUTPUTS CLK out CLOAD
Test Circuit #2
0.1mF
VDD OUTPUTS 1kW 1kW CLK out 10pF
0.1mF
VDD GND GND
0.1mF
VDD GND GND
Test Circuit for all parameters except t 8
Test Circuit for t 8 ,Output slew rate on -1H device
8
PS8385B
08/03/00
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PI6C2308A 3.3V Zero Delay Buffer
Package Diagrams
16-Pin SOIC (W)
16
.149 .157
3.78 3.99
1 .386 .393 9.80 10.00 0-8 .0155 .0260 0.393 0.660 REF .053 .068 1.35 1.75 SEATING PLANE 0.41 1.27 .0099 .0196
0.25 x 45 0.50
.0075 .0098 .016 .050
0.19 0.25
.050 BSC 1.27
.013 .020 0.330 0.508
.0040 0.10 .0098 0.25
.2284 .2440 5.80 6.20
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
16-Pin TSSOP (L)
16
.169 .177
4.3 4.5
1 .193 .201 4.9 5.1 .047 max. 1.20 SEATING PLANE 0.45 .018 0.75 .030 .252 BSC 6.4 .004 .008 0.09 0.20
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC
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PS8385B
08/03/00
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PI6C2308A 3.3V Zero Delay Buffer
Ordering Information (Commercial Temperature Device)
Orde ring Code PI6C2308A- 1W PI6C2308A- 1HW PI6C2308A- 2W PI6C2308A- 3W PI6C2308A- 4W PI6C2308A- 6W PI6C2308A- 1L PI6C2308A- 1HL PI6C2308A- 2L PI6C2308A3L PI6C2308A4L PI6C2308A- 6L L16 16- pin TSSO P Commercial W16 16- pin 150- mil SOIC Package Name Package Type Ope rating Range
Ordering Information (Industria l Temperature Device)
Orde ring Code PI6C2308A- 1WI PI6C2308A- 1HWI PI6C2308A- 2WI PI6C2308A- 3WI PI6C2308A- 4WI PI6C2308A- 6WI PI6C2308A- 1LI PI6C2308A- 1HLI PI6C2308A- 2LI PI6C2308A- 3LI PI6C2308A- 4LI PI6C2308A- 6LII L16 16- pin TSSO P Industrial W16 16- pin 150- mil SO IC Package Name Package Type Ope rating Range
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS8385B 08/03/00

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