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IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES:
Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages - Extended commercial range of -40C to +85C - VCC = 3.3V 0.3V, Normal Range - VCC = 2.7V to 3.6V, Extended Range - CMOS power levels (0.4 W typ. static) - All inputs, outputs and I/O are 5 Volt tolerant - Supports hot insertion Drive Features for LVCH16260A: - High Output Drivers: 24mA - Reduced system switching noise - -
IDT74LVCH16260A
bus multiplexer/transceiver for use in high-speed microprocessor applications. This bus exchanger supports memory interleaving with latched outputs on the B ports and address multiplexing with latched inputs on the B ports. The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage. When a latch-enable input is high, the latch is transparent. When a latchenable input is low, the data at the input is latched and remains latched until the latch enable input is returned high. Independent output enables (OE1B and OE2B) allow reading from one port while writing to the other port. All pins of the 12-bit Bus Exchanger can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. The LVCH16260A has been designed with a 24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16260A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
DESCRIPTION:
The LVCH16260A tri-port bus exchanger is built using advanced dual metal CMOS technology. The LVCH16260A is a high-speed 12-bit latched
Functional Block Diagram
OE1B
29
LEA1B
30
A-1B LATCH
12
1B1:12
LE1B
2
12
28 1
1B-A LATCH
12
12
SEL OEA
A1:12
12
M U X
1
0
12
27
12
LE2B
2B-A LATCH
12
55
LEA2B
56
A-2B LATCH
2B1:12
12
OE2B
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4229/1
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 LE2B SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 SO 56-1 SO 56-2 43 SO 56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OE2B LEA2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 LEA1B OE1B
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND
(1)
Unit V V C mA mA mA
LVC Link
Max. - 0.5 to +6.5 - 0.5 to +6.5 - 65 to +150 - 50 to +50 - 50 100
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
LVC Link
NOTE: 1. As applicable to the device type.
SSOP/ TSSOP/ TVSOP TOP VIEW
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLES
1Bx H L X X X X X 2Bx X X X H L X X Inputs SEL LE1B H H H L L L X H H L X X X X
(1)
Outputs Ax H L A0
(2)
Inputs Ax H L H L H L X X X X X LEA1B LEA2B H H H H L L L X X X X H H L L H H L X X X X OE1B L L L L L L L H L H L OE2B L L L L L L L H H L L 1Bx H L H L B0(2) B0(2) B0
(2)
Outputs 2Bx H L B0(2) B0(2) H L B0(2) Z Z Active Active
LE2B X X X H H L X
OEA L L L L L L H
H L A0(2) Z
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance 2. A0, B0 = Output level before the indicated steady-state input conditions were established.
Z Active Z Active
PIN DESCRIPTION
Signal A(1:12) 1B(1:12) 2B(1:12) LEA1B LEA2B LE1B LE2B SEL OEA OE1B OE2B I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1) Bidirectional Data Port 1B. Connected to the even path or even bank of memory.(1) Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.(1) Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA1B. Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA2B. Latch Enable Input for 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH to LOW transition of LE1B. Latch Enable Input for 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH to LOW transition of LE2B. 1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port to A Port. Output Enable for A Port (Active LOW). Output Enable for 1B Port (Active LOW). Output Enable for 2B Port (Active LOW).
NOTE: 1. These pins have "Bus-hold". All other pins are standard inputs, outputs, or I/Os.
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IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40OC to +85OC
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC 3.6 VIN 5.5V(2) Quiescent Power Supply Current Variation One input at VCC - 0.6V other inputs at VCC or GND -- -- -- -- -- -- -- - 0.7 100 -- -- -- 50 - 1.2 -- 10 10 500 A
LVC Link
Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VI = 0 to 5.5V VO = 0 to 5.5V
Min. 1.7 2 -- -- -- --
Typ.(1) -- -- -- -- -- --
Max. -- -- 0.7 0.8 5 10
Unit V V A A A V mV A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
LVC Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
VCC = 3.0V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2.0V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 -- -- --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
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IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55
LVC Link
Unit V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to +85C.
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per bus exchanger Outputs enabled Power Dissipation Capacitance per bus exchanger Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical Unit pF pF
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay AX to 1BX or Ax to 2BX Propagation Delay 1BX to AX or 2BX to AX Propagation Delay LEXB to AX Propagation Delay LEA1B to 1BX or LEA2B to 2BX Propagation Delay SEL to AX Output Enable Time OEA to AX, OE1B to 1BX, or OE2B to 2BX Output Disable Time OEA to AX, OE1B to 1BX, or OE2B to 2BX Set-Up Time, HIGH or LOW Data to Latch Hold Time, Latch to Data Pulse Width, Latch HIGH Output Skew (2)
(1)
VCC = 2.7V0.2V Min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1 1.2 3 -- Max. 5.7 6.1 6.1 6.1 6.3 6.7 5.9 -- -- -- -- Min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1 1 3 -- VCC = 3.3V0.3V Max. 5 5.2 5.2 5 5.2 5.5 5.2 -- -- -- 500 Unit ns ns ns ns ns ns ns ns ns ns ps
NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
5
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V 0.3V 6 2.7 1.5 300 300 50 VCC(1) = 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V 0.2V Unit 2 x Vcc V Vcc VCC / 2 150 150 30 V V mV mV pF
LVC Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 Pulse (1, 2) Generator VIN D.U.T. 500 CL VOUT VLOAD Open GND
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC Link
RT
LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTE: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT TIM ING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM tSU tH VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
GND Open
LVC Link
tSU
OUTPUT SKEW - tsk (x)
INPUT tPLH1 tPHL1
tH
VIH VT 0V VOH
PULSE WIDTH
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT
LVC Link
OUTPUT 1
tSK (x)
tSK (x)
VT VOL VOH
VT
OUTPUT 2 tPLH2 tPHL2
VT VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
LVC Link
6
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX LVC X Bus-Hold XX Family XXXX Device Type XX Package Temp. Range
PV PA PF 260A 16
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 12-Bit Tri-Port Bus Exchanger Double-D ensity with Resistors, 24m A
H 74
Bus-hold -40C to +85C
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