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MDT10C61
1. General Description
This ROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power u u LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) u 13 I/O pins with their own independent direction control
consump-tion and high noise immunity. On chip memory incl-udes 1K words of ROM, and 68 bytes of static RAM.
2. Features 3. Applications
The followings are some of the features on the hardware and software : u u u u Fully CMOS static design 8-bit data bus On chip ROM size : 1.0 K words Internal RAM size : 81 bytes (68 general purpose registers, 13 special registers) u u u u u u 37 single word instructions 14-bit instructions 8-level stacks Operating voltage : 2.5 V ~ 5.5 V Operating frequency : DC ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u u u u Power-on Reset Power edge-detector Reset Sleep Mode for power saving 3 interrupt sources: -External INT pin -TMR0 timer -PortB<7:4> interrupt on change u 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw The application areas of this MDT10C61 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
P. 1
2005/6
Ver. 1.7
MDT10C61
4. Pin Assignment DIP / SOP PA2 1 18 PA3 2 17 PA4/RTCC 3 16 /MCLR 4 15 Vss 5 14 PB0/INT 6 13 PB1 7 12 PB2 8 11 PB3 9 10 5. Pin Function Description
Pin Name PA0~PA3 PB0~PB7 I/O I/O I/O Port A, TTL input level Port B, TTL input level / PB0:External interrupt input , PB4~PB7:Interrupt on pin change RTCC/PA4 I/O Real Time Clock/Counter, Schmitt Trigger input levels Open drain output /MCLR OSC1 OSC2 Vdd Vss I I O Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground Function Description
PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
PA2 PA3 RTCC /MCLR VSS VSS PB0 PB1 PB2 PB3
SSOP 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11
PA1 PA0 OSC1 OSC2 VDD VDD PB7 PB6 PB5 PB4
6. Memory Map (A) Register Map
Address BANK0 00 01 02 03 04 Indirect Addressing Register RTCC PCL STATUS MSR Description
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2005/6
Ver. 1.7
MDT10C61
Address 05 06 0A 0B 0C~4F BANK1 01 05 06 TMR CPIO A CPIO B Port A Port B PCHLAT INTS General purpose register Description
(1)IAR ( Indirect Address Register) : R00 (2)RTCC (Real Time Counter/Counter Register) : R01 (3) PC (Program Counter) : R02,R0A Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET,RTFI --- from STACK
A9
A8
A7~A0
Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK (4) STATUS (Status register) : R03
Bit
0 1 2 3 4 5
Symbol
C HC Z PF TF RBS0 Carry bit Half Carry bit Zero bit
Function
Power down Flag bit WDT Timer overflow Flag bit Register Bank Select bit : 0 : 00H --- 7FH 1 : 80H --- FFH
7~6
XX
General purpose bit
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 3
2005/6
Ver. 1.7
MDT10C61
(5) MSR (Memory Bank Select Register) : R4 Memory Bank Select Register : 0 : 00~7F 1 : 80~FF
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode (6) PORT A : R05 PA4~PA0, I/O Register (7) PORT B : R06 PB7~PB0, I/O Register (8)PCHLAT : R0A
(9) INTS ( Interrupt Status Register ) : R0B
Bit 0 1 2 3
Symbol RBIF INTF TIF RBIE
Function PORT B change interrupt flag. Set when PB <7:4> inputs change Set when INT interrupt occurs. INT interrupt flag. Set when TMR overflows. 0 : disable PB change interrupt 1 : enable PB change interrupt
4
INTS
0 : disable INT interrupt 1 : enable INT interrupt
5
TIS
0 : disable TMR interrupt 1 : enable TMR interrupt
6 7
-GIS
Unimplemented 0 : disable global interrupt 1 : enable global interrupt
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 4
2005/6
Ver. 1.7
MDT10C61
(10) TMR (Time Mode Register) : R81 Bit Symbol Prescaler Value 000 001 010 011 2X0 PS2X0 100 101 110 Function RTCC rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64
3
PSC
4
TCE
5
TCS
6
IES
7
PBPH
111 1 : 256 1 : 128 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin Interrupt edge select 0 X Interrupt on falling edge on PB0 1 X Interrupt on rising edge on PB0 PORTB pull-hi 0 X PORTB pull-hi are enable 1 X PORTB pull-hi are disable
(11) CPIO A (Control Port I/O Mode Register) : R85 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (12) CPIO B (Control Port I/O Mode Register) : R86 x"0", I/O pin in output mode; x"1", I/O pin in input mode.
(13) Configurable options for ROM:
Oscillator Type RC Oscillator
HFXT Oscillator XTAL Oscillator LFXT Oscillator
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 5
2005/6
Ver. 1.7
MDT10C61
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
Oscillator-start Timer control 0ms 75ms
Power-edge Detect PED Disable PED Enable (B) Program Memory
Address 000-3FF 000 004 Program memory
Description
The starting address of power on, external reset or WDT time-out reset. Interrupt vector
7. Reset Condition for all Registers
Register IAR RTCC PC STATUS MSR PORT A PORT B INTS TMR CPIOA CPIOB PSTA Address 00h 01h 0Ah,02h 03h 04h 05h 06h 0Bh 81h 85h 86h 87h Power-On Reset, xxxx xxxx 00 0000 0000 0001 1xxx xxxx xxxx - - -1 xxxx xxxx xxxx 0000 0001 1111 1111 - - -1 1111 1111 1111 - - - - - -qq /MCLR or WDT Reset uuuu uuuu 00 0000 0000 000# #uuu uuuu uuuu - - -1 uuuu uuuu uuuu 0000 000u 1111 1111 - - -1 1111 1111 1111 - - - - - -uu Wake-up from SLEEP uuuu uuuu PC+1 000# #uuu uuuu uuuu - - -u uuuu uuuu uuuu uuuu uuuu uuuu uuuu - - -u uuuu uuuu uuuu - - - - --uu
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 6
2005/6
Ver. 1.7
MDT10C61
Note : uxunchanged, xxunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table
Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Power on reset
Status: bit 4 u 1 0 0 1
Status: bit 3 u 0 1 0 1
Status: bit 1 1 1 1 1 0
Status: bit 0 1 1 1 1 X
8. Instruction Set :
Instruction Code Mnemonic Operands No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return from subroutine Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Function None 0/WT 0/WT, stop OSC W/TMODE Stack/PC W/CPIO r W/R R/t I/W [R(0~3)R(4~7)]/t R + 1/t R + 1/t W + R/t R W/t or (R+/W+1/t) R 1/t R 1/t R a W/t i a W/W R a W/t i a W/W R o W/t i o W/W /R/t TF, PF TF, PF None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z Operating Status
010000 00000000 NOP 010000 00000001 CLRWT 010000 00000010 SLEEP 010000 00000011 TMODE 010000 00000100 RET 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t
DECRSZ R, t Decrement register, skip if zero ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 7
2005/6
Ver. 1.7
MDT10C61
Instruction Code 010110 trrrrrrr 010101 trrrrrrr Mnemonic Operands RRR RLR R, t R, t Function Rotate right register Rotate left register Clear working register R R, b R, b Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W Return, place immediate to W Subtract W from immediate Reture from interrupt Operating R(n) /R(n-1), C/R(7), R(0)/C R(n)/r(n+1), C/R(0), R(7)/C 010000 1xxxxxxx CLRW 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr CLRR BCR BSR 0/W 0/R 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/Stack n/PC W+i/W Stack/PC,i/W i-W/W Stack/PC,1/GIS Z Z None None None None None None C,HC,Z None C,HC,Z None C Status C
BTSC R, b BTSS R, b
100nnn nnnnnnnn LCALL n 101nnn nnnnnnnn LJUMP n 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii ADDWI i RTWI i
SUBWI i
010000 00001001 RTFI
Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` a' Exclusive ` o' Logic AND ` a' b t : : 0 1 : : : : : : : : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
R C HC Z / x i n
9. Electrical Characteristics
*Note: Temperature=25C 1. Operation Current :
(1) HF (C=10p) , WDT - enable, 4M 2.5V 3.0V 4.0V 300u 410u 650u 10M 670u 880u 1.4m 20M 1.4m 1.8m 2.6m Sleep 1u 2.5u 6.4u
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 8
2005/6
Ver. 1.7
MDT10C61
4M 5.0V 6.4V 1m 1.5m 10M 1.9m 2.8m 20M 3.4m 4.9m Sleep 12u 26u
These parameters are for reference only.
(2) XT (C=10p) , WDT - enable 1M 2.5V 3.0V 4.0V 5.0V 6.4V 100u 135u 240u 400u 720u 4M 300u 380u 600u 900u 1.4m 10M 700u 850u 1.35m 1.8m 2.6m Sleep 1u 2.5u 6.4u 12u 26u
These parameters are for reference only.
(3) RC, WDT - Enable; @Vdd = 5.0V C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k 4.7k 10k 100p 47k 100k 300k 470k Freq. 10.2M 5.64M 1.35M 654K 223K 144K 4.78M 2.47M 560K 268K 90K 58K 1.43M 721K 158K 75.4K 25.2K 16.2K Current 1.8m 1.1m 300u 180u 100u 80u 900u 500u 150u 100u 70u 60u 320u 200u 90u 70u 60u 55u
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 9
2005/6
Ver. 1.7
MDT10C61
C R 4.7k 10k 300p 47k 100k 300k 470k Freq. 641K 320K 70K 33.3K 11.1K 7.1K Current 180u 120u 70u 60u 50u 48u
These parameters are for reference only.
(4) LF (C=10p) , WDT - enable, 32K 2.5V 3.0V 4.0V 5.0V 6.4V 5u 8u 19u 45u 190u 455K 40u 55u 85u 130u 195u 1M 80u 100u 150u 200u 300u Sleep 1u 2.5u 6.4u 12u 26u
These parameters are for reference only.
2. Input Voltage (Vdd = 5V) : Port Vil TTL Schmitt trigger Vih TTL Schmitt trigger These parameters are for reference only. Min Vss Vss 2.2V 3.5V Max 1.0V 1.0V Vdd Vdd
3. Output Voltage (Vdd = 5V) : PA,PB Voh Vol Voh Vol 3.7V 0.5V 4.6V 0.3V Condition Ioh = -20mA Iol = 20mA Ioh = -5mA Iol = 5mA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
2005/6
Ver. 1.7
MDT10C61
4. Output Current (Max.) (Vdd = 5V) : Port A: source current sink current Current 30mA 50mA
Port B: source current sink current These parameters are for reference only.
Current 30mA 50mA
5. The basic WDT time-out cycle time : time 2.5V 3.0V 4.0V 5.0V 6.3V Unit = ms These parameters are for reference only. 25 22 19 17 15
6. Min Operation Voltage : C => XT, 20M HF, 20M 10p 2.5 2.5 20p 2.5 2.5 Unit = V RC, 1k, no cap. Unit = V C => LF, 1M 0p 2.6 10p 2.9 Unit = V These parameters are for reference only. 20p 3.1 2.5 30p 2.5 2.5
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 11
2005/6
Ver. 1.7
MDT10C61
8. Pull high/low resistor : Vdd 5V 3V
Hardware Pull high 100+-20% 200+-20% Hardware Pull low 100+-20% 200+-20% Software pull high 50+-20% 100+-20%
Unit = kOhm These parameters are for reference only.
9. MCLR filter time : Vdd=5V time Unit = ns These parameters are for reference only. 600
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 12
2005/6
Ver. 1.7

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