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| KL5KUSB200 USB2.0 Transceiver General Description The Kawasaki USB 2.0 Compliant Transceiver is the interface between the high performance USB serial bus and the 16-bit SIE bus. The high-speed analog interface and the digital serial bit processing feature of the USB 2.0 transceiver enables a highly integrated USB 2.0 device. The transceiver is controlled by input signals from the SIE bus which is synchronized with the 30MHz clock output. The Kawasaki Transceiver also provides output signals to monitor the USB bus status. The Kawasaki Transceiver, SIE, and logic design are combined to create Kawasaki's USB chip solutions for peripheral devices or can be used as IP with our ASIC technology. Features * * * * * * * USB 2.0 compliant transceiver UTMI based design (USB 2.0 Transceiver Macro cell Interface) Generates 48MHz to 480MHz input Full Speed / High Speed capabilities Supports "Chirp" for High Speed recognition Support Reset and Suspend Operational mode selection * * * * * * * Status signals for monitoring USB bus Optional CRC verification/generation logic Mode bit expansion for device test 16 bit Bi-directional SIE bus TX data packet abort ASIC IP supports High speed SIE with ASIC IP 80 pin LQFP package (12 mm2) Block Diagram USB Bus HSDP HSDM SIE Bus High Speed Front end HS DLL EBUF Shared Logic SIE Interface Control Signals Status CKOUT SIE_Data RPU_ENA FSDP FSDM Full Speed Front end DPLL External 48MHz Clk Clock Generator US: Kawasaki LSI , 2570 N. 1st Street, San Jose, CA 95131,Tel:(408) 570-0555, Fax(408) 570-0567, www.klsi.com Japan: Kawasaki Steel Corp, Makuhari Techno-Garden B5, Nakase 1-3, Mihama-ku, Chiba, 261-8501Tel:(043)296-3283, Fax:(043)296-3285, email:usb-info@lsidv.kawasaki-steel.co.jp Ver. 2.2 1 KL5KUSB200 USB2.0 Transceiver Pin Diagram 80LQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 0GND XOUT XIN 0VDD RXACT RXVLD 0GND CRCERR RXERR TXRDY WDVLD ICVDD CGND TXACT CRCACT IGND FS_HSN PU_SEON ICVDD CGND A1VDD 1 A1GND 2 A2VDD 3 A2GND 4 REXT 5 RPU_ENA 6 UVDD 7 UGND 8 FSDP 9 HSDP 10 HSDM 11 FSDM 12 UGND 13 UVDD 14 ICVDD 15 MODE[0] 16 MODE[1] 17 IGND 18 MODE[2] 19 MODE[3] 20 KL5KUSB200 USB 2.0 Transceiver 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SIE_DAT[15] CKOUT 0VDD 0GND ICVDD CGND SIE_DAT[14] SIE_DAT[13] IGND SIE_DAT[12] CGND SIE_DAT[11] SIE_DAT[10] 0VDD 0GND ICVDD CGND SIE_DATA[9] SIE_DATA[8] SIE_DATA[7] Application Block Diagram HS D+ HS DRpu D+ RPU_ENA RSTN 21 SUSPN 22 BSTAT[0] 23 BSTAT[1] 24 SIE_DAT[0] 25 0VDD 26 0GND 27 SIE_DAT[1] 28 SIE_DAT[2] 29 IGND 30 SIE_DAT[3] 31 ICVDD 32 CGND 33 SIE_DAT[4] 34 0GND 35 0VDD 36 SIE_DAT[5] 37 SIE_DAT[6] 38 ICVDD 39 CGND 40 SIE Block KL5KUSB200 Control Logic Endpoint Buffer User Logic Rs D- Rs Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice form Kawasaki LSI Oct 2000 * (c)Copyright 2000 * Kawasaki LSI * Printed in U.S.A US: Kawasaki LSI , 2570 N. 1st Street, San Jose, CA 95131,Tel:(408) 570-0555, Fax(408) 570-0567, www.klsi.com Japan: Kawasaki Steel Corp, Makuhari Techno-Garden B5, Nakase 1-3, Mihama-ku, Chiba, 261-8501Tel:(043)296-3283, Fax:(043)296-3285, email:usb-info@lsidv.kawasaki-steel.co.jp Ver. 2.2 2 |
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